1    Architecture-Based Considerations

This chapter describes programming considerations that are determined by the Alpha system architecture. It addresses the following topics:

• Registers (Section 1.1)

• Bit and byte ordering (Section 1.2)

• Addressing (Section 1.3)

• Exceptions (Section 1.4)

1.1    Registers

This section discusses the registers that are available on Alpha systems and describes how memory organization affects them. See Section 6.3 for information on register use and linkage.

Alpha systems have the following types of registers:

• Integer registers

• Floating-point registers

You must use integer registers where the assembly instructions expect integer registers and floating-point registers where the assembly instructions expect floating-point registers. If you confuse the two, the assembler issues an error message.

The assembler reserves all register names (see Section 6.3.1). All register names start with a dollar sign ($) and all alphabetic characters in register names are lowercase.

1.1.1    Integer Registers

Alpha systems have 32 integer registers, each of which is 64 bits wide. Integer registers are sometimes referred to as general registers in other system architectures.

The integer registers have the names $0 to $31.

By including the file regdef.h (use #include <alpha/regdef.h>) in your assembly language program, you can use the software names of all of the integer registers, except for $28, $29, and $30. The operating system and the assembler use the integer registers $28, $29, and $30 for specific purposes.

Note

If you need to use the registers reserved for the operating system and the assembler, you must specify their alias names in your program, not their regular names. The alias names for $28, $29, and $30 are $at, $gp, and $sp, respectively. To prevent you from using these registers unknowingly and thereby producing potentially unexpected results, the assembler issues warning messages if you specify their regular names in your program.

The $gp register (integer register $29) is available as a general register on some non-Alpha compiler systems when the -G 0 compilation option is specified. It is not available as a general register on Alpha systems under any circumstances.

Integer register $31 always contains the value 0. All other integer registers can be used interchangeably, except for integer register $30, which is assumed to be the stack pointer by certain PALcode instructions. See Table 6-1 for a description of integer register assignments. See Appendix D and the Alpha Architecture Handbook for information on PALcode (Privileged Architecture Library code).

1.1.2    Floating-Point Registers

Alpha systems have 32 floating-point registers, each of which is 64 bits wide. Each register can hold one single-precision (32-bit) value or one double-precision (64-bit) value.

The floating-point registers have the names $f0 to $f31.

Floating-point register $f31 always contains the value 0.0. All other floating-point registers can be used interchangeably. See Table 6-2 for a description of floating-point register assignments.

1.2    Bit and Byte Ordering

A system's byte-ordering scheme, or endian scheme, affects memory organization and defines the relationship between address and byte position of data in memory:

• Big-endian systems store the sign bit in the lowest address byte.

• Little-endian systems store the sign bit in the highest address byte.

Figure 1-1:  Byte Ordering

Alpha systems use the little-endian scheme. Byte-ordering is as follows:

• The bytes of a quadword are numbered from 7 to 0. Byte 7 holds the sign and most significant bits.

• The bytes of a longword are numbered from 3 to 0. Byte 3 holds the sign and most significant bits.

• The bytes of a word are numbered from 1 to 0. Byte 1 holds the sign and most significant bits.

The bits of each byte are numbered from 7 to 0, using the format shown in Figure 1-1. (Bit numbering is a software convention; no assembler instructions depend on it.)

1.3    Addressing

This section describes the byte-addressing schemes for load and store instructions. (Section 2.8 describes the formats in which you can specify addresses.)

1.3.1    Aligned Data Operations

All Alpha systems use the following byte-addressing scheme for aligned data:

• Access to words requires alignment on byte boundaries that are evenly divisible by two.

• Access to longwords requires alignment on byte boundaries that are evenly divisible by four.

• Access to quadwords requires alignment on byte boundaries that are evenly divisible by eight.

Any attempt to address a data item that does not have the proper alignment causes an alignment exception.

The following instructions load or store aligned data:

• Load quadword (ldq)

• Store quadword (stq)

• Load longword (ldl)

• Store longword (stl)

• Load word (ldw)

• Store word (stw)

• Load word unsigned (ldwu)

1.3.2    Unaligned Data Operations

The assembler's unaligned load and store instructions operate on arbitrary byte boundaries. They all generate multiple machine-code instructions. They do not raise alignment exceptions.

The following instructions load and store unaligned data:

• Unaligned load quadword (uldq)

• Unaligned store quadword (ustq)

• Unaligned load longword (uldl)

• Unaligned store longword (ustl)

• Unaligned load word (uldw)

• Unaligned store word (ustw)

• Unaligned load word unsigned (uldwu)

• Load byte (ldb)

• Store byte (stb)

• Load byte unsigned (ldbu)

1.4    Exceptions

The Alpha system detects some exceptions directly, and other exceptions are signaled as a result of specific tests that are inserted by the assembler.

The following sections describe exceptions that you may encounter during the execution of assembly programs. Only those exceptions that occur most frequently are described.

1.4.1    Main Processor Exceptions

The following exceptions are the most common to the main processor:

• Address error exceptions occur when an address is invalid for the executing process or, in most instances, when a reference is made to a data item that is not properly aligned.

• Overflow exceptions occur when arithmetic operations compute signed values and the destination lacks the precision to store the result.

• Bus exceptions occur when an address is invalid for the executing process.

• Divide-by-zero exceptions occur when a divisor is zero.

1.4.2    Floating-Point Processor Exceptions

The following exceptions are the most common floating-point exceptions:

• Invalid operation exceptions include the following:

  • Magnitude subtraction of infinities, for example, (+INF) - (+INF).

  • Multiplication of 0 by INF with any signs.

  • Division of 0 by 0 or INF by INF with any signs.

  • Conversion of a binary floating-point number to an integer format, that is, only in those cases in which the conversion produces an overflow or an operand value of infinity or NaN. (The cvttq instruction converts floating-point numbers to integer formats.)

  • Comparison of predicates that have unordered operands and involve Less Than or Less Than or Equal.

  • Any operation on a signaling NaN. (See the introduction of Chapter 4 for a description of NaN symbols.)

• Divide-by-zero exceptions occur when a divisor is zero.

• Overflow exceptions occur when a rounded floating-point result exceeds the destination format's largest finite number.

• Underflow exceptions occur when a result has lost accuracy and also when a nonzero result is between ±2^Emin (plus or minus 2 to the minimum expressible exponent).

• Inexact exceptions occur if the infinitely precise result differs from the rounded result.

For additional information on floating-point exceptions, see Section 4.1.3.