2    Symmetrical Multiprocessing

2.1    Overview

Symmetrical multiprocessing (SMP) is the ability of two or more processes (or multiple threads of a threaded application) to execute simultaneously on two or more CPUs. This concurrency of execution greatly improves performance. Additionally, it affords customers the opportunity to extend the life and increase the cost-effectiveness of their multiprocessor systems by adding CPU cards (and their compute power) to their multiprocessors rather than buying more systems.

Digital UNIX supports an implementation of SMP that is designed to optimize the performance of compute servers (systems dedicated to compute-bound, multithreaded applications) and data servers (file servers, DBMS servers, TP systems, and mail routers that serve a large number of network clients). In addition, Digital UNIX supports multithreaded application development in an SMP environment. Note that SMP does not adversely affect using a multiprocessor as a timesharing system.

2.2    Implementation

The Digital UNIX SMP implementation makes use of simple locks (also called spin locks, since they "spin" for a specified period of time waiting for held locks to be freed before timing out), complex locks (read/write locks that can block waiting for a lock to be freed), and in very rare cases where locks would not be of benefit, funneling, whereby a process is forced to execute on a specified CPU.

The Digital UNIX SMP implementation also endeavors to achieve as much concurrency as possible by reducing the size of the system state that must be protected by locks, thereby reducing the necessity for locks and their attendant overhead.

Thus, both the kernel, and for the most part, the operating system as a whole, are fully parallelized so that multiple processes or multiple threads can run simultaneously on multiple CPUs. As these multiple processes or multiple threads execute, the operating system ensures--either through concurrency or through its locking strategy--that processes that access the same kernel data structures do so in a logical order so that the integrity of these data structures is maintained and that processes do not hold and request each other's locks, thereby deadlocking the system. There are no architectural limits on the number of CPUs supported.

Digital UNIX SMP also supports processor affinity, the ability to bind a particular process to a specified CPU, and load balancing, whereby the scheduler attempts to distribute all runable processes across all available CPUs. (Note that load balancing will not override processor affinity).

To improve performance, the scheduler also attempts to execute each process on the last CPU where it ran to take advantage of any state that may be left in that CPU's cache.

SMP is configurable and any of the following five modes can be configured at system boot time:

• Uniprocessing

• Optimized realtime preemption

• Optimized SMP

• Optimized realtime preemption and SMP

• Lock debug mode

When uniprocessing is set, only those locks necessary to support multiple threads are compiled into the kernel at system boot time.

When lock debug mode is set, the system checks the lock hierarchy and minimum system priority level (SPL); stores debugging information by classes and maintains lock statistics; records the simple locks that are held by each CPU in CPU-specific arrays; and records all of the complex locks that a thread is holding in the thread structure. All of this debugging information can be accessed through the dbx debugger.

In addition, the development environment has been enhanced to support multithreaded application development. Specifically the dbx, profile, and pixie utilities have had been extended to include support for multiple threads, and more thread-safe libraries have been added to the system.

For information on the Digital UNIX development environment and the threads package that Digital UNIX supports, see the Programmer's Guide and the Guide to DECthreads. For information on configuring SMP, see the System Administration guide and the System Tuning and Performance Management guide .