Hardware Interrupt Priorities--Background and Usage (99357)
This article was previously published under Q99357
SUMMARY
IBM PC-compatible computers (EISA-based or on the AT bus standard) use the
equivalent of two Intel-8259 style interrupt controllers. Each 8259 has
eight interrupt request (IRQ) inputs and a consolidated interrupt output.
The two 8259s are arranged in a master/slave configuration. The interrupt
output of the slave 8259 is cascaded through master controller IRQ input 2,
leaving a total of 15 interrupts available.
Controller priority works this way: if two simultaneous interrupts come in
on different interrupt lines, the interrupt request with the LOWER number
has HIGHER priority and is serviced first.
The master/slave configuration changes interrupt priority so that any
interrupt coming in on the slave interrupt controller has higher priority
then any interrupts on the master interrupt controller that are downstream
of IRQ 2.
Modification Type: |
Major |
Last Reviewed: |
7/30/2001 |
Keywords: |
KB99357 |
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