FIX: FWAIT Prefixes Generated for Processor Control Instructions (34774)

The information in this article applies to:

Microsoft Macro Assembler (MASM) 5.1
Microsoft Macro Assembler (MASM) 5.1a

This article was previously published under Q34774

SYMPTOMS

For a 80287 or 80387 processor, MASM should not be generating FWAIT prefixes for processor control instructions that do not have no-wait forms, including the following:

   FLDCW, FLDENV, FRSTOR, FINCSTP, FDECSTP, FFREE, and FNOP

STATUS

Microsoft has confirmed this to be problem in MASM versions 5.10 and 5.10a. This problem was corrected in MASM version 6.00.

MORE INFORMATION

The following is an example of the wait incorrectly generated by MASM for the FLDCW instruction. The fldcw generates the opcodes "9B D9 2D" when it should only generate "D9 2D" without the "9B" wait.

Sample Code

; Assemble options needed: none

   .386
   .387
   .model small
   .data

d1 DW 0

   .code
fldcw d1

   END

Modification Type:	Major	Last Reviewed:	10/29/2003
Keywords:	kbfix KB34774