PRB: Random Exceptions or System Lockup on PowerPC Platform ISR Under Heavy Interrupt Load (297347)

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The PowerPC does not have a way to perform strict atomic operations intrinsically guarded by the processor. Instead, the PowerPC provides the lwarx and stwcx instructions to provide a mechanism for guarding against interrupted atomic memory operations. These are intended to allow the programmer to load a value from memory, execute other code, and then conditionally store the value back to the same memory address. The processor will only perform the store if no other stores have occurred to the same address since the first load, otherwise this will fail. If the store fails, the RESERVED bit will be cleared. The code can use a loop to test the RESERVED bit and, if clear, retry the load/store operation again until the conditional store succeeds. If the ISR is reentered or memory touched in the ISR is otherwise written to out of sequence with the ISR, this lwarx/stcwx logic will cause the operation to try until it gets a clean atomic load/store. For example,

loop:
li	r5, g_Value
lwarx	r4, r0, r5
addi	r4, r4, SOME_NUMBER
stwcx.	r4, r0, r5
bne	loop
				

As an example, this logic is performed in the source for the ODO [Hitachi D9000 hardware development platform] PowerPC OAL in the Platform Builder 3.0 under \WINCE300\PLATFORM\ODO\KERNEL\HAL\PPC\intr403.s for the CurMSecUpdate and DiffMSecUpdate operations. See the design manuals for your processor for details on how these instructions work.

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