PRB:Status Error Bit Ignored by Windows 95 Serial Port Driver (138895)

CAUSE

The bits affected are in the LSR (line status register) in the serial chip. When the Serial.vxd driver determines that data is available and there are currently no errors, it enters a loop clearing the FIFO (first in, first out) buffer. This is a very fast loop which only needs to read a minimum of two bytes or a maximum of seventeen bytes to clear the hardware buffer depending on the type of chip in use. Remember, worst case, one last byte may be clocking in while you are reading another byte. It is assumed that the loop time is easily fast enough to complete before subsequent incoming bytes are ready to be read.

To check for remaining byte(s), the loop reads the LSR, which contains the DR (data ready) bit. The remaining bits are ignored. However, reading the LSR, clears the OR, FE, and PE error bits.

If an error occurs in the brief time on the way to this loop, it is ignored and cleared. There are two cases where this might be a problem if the FIFO triggering is set to the maximum, or if an 8250-style chip is being used. One case occurs during a high speed continuous data transfer just bordering on overrun, where the very first error must be flagged immediately. The other case involves a high speed burst or packet of data, again bordering on overrun where the error occurs just at the end of the transfer so that the one and only error might be missed occasionally.

As you would expect, applications handling any sort of continuing data, not in a burst, quickly get subsequent error codes being reported. Any condition, such as overrun still continues to cause ongoing errors, and at the user level, it is noted by an application.