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How DTS Adjusts System Clocks

Many system clocks are based on an oscillator and operate with a combination of hardware and software. The hardware for each clock contains a timer that sends interrupts to the operating system at fixed intervals; each interrupt is a single tick. A software register that contains the current value of the time is incremented by a fixed amount (for example, 10 milliseconds) at each tick. DTS adjusts the rate of the clock by changing only the incremental value that is added to the software register. It does not directly affect the ticks of the hardware clock.

DTS adjusts system clocks at the rate of 100 to 1; that is, it requires 100 time units to adjust 1 time unit of error. For example, it takes 1 minute and 40 seconds to correct a 1-second error. This rate of adjustment exceeds the normal rate of drift so that synchronization is carried out without further significant interference from the clock.

The following figure illustrates how DTS changes the increment to the software register. The top line represents a 10-millisecond increment to the normal clock at every 10-millisecond tick. The middle line illustrates the adjustment to a fast clock; DTS slows the clock by incrementing the register by 9.9 milliseconds instead of 10 milliseconds at each tick. The bottom line illustrates the adjustment to a slow clock; DTS speeds it up by incrementing the register by 10.1 milliseconds instead of the usual 10 milliseconds at each tick.


Adjustment of the Clock

It is occasionally preferable to set the system clock immediately, rather than adjusting it gradually. DTS provides this option for the following situations:

· During system startup when you want to set the initial system time

· If it has been a long time since the last synchronization, and you decide that the skews between system clocks are too large to wait for a gradual adjustment

· When a network has had catastrophic hardware problems, causing a large number of the clocks to become faulty

· When the time interval for a given clock does not intersect with the intervals of other clocks, and the error exceeds a predetermined tolerance