/*
 * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_SYS_MACHCPUVAR_H
#define	_SYS_MACHCPUVAR_H

#pragma ident	"@(#)machcpuvar.h	1.44	05/10/03 SMI"

#include <sys/intr.h>
#include <sys/clock.h>
#include <sys/machparam.h>
#include <sys/machpcb.h>
#include <sys/privregs.h>
#include <sys/machlock.h>

#ifdef	__cplusplus
extern "C" {
#endif

#ifndef	_ASM

#include <sys/obpdefs.h>

/*
 * CPU state ptl1_panic save.
 */
typedef struct ptl1_trapregs {
	uint32_t	ptl1_tl;
	uint32_t	ptl1_tt;
	uint64_t	ptl1_tstate;
	uint64_t	ptl1_tpc;
	uint64_t	ptl1_tnpc;
} ptl1_trapregs_t;

typedef struct ptl1_regs {
	ptl1_trapregs_t	ptl1_trap_regs[PTL1_MAXTL];
	uint64_t	ptl1_g1;
	uint64_t	ptl1_g2;
	uint64_t	ptl1_g3;
	uint64_t	ptl1_g4;
	uint64_t	ptl1_g5;
	uint64_t	ptl1_g6;
	uint64_t	ptl1_g7;
	uint64_t	ptl1_tick;
	uint64_t	ptl1_dmmu_sfar;
	uint64_t	ptl1_dmmu_sfsr;
	uint64_t	ptl1_dmmu_tag_access;
	uint64_t	ptl1_immu_sfsr;
	uint64_t	ptl1_immu_tag_access;
	struct rwindow	ptl1_rwindow[MAXWIN];
	uint32_t	ptl1_softint;
	uint16_t	ptl1_pstate;
	uint8_t		ptl1_pil;
	uint8_t		ptl1_cwp;
	uint8_t		ptl1_wstate;
	uint8_t		ptl1_otherwin;
	uint8_t		ptl1_cleanwin;
	uint8_t		ptl1_cansave;
	uint8_t		ptl1_canrestore;
} ptl1_regs_t;

typedef struct ptl1_state {
	ptl1_regs_t	ptl1_regs;
	uint32_t	ptl1_entry_count;
	uintptr_t	ptl1_stktop;
	ulong_t		ptl1_stk[1];
} ptl1_state_t;

/*
 * Machine specific fields of the cpu struct
 * defined in common/sys/cpuvar.h.
 */
struct	machcpu {
	struct machpcb	*mpcb;
	int		mutex_ready;
	int		in_prom;
	int		tl1_hdlr;
	char		*cpu_info;
	u_longlong_t	tmp1;		/* per-cpu tmps */
	u_longlong_t	tmp2;		/*  used in trap processing */
	struct intr_req intr_pool[INTR_PENDING_MAX];	/* intr pool */
	struct intr_req *intr_head[PIL_LEVELS];		/* intr que heads */
	struct intr_req *intr_tail[PIL_LEVELS];		/* intr que tails */
	int		intr_pool_added;		/* add'l intr pool */
	boolean_t	poke_cpu_outstanding;
	/*
	 * The cpu module allocates a private data structure for the
	 * E$ data, which is needed for the specific cpu type.
	 */
	void		*cpu_private;		/* ptr to cpu private data */

	uint64_t	cpc_saved_pcr;		/* save area for idle thread */

	ptl1_state_t	ptl1_state;

	uint64_t	pil_high_start[HIGH_LEVELS];	/* high-level intrs */
	uint64_t	intrstat[PIL_MAX+1];		/* total intr ticks */
	uint8_t		intrcnt;	/* number of back-to-back interrupts */
};

typedef	struct machcpu	machcpu_t;

/*
 * The OpenBoot Standalone Interface supplies the kernel with
 * implementation dependent parameters through the devinfo/property mechanism
 */
#define	MAXSYSNAME	20

/*
 * Used to indicate busy/idle state of a cpu.
 * msram field will be set with ECACHE_CPU_MIRROR if we are on
 * mirrored sram module.
 */
#define	ECACHE_CPU_IDLE		0x0		/* CPU is idle */
#define	ECACHE_CPU_BUSY		0x1		/* CPU is busy */
#define	ECACHE_CPU_MIRROR 	0x2		/* E$ is mirrored */
#define	ECACHE_CPU_NON_MIRROR	0x3		/* E$ is not mirrored */

struct cpu_node {
	char	name[MAXSYSNAME];
	int	implementation;
	int	version;
	int	portid;
	dnode_t	nodeid;
	uint64_t	clock_freq;
	uint_t	tick_nsec_scale;
	union {
		int	dummy;
	}	u_info;
	int	ecache_size;
	int	ecache_linesize;
	ushort_t	itlb_size;
	ushort_t	dtlb_size;
	int	msram;
};

extern struct cpu_node cpunodes[];

#endif	/* _ASM */

#ifdef	__cplusplus
}
#endif

#endif	/* _SYS_MACHCPUVAR_H */
