The Alpha architecture is a quadword (64-bit) architecture, with limited
backward compatibility for longword (32-bit) operations.
The Alpha architecture's
design philosophy for longword operations is to use the quadword instructions
wherever possible and to include specialized longword instructions for high-frequency
operations.
B.1 Canonical Form
Longword operations deal with longword data stored in canonical form in quadword registers. The canonical form has the longword data in the low 32 bits (0-31) of the register, with bit 31 replicated in the high 32 bits (32-63). Note that the canonical form is the same for both signed and unsigned longword data.
To create a canonical form operand from longword data, use the
ldl,
ldl_l, or
uldl
instruction.
To create a canonical form operand from a constant, use the
ldil
instruction.
The
ldil
instruction is a macro
instruction that expands into a series of instructions, including the
lda
and
ldah
instructions.
B.2 Longword Instructions
The Alpha architecture includes the following longword instructions:
Load Longword (ldl)
Load Longword Locked (ldl_l)
Store Longword (stl)
Store Longword Conditional (stl_c)
Add Longword (addl, addlv)
Subtract Longword (subl, sublv)
Multiply Longword (mull, mullv)
Scaled Longword Add (s4addl, s8addl)
Scaled Longword Subtract (s4subl, s8subl)
In addition, the assembler provides the following longword macro instructions:
Divide Longword (divl, divlu)
Remainder Longword (reml, remlu)
Negate Longword (negl, neglv)
Unaligned Load Longword (uldl)
Load Immediate Longword (ldil)
Absolute Value Longword (absl)
Sign-Extension Longword (sextl)
All longword instructions, with the exception of
stl
and
stl_c, generate results in canonical form.
All longword instructions that have source operands produce correct results, regardless of whether the data items in the source registers are in canonical form.
See
Chapter 3
for a detailed description
of the longword instructions.
B.3 Quadword Instructions for Longword Operations
The following quadword instructions, if presented with two canonical longword operands, produce a canonical longword result:
Logical AND (and)
Logical OR (bis)
Logical Exclusive OR (xor)
Logical OR NOT (ornot)
Logical Equivalence (eqv)
Conditional Move (cmovxx)
Compare (cmpxx)
Conditional Branch (bxx)
Arithmetic Shift Right (sra)
Note that these instructions, unlike the longword instructions, must have operands in canonical form to produce correct results.
See
Chapter 3
for a detailed description
of the quadword instructions.
B.4 Logical Shift Instructions
No instructions, either machine or macro, exist for performing logical shifts on canonical longwords.
To perform a logical shift left, use the following instruction sequence:
sll $rx, xx, $ry # noncanonical result addl $ry, 0, $ry # sign-extend bit-31
To perform a logical shift right, use the following instruction sequence:
zap $rx, 0xf0, $ry # noncanonical result srl $ry, xx, $ry # if xx >= 1, bring in zeros addl $ry, 0, $ry # sign-extend bit-31
Note that the
addl
instruction is not needed if the
shift count in the previous sequence is guaranteed to be nonzero.
B.5 Conversions to Quadword
A signed longword value in canonical form is also a proper signed quadword value and no conversions are needed.
An unsigned longword value in canonical form is not a proper unsigned quadword value. To convert an unsigned longword to a quadword, use the following instruction sequence:
zap $rx, 0xf0, $ry # clear bits 32-63
To convert a quadword value to either a signed or unsigned longword, use the following instruction sequence:
addl $rx, 0, $ry # sign-extend bit-31