File: (none)
                  [000000]     1  is_hal = 1
                  [000000]     1  .SHOW MEB
File: ev6_defs.mar
                  [000000]     1  ;; Alpha assembly macro (-m) output created by DEFNR
                  [000000]     2  
                  [000000]     3  EV6__DTBM_DOUBLE_3_ENTRY = ^x100	
                  [000000]     4  EV6__DTBM_DOUBLE_4_ENTRY = ^x180	
                  [000000]     5  EV6__FEN_ENTRY = ^x200	
                  [000000]     6  EV6__UNALIGN_ENTRY = ^x280	
                  [000000]     7  EV6__DTBM_SINGLE_ENTRY = ^x300	
                  [000000]     8  EV6__DFAULT_ENTRY = ^x380	
                  [000000]     9  EV6__OPCDEC_ENTRY = ^x400	
                  [000000]    10  EV6__IACV_ENTRY = ^x480	
                  [000000]    11  EV6__MCHK_ENTRY = ^x500	
                  [000000]    12  EV6__ITB_MISS_ENTRY = ^x580	
                  [000000]    13  EV6__ARITH_ENTRY = ^x600	
                  [000000]    14  EV6__INTERRUPT_ENTRY = ^x680	
                  [000000]    15  EV6__MT_FPCR_ENTRY = ^x700	
                  [000000]    16  EV6__RESET_ENTRY = ^x780	
                  [000000]    17  EV6__CHIP_ID_EV6_PASS1 = ^x0	
                  [000000]    18  EV6__CHIP_ID_EV6_PASS2 = ^x1	
                  [000000]    19  EV6__CHIP_ID_EV6_PASS2_2 = ^x2	
                  [000000]    20  EV6__CHIP_ID_EV6_PASS2_3 = ^x3	
                  [000000]    21  EV6__CHIP_ID_EV6_PASS3 = ^x4	
                  [000000]    22  EV6__CHIP_ID_EV67_PASS1 = ^x8	
                  [000000]    23  EV6__CHIP_ID_EV67_PASS2_1 = ^x8	
                  [000000]    24  EV6__CHIP_ID_EV67_PASS2_1_1 = ^xa	
                  [000000]    25  EV6__CHIP_ID_EV67_PASS2_2 = ^x9	
                  [000000]    26  EV6__CHIP_ID_EV67_PASS2_2_1 = ^xb	
                  [000000]    27  EV6__CHIP_ID_EV68_PASS1 = ^x10	
                  [000000]    28  EV6__CHIP_ID_EV7_PASS1 = ^x18	
                  [000000]    29  EV6__HALT_ENTRY = ^x2000	
                  [000000]    30  EV6__CALL_PAL_00_ENTRY = ^x2000	
                  [000000]    31  EV6__CALL_PAL_01_ENTRY = ^x2040	
                  [000000]    32  EV6__CALL_PAL_02_ENTRY = ^x2080	
                  [000000]    33  EV6__CALL_PAL_03_ENTRY = ^x20c0	
                  [000000]    34  EV6__CALL_PAL_04_ENTRY = ^x2100	
                  [000000]    35  EV6__CALL_PAL_05_ENTRY = ^x2140	
                  [000000]    36  EV6__CALL_PAL_06_ENTRY = ^x2180	
                  [000000]    37  EV6__CALL_PAL_07_ENTRY = ^x21c0	
                  [000000]    38  EV6__CALL_PAL_08_ENTRY = ^x2200	
                  [000000]    39  EV6__CALL_PAL_09_ENTRY = ^x2240	
                  [000000]    40  EV6__CALL_PAL_0A_ENTRY = ^x2280	
                  [000000]    41  EV6__CALL_PAL_0B_ENTRY = ^x22c0	
                  [000000]    42  EV6__CALL_PAL_0C_ENTRY = ^x2300	
                  [000000]    43  EV6__CALL_PAL_0D_ENTRY = ^x2340	
                  [000000]    44  EV6__CALL_PAL_0E_ENTRY = ^x2380	
                  [000000]    45  EV6__CALL_PAL_0F_ENTRY = ^x23c0	
                  [000000]    46  EV6__CALL_PAL_10_ENTRY = ^x2400	
                  [000000]    47  EV6__CALL_PAL_11_ENTRY = ^x2440	
                  [000000]    48  EV6__CALL_PAL_12_ENTRY = ^x2480	
                  [000000]    49  EV6__CALL_PAL_13_ENTRY = ^x24c0	
                  [000000]    50  EV6__CALL_PAL_14_ENTRY = ^x2500	
                  [000000]    51  EV6__CALL_PAL_15_ENTRY = ^x2540	
                  [000000]    52  EV6__CALL_PAL_16_ENTRY = ^x2580	
                  [000000]    53  EV6__CALL_PAL_17_ENTRY = ^x25c0	
                  [000000]    54  EV6__CALL_PAL_18_ENTRY = ^x2600	
                  [000000]    55  EV6__CALL_PAL_19_ENTRY = ^x2640	
                  [000000]    56  EV6__CALL_PAL_1A_ENTRY = ^x2680	
                  [000000]    57  EV6__CALL_PAL_1B_ENTRY = ^x26c0	
                  [000000]    58  EV6__CALL_PAL_1C_ENTRY = ^x2700	
                  [000000]    59  EV6__CALL_PAL_1D_ENTRY = ^x2740	
                  [000000]    60  EV6__CALL_PAL_1E_ENTRY = ^x2780	
                  [000000]    61  EV6__CALL_PAL_1F_ENTRY = ^x27c0	
                  [000000]    62  EV6__CALL_PAL_20_ENTRY = ^x2800	
                  [000000]    63  EV6__CALL_PAL_21_ENTRY = ^x2840	
                  [000000]    64  EV6__CALL_PAL_22_ENTRY = ^x2880	
                  [000000]    65  EV6__CALL_PAL_23_ENTRY = ^x28c0	
                  [000000]    66  EV6__CALL_PAL_24_ENTRY = ^x2900	
                  [000000]    67  EV6__CALL_PAL_25_ENTRY = ^x2940	
                  [000000]    68  EV6__CALL_PAL_26_ENTRY = ^x2980	
                  [000000]    69  EV6__CALL_PAL_27_ENTRY = ^x29c0	
                  [000000]    70  EV6__CALL_PAL_28_ENTRY = ^x2a00	
                  [000000]    71  EV6__CALL_PAL_29_ENTRY = ^x2a40	
                  [000000]    72  EV6__CALL_PAL_2A_ENTRY = ^x2a80	
                  [000000]    73  EV6__CALL_PAL_2B_ENTRY = ^x2ac0	
                  [000000]    74  EV6__CALL_PAL_2C_ENTRY = ^x2b00	
                  [000000]    75  EV6__CALL_PAL_2D_ENTRY = ^x2b40	
                  [000000]    76  EV6__CALL_PAL_2E_ENTRY = ^x2b80	
                  [000000]    77  EV6__CALL_PAL_2F_ENTRY = ^x2bc0	
                  [000000]    78  EV6__CALL_PAL_30_ENTRY = ^x2c00	
                  [000000]    79  EV6__CALL_PAL_31_ENTRY = ^x2c40	
                  [000000]    80  EV6__CALL_PAL_32_ENTRY = ^x2c80	
                  [000000]    81  EV6__CALL_PAL_33_ENTRY = ^x2cc0	
                  [000000]    82  EV6__CALL_PAL_34_ENTRY = ^x2d00	
                  [000000]    83  EV6__CALL_PAL_35_ENTRY = ^x2d40	
                  [000000]    84  EV6__CALL_PAL_36_ENTRY = ^x2d80	
                  [000000]    85  EV6__CALL_PAL_37_ENTRY = ^x2dc0	
                  [000000]    86  EV6__CALL_PAL_38_ENTRY = ^x2e00	
                  [000000]    87  EV6__CALL_PAL_39_ENTRY = ^x2e40	
                  [000000]    88  EV6__CALL_PAL_3A_ENTRY = ^x2e80	
                  [000000]    89  EV6__CALL_PAL_3B_ENTRY = ^x2ec0	
                  [000000]    90  EV6__CALL_PAL_3C_ENTRY = ^x2f00	
                  [000000]    91  EV6__CALL_PAL_3D_ENTRY = ^x2f40	
                  [000000]    92  EV6__CALL_PAL_3E_ENTRY = ^x2f80	
                  [000000]    93  EV6__CALL_PAL_3F_ENTRY = ^x2fc0	
                  [000000]    94  EV6__CALL_PAL_80_ENTRY = ^x3000	
                  [000000]    95  EV6__CALL_PAL_81_ENTRY = ^x3040	
                  [000000]    96  EV6__CALL_PAL_82_ENTRY = ^x3080	
                  [000000]    97  EV6__CALL_PAL_83_ENTRY = ^x30c0	
                  [000000]    98  EV6__CALL_PAL_84_ENTRY = ^x3100	
                  [000000]    99  EV6__CALL_PAL_85_ENTRY = ^x3140	
                  [000000]   100  EV6__CALL_PAL_86_ENTRY = ^x3180	
                  [000000]   101  EV6__CALL_PAL_87_ENTRY = ^x31c0	
                  [000000]   102  EV6__CALL_PAL_88_ENTRY = ^x3200	
                  [000000]   103  EV6__CALL_PAL_89_ENTRY = ^x3240	
                  [000000]   104  EV6__CALL_PAL_8A_ENTRY = ^x3280	
                  [000000]   105  EV6__CALL_PAL_8B_ENTRY = ^x32c0	
                  [000000]   106  EV6__CALL_PAL_8C_ENTRY = ^x3300	
                  [000000]   107  EV6__CALL_PAL_8D_ENTRY = ^x3340	
                  [000000]   108  EV6__CALL_PAL_8E_ENTRY = ^x3380	
                  [000000]   109  EV6__CALL_PAL_8F_ENTRY = ^x33c0	
                  [000000]   110  EV6__CALL_PAL_90_ENTRY = ^x3400	
                  [000000]   111  EV6__CALL_PAL_91_ENTRY = ^x3440	
                  [000000]   112  EV6__CALL_PAL_92_ENTRY = ^x3480	
                  [000000]   113  EV6__CALL_PAL_93_ENTRY = ^x34c0	
                  [000000]   114  EV6__CALL_PAL_94_ENTRY = ^x3500	
                  [000000]   115  EV6__CALL_PAL_95_ENTRY = ^x3540	
                  [000000]   116  EV6__CALL_PAL_96_ENTRY = ^x3580	
                  [000000]   117  EV6__CALL_PAL_97_ENTRY = ^x35c0	
                  [000000]   118  EV6__CALL_PAL_98_ENTRY = ^x3600	
                  [000000]   119  EV6__CALL_PAL_99_ENTRY = ^x3640	
                  [000000]   120  EV6__CALL_PAL_9A_ENTRY = ^x3680	
                  [000000]   121  EV6__CALL_PAL_9B_ENTRY = ^x36c0	
                  [000000]   122  EV6__CALL_PAL_9C_ENTRY = ^x3700	
                  [000000]   123  EV6__CALL_PAL_9D_ENTRY = ^x3740	
                  [000000]   124  EV6__CALL_PAL_9E_ENTRY = ^x3780	
                  [000000]   125  EV6__CALL_PAL_9F_ENTRY = ^x37c0	
                  [000000]   126  EV6__CALL_PAL_A0_ENTRY = ^x3800	
                  [000000]   127  EV6__CALL_PAL_A1_ENTRY = ^x3840	
                  [000000]   128  EV6__CALL_PAL_A2_ENTRY = ^x3880	
                  [000000]   129  EV6__CALL_PAL_A3_ENTRY = ^x38c0	
                  [000000]   130  EV6__CALL_PAL_A4_ENTRY = ^x3900	
                  [000000]   131  EV6__CALL_PAL_A5_ENTRY = ^x3940	
                  [000000]   132  EV6__CALL_PAL_A6_ENTRY = ^x3980	
                  [000000]   133  EV6__CALL_PAL_A7_ENTRY = ^x39c0	
                  [000000]   134  EV6__CALL_PAL_A8_ENTRY = ^x3a00	
                  [000000]   135  EV6__CALL_PAL_A9_ENTRY = ^x3a40	
                  [000000]   136  EV6__CALL_PAL_AA_ENTRY = ^x3a80	
                  [000000]   137  EV6__CALL_PAL_AB_ENTRY = ^x3ac0	
                  [000000]   138  EV6__CALL_PAL_AC_ENTRY = ^x3b00	
                  [000000]   139  EV6__CALL_PAL_AD_ENTRY = ^x3b40	
                  [000000]   140  EV6__CALL_PAL_AE_ENTRY = ^x3b80	
                  [000000]   141  EV6__CALL_PAL_AF_ENTRY = ^x3bc0	
                  [000000]   142  EV6__CALL_PAL_B0_ENTRY = ^x3c00	
                  [000000]   143  EV6__CALL_PAL_B1_ENTRY = ^x3c40	
                  [000000]   144  EV6__CALL_PAL_B2_ENTRY = ^x3c80	
                  [000000]   145  EV6__CALL_PAL_B3_ENTRY = ^x3cc0	
                  [000000]   146  EV6__CALL_PAL_B4_ENTRY = ^x3d00	
                  [000000]   147  EV6__CALL_PAL_B5_ENTRY = ^x3d40	
                  [000000]   148  EV6__CALL_PAL_B6_ENTRY = ^x3d80	
                  [000000]   149  EV6__CALL_PAL_B7_ENTRY = ^x3dc0	
                  [000000]   150  EV6__CALL_PAL_B8_ENTRY = ^x3e00	
                  [000000]   151  EV6__CALL_PAL_B9_ENTRY = ^x3e40	
                  [000000]   152  EV6__CALL_PAL_BA_ENTRY = ^x3e80	
                  [000000]   153  EV6__CALL_PAL_BB_ENTRY = ^x3ec0	
                  [000000]   154  EV6__CALL_PAL_BC_ENTRY = ^x3f00	
                  [000000]   155  EV6__CALL_PAL_BD_ENTRY = ^x3f40	
                  [000000]   156  EV6__CALL_PAL_BE_ENTRY = ^x3f80	
                  [000000]   157  EV6__CALL_PAL_BF_ENTRY = ^x3fc0	
                  [000000]   158  
                  [000000]   159  EV6__CC = ^xc0	
                  [000000]   160  EV6__CC__COUNTER_BOT__S = ^x0	
                  [000000]   161  EV6__CC__COUNTER_BOT__V = ^x4	
                  [000000]   162  EV6__CC__COUNTER_BOT__M = ^xf	
                  [000000]   163  EV6__CC__COUNTER__S = ^x4	
                  [000000]   164  EV6__CC__COUNTER__V = ^x1c	
                  [000000]   165  EV6__CC__COUNTER__M = ^xfffffff	
                  [000000]   166  EV6__CC__OFFSET__S = ^x20	
                  [000000]   167  EV6__CC__OFFSET__V = ^x20	
                  [000000]   168  EV6__CC__OFFSET__M = ^xffffffff	
                  [000000]   169  
                  [000000]   170  EV6__CC_CTL = ^xc1	
                  [000000]   171  EV6__CC_CTL__RSV1__S = ^x0	
                  [000000]   172  EV6__CC_CTL__RSV1__V = ^x4	
                  [000000]   173  EV6__CC_CTL__RSV1__M = ^xf	
                  [000000]   174  EV6__CC_CTL__COUNTER__S = ^x4	
                  [000000]   175  EV6__CC_CTL__COUNTER__V = ^x1c	
                  [000000]   176  EV6__CC_CTL__COUNTER__M = ^xfffffff	
                  [000000]   177  EV6__CC_CTL__CC_ENA__S = ^x20	
                  [000000]   178  EV6__CC_CTL__CC_ENA__V = ^x1	
                  [000000]   179  EV6__CC_CTL__CC_ENA__M = ^x1	
                  [000000]   180  EV6__CC_CTL__RSV2__S = ^x21	
                  [000000]   181  EV6__CC_CTL__RSV2__V = ^x1f	
                  [000000]   182  EV6__CC_CTL__RSV2__M = ^x7fffffff	
                  [000000]   183  
                  [000000]   184  EV6__VA = ^xc2	
                  [000000]   185  EV6__VA__ADDR__S = ^x0	
                  [000000]   186  EV6__VA__ADDR__V = ^x40	
                  [000000]   187  EV6__VA__ADDR__M = ^xffffffffffffffff	
                  [000000]   188  
                  [000000]   189  EV6__VA_FORM = ^xc3	
                  [000000]   190  EV6__VA_FORM__RSV1__S = ^x0	
                  [000000]   191  EV6__VA_FORM__RSV1__V = ^x3	
                  [000000]   192  EV6__VA_FORM__RSV1__M = ^x7	
                  [000000]   193  EV6__VA_FORM__VA__S = ^x3	
                  [000000]   194  EV6__VA_FORM__VA__V = ^x1e	
                  [000000]   195  EV6__VA_FORM__VA__M = ^x3fffffff	
                  [000000]   196  EV6__VA_FORM__VPTB__S = ^x21	
                  [000000]   197  EV6__VA_FORM__VPTB__V = ^x1f	
                  [000000]   198  EV6__VA_FORM__VPTB__M = ^x7fffffff	
                  [000000]   199  
                  [000000]   200  EV6__VA_FORM_48 = ^xc3	
                  [000000]   201  EV6__VA_FORM_48__RSV1__S = ^x0	
                  [000000]   202  EV6__VA_FORM_48__RSV1__V = ^x3	
                  [000000]   203  EV6__VA_FORM_48__RSV1__M = ^x7	
                  [000000]   204  EV6__VA_FORM_48__VA__S = ^x3	
                  [000000]   205  EV6__VA_FORM_48__VA__V = ^x23	
                  [000000]   206  EV6__VA_FORM_48__VA__M = ^x7ffffffff	
                  [000000]   207  EV6__VA_FORM_48__VA_SEXT0__S = ^x26	
                  [000000]   208  EV6__VA_FORM_48__VA_SEXT0__V = ^x1	
                  [000000]   209  EV6__VA_FORM_48__VA_SEXT0__M = ^x1	
                  [000000]   210  EV6__VA_FORM_48__VA_SEXT1__S = ^x27	
                  [000000]   211  EV6__VA_FORM_48__VA_SEXT1__V = ^x1	
                  [000000]   212  EV6__VA_FORM_48__VA_SEXT1__M = ^x1	
                  [000000]   213  EV6__VA_FORM_48__VA_SEXT2__S = ^x28	
                  [000000]   214  EV6__VA_FORM_48__VA_SEXT2__V = ^x1	
                  [000000]   215  EV6__VA_FORM_48__VA_SEXT2__M = ^x1	
                  [000000]   216  EV6__VA_FORM_48__VA_SEXT3__S = ^x29	
                  [000000]   217  EV6__VA_FORM_48__VA_SEXT3__V = ^x1	
                  [000000]   218  EV6__VA_FORM_48__VA_SEXT3__M = ^x1	
                  [000000]   219  EV6__VA_FORM_48__VA_SEXT4__S = ^x2a	
                  [000000]   220  EV6__VA_FORM_48__VA_SEXT4__V = ^x1	
                  [000000]   221  EV6__VA_FORM_48__VA_SEXT4__M = ^x1	
                  [000000]   222  EV6__VA_FORM_48__VPTB__S = ^x2b	
                  [000000]   223  EV6__VA_FORM_48__VPTB__V = ^x15	
                  [000000]   224  EV6__VA_FORM_48__VPTB__M = ^x1fffff	
                  [000000]   225  
                  [000000]   226  EV6__VA_FORM_32 = ^xc3	
                  [000000]   227  EV6__VA_FORM_32__RSV1__S = ^x0	
                  [000000]   228  EV6__VA_FORM_32__RSV1__V = ^x3	
                  [000000]   229  EV6__VA_FORM_32__RSV1__M = ^x7	
                  [000000]   230  EV6__VA_FORM_32__VA__S = ^x3	
                  [000000]   231  EV6__VA_FORM_32__VA__V = ^x13	
                  [000000]   232  EV6__VA_FORM_32__VA__M = ^x7ffff	
                  [000000]   233  EV6__VA_FORM_32__RSV2__S = ^x16	
                  [000000]   234  EV6__VA_FORM_32__RSV2__V = ^x8	
                  [000000]   235  EV6__VA_FORM_32__RSV2__M = ^xff	
                  [000000]   236  EV6__VA_FORM_32__VPTB__S = ^x1e	
                  [000000]   237  EV6__VA_FORM_32__VPTB__V = ^x22	
                  [000000]   238  EV6__VA_FORM_32__VPTB__M = ^x3ffffffff	
                  [000000]   239  
                  [000000]   240  EV6__VA_FORM_64 = ^xc3	
                  [000000]   241  EV6__VA_FORM_64__RSV1__S = ^x0	
                  [000000]   242  EV6__VA_FORM_64__RSV1__V = ^x3	
                  [000000]   243  EV6__VA_FORM_64__RSV1__M = ^x7	
                  [000000]   244  EV6__VA_FORM_64__VA__S = ^x3	
                  [000000]   245  EV6__VA_FORM_64__VA__V = ^x20	
                  [000000]   246  EV6__VA_FORM_64__VA__M = ^xffffffff	
                  [000000]   247  EV6__VA_FORM_64__VA_SEXT0__S = ^x23	
                  [000000]   248  EV6__VA_FORM_64__VA_SEXT0__V = ^x1	
                  [000000]   249  EV6__VA_FORM_64__VA_SEXT0__M = ^x1	
                  [000000]   250  EV6__VA_FORM_64__VA_SEXT1__S = ^x24	
                  [000000]   251  EV6__VA_FORM_64__VA_SEXT1__V = ^x1	
                  [000000]   252  EV6__VA_FORM_64__VA_SEXT1__M = ^x1	
                  [000000]   253  EV6__VA_FORM_64__VA_SEXT2__S = ^x25	
                  [000000]   254  EV6__VA_FORM_64__VA_SEXT2__V = ^x1	
                  [000000]   255  EV6__VA_FORM_64__VA_SEXT2__M = ^x1	
                  [000000]   256  EV6__VA_FORM_64__VA_SEXT3__S = ^x26	
                  [000000]   257  EV6__VA_FORM_64__VA_SEXT3__V = ^x1	
                  [000000]   258  EV6__VA_FORM_64__VA_SEXT3__M = ^x1	
                  [000000]   259  EV6__VA_FORM_64__VA_SEXT4__S = ^x27	
                  [000000]   260  EV6__VA_FORM_64__VA_SEXT4__V = ^x1	
                  [000000]   261  EV6__VA_FORM_64__VA_SEXT4__M = ^x1	
                  [000000]   262  EV6__VA_FORM_64__VA_SEXT5__S = ^x28	
                  [000000]   263  EV6__VA_FORM_64__VA_SEXT5__V = ^x1	
                  [000000]   264  EV6__VA_FORM_64__VA_SEXT5__M = ^x1	
                  [000000]   265  EV6__VA_FORM_64__VA_SEXT6__S = ^x29	
                  [000000]   266  EV6__VA_FORM_64__VA_SEXT6__V = ^x1	
                  [000000]   267  EV6__VA_FORM_64__VA_SEXT6__M = ^x1	
                  [000000]   268  EV6__VA_FORM_64__VA_SEXT7__S = ^x2a	
                  [000000]   269  EV6__VA_FORM_64__VA_SEXT7__V = ^x1	
                  [000000]   270  EV6__VA_FORM_64__VA_SEXT7__M = ^x1	
                  [000000]   271  EV6__VA_FORM_64__VPTB__S = ^x2b	
                  [000000]   272  EV6__VA_FORM_64__VPTB__V = ^x15	
                  [000000]   273  EV6__VA_FORM_64__VPTB__M = ^x1fffff	
                  [000000]   274  
                  [000000]   275  EV6__VA_CTL = ^xc4	
                  [000000]   276  EV6__VA_CTL__B_ENDIAN__S = ^x0	
                  [000000]   277  EV6__VA_CTL__B_ENDIAN__V = ^x1	
                  [000000]   278  EV6__VA_CTL__B_ENDIAN__M = ^x1	
                  [000000]   279  EV6__VA_CTL__VA_48__S = ^x1	
                  [000000]   280  EV6__VA_CTL__VA_48__V = ^x1	
                  [000000]   281  EV6__VA_CTL__VA_48__M = ^x1	
                  [000000]   282  EV6__VA_CTL__VA_FORM_32__S = ^x2	
                  [000000]   283  EV6__VA_CTL__VA_FORM_32__V = ^x1	
                  [000000]   284  EV6__VA_CTL__VA_FORM_32__M = ^x1	
                  [000000]   285  EV6__VA_CTL__RSV1__S = ^x3	
                  [000000]   286  EV6__VA_CTL__RSV1__V = ^x1b	
                  [000000]   287  EV6__VA_CTL__RSV1__M = ^x7ffffff	
                  [000000]   288  EV6__VA_CTL__VPTB__S = ^x1e	
                  [000000]   289  EV6__VA_CTL__VPTB__V = ^x22	
                  [000000]   290  EV6__VA_CTL__VPTB__M = ^x3ffffffff	
                  [000000]   291  
                  [000000]   292  EV6__ITB_TAG = ^x0	
                  [000000]   293  EV6__ITB_TAG__RSV1__S = ^x0	
                  [000000]   294  EV6__ITB_TAG__RSV1__V = ^xd	
                  [000000]   295  EV6__ITB_TAG__RSV1__M = ^x1fff	
                  [000000]   296  EV6__ITB_TAG__VA__S = ^xd	
                  [000000]   297  EV6__ITB_TAG__VA__V = ^x23	
                  [000000]   298  EV6__ITB_TAG__VA__M = ^x7ffffffff	
                  [000000]   299  EV6__ITB_TAG__RSV2__S = ^x30	
                  [000000]   300  EV6__ITB_TAG__RSV2__V = ^x10	
                  [000000]   301  EV6__ITB_TAG__RSV2__M = ^xffff	
                  [000000]   302  
                  [000000]   303  EV6__ITB_PTE = ^x1	
                  [000000]   304  EV6__ITB_PTE__RSV1__S = ^x0	
                  [000000]   305  EV6__ITB_PTE__RSV1__V = ^x4	
                  [000000]   306  EV6__ITB_PTE__RSV1__M = ^xf	
                  [000000]   307  EV6__ITB_PTE__ASM__S = ^x4	
                  [000000]   308  EV6__ITB_PTE__ASM__V = ^x1	
                  [000000]   309  EV6__ITB_PTE__ASM__M = ^x1	
                  [000000]   310  EV6__ITB_PTE__GH__S = ^x5	
                  [000000]   311  EV6__ITB_PTE__GH__V = ^x2	
                  [000000]   312  EV6__ITB_PTE__GH__M = ^x3	
                  [000000]   313  EV6__ITB_PTE__RSV2__S = ^x7	
                  [000000]   314  EV6__ITB_PTE__RSV2__V = ^x1	
                  [000000]   315  EV6__ITB_PTE__RSV2__M = ^x1	
                  [000000]   316  EV6__ITB_PTE__KRE__S = ^x8	
                  [000000]   317  EV6__ITB_PTE__KRE__V = ^x1	
                  [000000]   318  EV6__ITB_PTE__KRE__M = ^x1	
                  [000000]   319  EV6__ITB_PTE__ERE__S = ^x9	
                  [000000]   320  EV6__ITB_PTE__ERE__V = ^x1	
                  [000000]   321  EV6__ITB_PTE__ERE__M = ^x1	
                  [000000]   322  EV6__ITB_PTE__SRE__S = ^xa	
                  [000000]   323  EV6__ITB_PTE__SRE__V = ^x1	
                  [000000]   324  EV6__ITB_PTE__SRE__M = ^x1	
                  [000000]   325  EV6__ITB_PTE__URE__S = ^xb	
                  [000000]   326  EV6__ITB_PTE__URE__V = ^x1	
                  [000000]   327  EV6__ITB_PTE__URE__M = ^x1	
                  [000000]   328  EV6__ITB_PTE__RSV3__S = ^xc	
                  [000000]   329  EV6__ITB_PTE__RSV3__V = ^x1	
                  [000000]   330  EV6__ITB_PTE__RSV3__M = ^x1	
                  [000000]   331  EV6__ITB_PTE__PFN__S = ^xd	
                  [000000]   332  EV6__ITB_PTE__PFN__V = ^x1f	
                  [000000]   333  EV6__ITB_PTE__PFN__M = ^x7fffffff	
                  [000000]   334  EV6__ITB_PTE__RSV4__S = ^x2c	
                  [000000]   335  EV6__ITB_PTE__RSV4__V = ^x14	
                  [000000]   336  EV6__ITB_PTE__RSV4__M = ^xfffff	
                  [000000]   337  
                  [000000]   338  EV6__ITB_IAP = ^x2	
                  [000000]   339  EV6__ITB_IAP__RSV__S = ^x0	
                  [000000]   340  EV6__ITB_IAP__RSV__V = ^x40	
                  [000000]   341  EV6__ITB_IAP__RSV__M = ^xffffffffffffffff	
                  [000000]   342  
                  [000000]   343  EV6__ITB_IA = ^x3	
                  [000000]   344  EV6__ITB_IA__RSV__S = ^x0	
                  [000000]   345  EV6__ITB_IA__RSV__V = ^x40	
                  [000000]   346  EV6__ITB_IA__RSV__M = ^xffffffffffffffff	
                  [000000]   347  
                  [000000]   348  EV6__ITB_IS = ^x4	
                  [000000]   349  EV6__ITB_IS__RSV1__S = ^x0	
                  [000000]   350  EV6__ITB_IS__RSV1__V = ^xd	
                  [000000]   351  EV6__ITB_IS__RSV1__M = ^x1fff	
                  [000000]   352  EV6__ITB_IS__VA__S = ^xd	
                  [000000]   353  EV6__ITB_IS__VA__V = ^x23	
                  [000000]   354  EV6__ITB_IS__VA__M = ^x7ffffffff	
                  [000000]   355  EV6__ITB_IS__RSV2__S = ^x30	
                  [000000]   356  EV6__ITB_IS__RSV2__V = ^x10	
                  [000000]   357  EV6__ITB_IS__RSV2__M = ^xffff	
                  [000000]   358  
                  [000000]   359  EV6__EXC_ADDR = ^x6	
                  [000000]   360  EV6__EXC_ADDR__PAL__S = ^x0	
                  [000000]   361  EV6__EXC_ADDR__PAL__V = ^x1	
                  [000000]   362  EV6__EXC_ADDR__PAL__M = ^x1	
                  [000000]   363  EV6__EXC_ADDR__RSV__S = ^x1	
                  [000000]   364  EV6__EXC_ADDR__RSV__V = ^x1	
                  [000000]   365  EV6__EXC_ADDR__RSV__M = ^x1	
                  [000000]   366  EV6__EXC_ADDR__PC__S = ^x2	
                  [000000]   367  EV6__EXC_ADDR__PC__V = ^x2e	
                  [000000]   368  EV6__EXC_ADDR__PC__M = ^x3fffffffffff	
                  [000000]   369  EV6__EXC_ADDR__PC_SEXT0__S = ^x30	
                  [000000]   370  EV6__EXC_ADDR__PC_SEXT0__V = ^x1	
                  [000000]   371  EV6__EXC_ADDR__PC_SEXT0__M = ^x1	
                  [000000]   372  EV6__EXC_ADDR__PC_SEXT1__S = ^x31	
                  [000000]   373  EV6__EXC_ADDR__PC_SEXT1__V = ^x1	
                  [000000]   374  EV6__EXC_ADDR__PC_SEXT1__M = ^x1	
                  [000000]   375  EV6__EXC_ADDR__PC_SEXT2__S = ^x32	
                  [000000]   376  EV6__EXC_ADDR__PC_SEXT2__V = ^x1	
                  [000000]   377  EV6__EXC_ADDR__PC_SEXT2__M = ^x1	
                  [000000]   378  EV6__EXC_ADDR__PC_SEXT3__S = ^x33	
                  [000000]   379  EV6__EXC_ADDR__PC_SEXT3__V = ^x1	
                  [000000]   380  EV6__EXC_ADDR__PC_SEXT3__M = ^x1	
                  [000000]   381  EV6__EXC_ADDR__PC_SEXT4__S = ^x34	
                  [000000]   382  EV6__EXC_ADDR__PC_SEXT4__V = ^x1	
                  [000000]   383  EV6__EXC_ADDR__PC_SEXT4__M = ^x1	
                  [000000]   384  EV6__EXC_ADDR__PC_SEXT5__S = ^x35	
                  [000000]   385  EV6__EXC_ADDR__PC_SEXT5__V = ^x1	
                  [000000]   386  EV6__EXC_ADDR__PC_SEXT5__M = ^x1	
                  [000000]   387  EV6__EXC_ADDR__PC_SEXT6__S = ^x36	
                  [000000]   388  EV6__EXC_ADDR__PC_SEXT6__V = ^x1	
                  [000000]   389  EV6__EXC_ADDR__PC_SEXT6__M = ^x1	
                  [000000]   390  EV6__EXC_ADDR__PC_SEXT7__S = ^x37	
                  [000000]   391  EV6__EXC_ADDR__PC_SEXT7__V = ^x1	
                  [000000]   392  EV6__EXC_ADDR__PC_SEXT7__M = ^x1	
                  [000000]   393  EV6__EXC_ADDR__PC_SEXT8__S = ^x38	
                  [000000]   394  EV6__EXC_ADDR__PC_SEXT8__V = ^x1	
                  [000000]   395  EV6__EXC_ADDR__PC_SEXT8__M = ^x1	
                  [000000]   396  EV6__EXC_ADDR__PC_SEXT9__S = ^x39	
                  [000000]   397  EV6__EXC_ADDR__PC_SEXT9__V = ^x1	
                  [000000]   398  EV6__EXC_ADDR__PC_SEXT9__M = ^x1	
                  [000000]   399  EV6__EXC_ADDR__PC_SEXT10__S = ^x3a	
                  [000000]   400  EV6__EXC_ADDR__PC_SEXT10__V = ^x1	
                  [000000]   401  EV6__EXC_ADDR__PC_SEXT10__M = ^x1	
                  [000000]   402  EV6__EXC_ADDR__PC_SEXT11__S = ^x3b	
                  [000000]   403  EV6__EXC_ADDR__PC_SEXT11__V = ^x1	
                  [000000]   404  EV6__EXC_ADDR__PC_SEXT11__M = ^x1	
                  [000000]   405  EV6__EXC_ADDR__PC_SEXT12__S = ^x3c	
                  [000000]   406  EV6__EXC_ADDR__PC_SEXT12__V = ^x1	
                  [000000]   407  EV6__EXC_ADDR__PC_SEXT12__M = ^x1	
                  [000000]   408  EV6__EXC_ADDR__PC_SEXT13__S = ^x3d	
                  [000000]   409  EV6__EXC_ADDR__PC_SEXT13__V = ^x1	
                  [000000]   410  EV6__EXC_ADDR__PC_SEXT13__M = ^x1	
                  [000000]   411  EV6__EXC_ADDR__PC_SEXT14__S = ^x3e	
                  [000000]   412  EV6__EXC_ADDR__PC_SEXT14__V = ^x1	
                  [000000]   413  EV6__EXC_ADDR__PC_SEXT14__M = ^x1	
                  [000000]   414  EV6__EXC_ADDR__PC_SEXT15__S = ^x3f	
                  [000000]   415  EV6__EXC_ADDR__PC_SEXT15__V = ^x1	
                  [000000]   416  EV6__EXC_ADDR__PC_SEXT15__M = ^x1	
                  [000000]   417  
                  [000000]   418  EV6__IVA_FORM = ^x7	
                  [000000]   419  EV6__IVA_FORM__RSV1__S = ^x0	
                  [000000]   420  EV6__IVA_FORM__RSV1__V = ^x3	
                  [000000]   421  EV6__IVA_FORM__RSV1__M = ^x7	
                  [000000]   422  EV6__IVA_FORM__VA__S = ^x3	
                  [000000]   423  EV6__IVA_FORM__VA__V = ^x1e	
                  [000000]   424  EV6__IVA_FORM__VA__M = ^x3fffffff	
                  [000000]   425  EV6__IVA_FORM__VPTB__S = ^x21	
                  [000000]   426  EV6__IVA_FORM__VPTB__V = ^x1f	
                  [000000]   427  EV6__IVA_FORM__VPTB__M = ^x7fffffff	
                  [000000]   428  
                  [000000]   429  EV6__IVA_FORM_48 = ^x7	
                  [000000]   430  EV6__IVA_FORM_48__RSV1__S = ^x0	
                  [000000]   431  EV6__IVA_FORM_48__RSV1__V = ^x3	
                  [000000]   432  EV6__IVA_FORM_48__RSV1__M = ^x7	
                  [000000]   433  EV6__IVA_FORM_48__VA__S = ^x3	
                  [000000]   434  EV6__IVA_FORM_48__VA__V = ^x23	
                  [000000]   435  EV6__IVA_FORM_48__VA__M = ^x7ffffffff	
                  [000000]   436  EV6__IVA_FORM_48__VA_SEXT0__S = ^x26	
                  [000000]   437  EV6__IVA_FORM_48__VA_SEXT0__V = ^x1	
                  [000000]   438  EV6__IVA_FORM_48__VA_SEXT0__M = ^x1	
                  [000000]   439  EV6__IVA_FORM_48__VA_SEXT1__S = ^x27	
                  [000000]   440  EV6__IVA_FORM_48__VA_SEXT1__V = ^x1	
                  [000000]   441  EV6__IVA_FORM_48__VA_SEXT1__M = ^x1	
                  [000000]   442  EV6__IVA_FORM_48__VA_SEXT2__S = ^x28	
                  [000000]   443  EV6__IVA_FORM_48__VA_SEXT2__V = ^x1	
                  [000000]   444  EV6__IVA_FORM_48__VA_SEXT2__M = ^x1	
                  [000000]   445  EV6__IVA_FORM_48__VA_SEXT3__S = ^x29	
                  [000000]   446  EV6__IVA_FORM_48__VA_SEXT3__V = ^x1	
                  [000000]   447  EV6__IVA_FORM_48__VA_SEXT3__M = ^x1	
                  [000000]   448  EV6__IVA_FORM_48__VA_SEXT4__S = ^x2a	
                  [000000]   449  EV6__IVA_FORM_48__VA_SEXT4__V = ^x1	
                  [000000]   450  EV6__IVA_FORM_48__VA_SEXT4__M = ^x1	
                  [000000]   451  EV6__IVA_FORM_48__VPTB__S = ^x2b	
                  [000000]   452  EV6__IVA_FORM_48__VPTB__V = ^x15	
                  [000000]   453  EV6__IVA_FORM_48__VPTB__M = ^x1fffff	
                  [000000]   454  
                  [000000]   455  EV6__IVA_FORM_32 = ^x7	
                  [000000]   456  EV6__IVA_FORM_32__RSV1__S = ^x0	
                  [000000]   457  EV6__IVA_FORM_32__RSV1__V = ^x3	
                  [000000]   458  EV6__IVA_FORM_32__RSV1__M = ^x7	
                  [000000]   459  EV6__IVA_FORM_32__VA__S = ^x3	
                  [000000]   460  EV6__IVA_FORM_32__VA__V = ^x13	
                  [000000]   461  EV6__IVA_FORM_32__VA__M = ^x7ffff	
                  [000000]   462  EV6__IVA_FORM_32__RSV2__S = ^x16	
                  [000000]   463  EV6__IVA_FORM_32__RSV2__V = ^x8	
                  [000000]   464  EV6__IVA_FORM_32__RSV2__M = ^xff	
                  [000000]   465  EV6__IVA_FORM_32__VPTB__S = ^x1e	
                  [000000]   466  EV6__IVA_FORM_32__VPTB__V = ^x22	
                  [000000]   467  EV6__IVA_FORM_32__VPTB__M = ^x3ffffffff	
                  [000000]   468  
                  [000000]   469  EV6__IVA_FORM_64 = ^x7	
                  [000000]   470  EV6__IVA_FORM_64__RSV1__S = ^x0	
                  [000000]   471  EV6__IVA_FORM_64__RSV1__V = ^x3	
                  [000000]   472  EV6__IVA_FORM_64__RSV1__M = ^x7	
                  [000000]   473  EV6__IVA_FORM_64__VA__S = ^x3	
                  [000000]   474  EV6__IVA_FORM_64__VA__V = ^x20	
                  [000000]   475  EV6__IVA_FORM_64__VA__M = ^xffffffff	
                  [000000]   476  EV6__IVA_FORM_64__VA_SEXT0__S = ^x23	
                  [000000]   477  EV6__IVA_FORM_64__VA_SEXT0__V = ^x1	
                  [000000]   478  EV6__IVA_FORM_64__VA_SEXT0__M = ^x1	
                  [000000]   479  EV6__IVA_FORM_64__VA_SEXT1__S = ^x24	
                  [000000]   480  EV6__IVA_FORM_64__VA_SEXT1__V = ^x1	
                  [000000]   481  EV6__IVA_FORM_64__VA_SEXT1__M = ^x1	
                  [000000]   482  EV6__IVA_FORM_64__VA_SEXT2__S = ^x25	
                  [000000]   483  EV6__IVA_FORM_64__VA_SEXT2__V = ^x1	
                  [000000]   484  EV6__IVA_FORM_64__VA_SEXT2__M = ^x1	
                  [000000]   485  EV6__IVA_FORM_64__VA_SEXT3__S = ^x26	
                  [000000]   486  EV6__IVA_FORM_64__VA_SEXT3__V = ^x1	
                  [000000]   487  EV6__IVA_FORM_64__VA_SEXT3__M = ^x1	
                  [000000]   488  EV6__IVA_FORM_64__VA_SEXT4__S = ^x27	
                  [000000]   489  EV6__IVA_FORM_64__VA_SEXT4__V = ^x1	
                  [000000]   490  EV6__IVA_FORM_64__VA_SEXT4__M = ^x1	
                  [000000]   491  EV6__IVA_FORM_64__VA_SEXT5__S = ^x28	
                  [000000]   492  EV6__IVA_FORM_64__VA_SEXT5__V = ^x1	
                  [000000]   493  EV6__IVA_FORM_64__VA_SEXT5__M = ^x1	
                  [000000]   494  EV6__IVA_FORM_64__VA_SEXT6__S = ^x29	
                  [000000]   495  EV6__IVA_FORM_64__VA_SEXT6__V = ^x1	
                  [000000]   496  EV6__IVA_FORM_64__VA_SEXT6__M = ^x1	
                  [000000]   497  EV6__IVA_FORM_64__VA_SEXT7__S = ^x2a	
                  [000000]   498  EV6__IVA_FORM_64__VA_SEXT7__V = ^x1	
                  [000000]   499  EV6__IVA_FORM_64__VA_SEXT7__M = ^x1	
                  [000000]   500  EV6__IVA_FORM_64__VPTB__S = ^x2b	
                  [000000]   501  EV6__IVA_FORM_64__VPTB__V = ^x15	
                  [000000]   502  EV6__IVA_FORM_64__VPTB__M = ^x1fffff	
                  [000000]   503  
                  [000000]   504  EV6__PS = ^x9	
                  [000000]   505  EV6__PS__RSV0__S = ^x0	
                  [000000]   506  EV6__PS__RSV0__V = ^x3	
                  [000000]   507  EV6__PS__RSV0__M = ^x7	
                  [000000]   508  EV6__PS__CM__S = ^x3	
                  [000000]   509  EV6__PS__CM__V = ^x2	
                  [000000]   510  EV6__PS__CM__M = ^x3	
                  [000000]   511  EV6__PS__RSV1__S = ^x5	
                  [000000]   512  EV6__PS__RSV1__V = ^x8	
                  [000000]   513  EV6__PS__RSV1__M = ^xff	
                  [000000]   514  EV6__PS__ASTEN__S = ^xd	
                  [000000]   515  EV6__PS__ASTEN__V = ^x1	
                  [000000]   516  EV6__PS__ASTEN__M = ^x1	
                  [000000]   517  EV6__PS__SIEN__S = ^xe	
                  [000000]   518  EV6__PS__SIEN__V = ^xf	
                  [000000]   519  EV6__PS__SIEN__M = ^x7fff	
                  [000000]   520  EV6__PS__PCEN__S = ^x1d	
                  [000000]   521  EV6__PS__PCEN__V = ^x2	
                  [000000]   522  EV6__PS__PCEN__M = ^x3	
                  [000000]   523  EV6__PS__CREN__S = ^x1f	
                  [000000]   524  EV6__PS__CREN__V = ^x1	
                  [000000]   525  EV6__PS__CREN__M = ^x1	
                  [000000]   526  EV6__PS__SLEN__S = ^x20	
                  [000000]   527  EV6__PS__SLEN__V = ^x1	
                  [000000]   528  EV6__PS__SLEN__M = ^x1	
                  [000000]   529  EV6__PS__EIEN__S = ^x21	
                  [000000]   530  EV6__PS__EIEN__V = ^x6	
                  [000000]   531  EV6__PS__EIEN__M = ^x3f	
                  [000000]   532  EV6__PS__RSV2__S = ^x27	
                  [000000]   533  EV6__PS__RSV2__V = ^x19	
                  [000000]   534  EV6__PS__RSV2__M = ^x1ffffff	
                  [000000]   535  
                  [000000]   536  EV6__IER = ^xa	
                  [000000]   537  EV6__IER__RSV0__S = ^x0	
                  [000000]   538  EV6__IER__RSV0__V = ^x3	
                  [000000]   539  EV6__IER__RSV0__M = ^x7	
                  [000000]   540  EV6__IER__CM__S = ^x3	
                  [000000]   541  EV6__IER__CM__V = ^x2	
                  [000000]   542  EV6__IER__CM__M = ^x3	
                  [000000]   543  EV6__IER__RSV1__S = ^x5	
                  [000000]   544  EV6__IER__RSV1__V = ^x8	
                  [000000]   545  EV6__IER__RSV1__M = ^xff	
                  [000000]   546  EV6__IER__ASTEN__S = ^xd	
                  [000000]   547  EV6__IER__ASTEN__V = ^x1	
                  [000000]   548  EV6__IER__ASTEN__M = ^x1	
                  [000000]   549  EV6__IER__SIEN__S = ^xe	
                  [000000]   550  EV6__IER__SIEN__V = ^xf	
                  [000000]   551  EV6__IER__SIEN__M = ^x7fff	
                  [000000]   552  EV6__IER__PCEN__S = ^x1d	
                  [000000]   553  EV6__IER__PCEN__V = ^x2	
                  [000000]   554  EV6__IER__PCEN__M = ^x3	
                  [000000]   555  EV6__IER__CREN__S = ^x1f	
                  [000000]   556  EV6__IER__CREN__V = ^x1	
                  [000000]   557  EV6__IER__CREN__M = ^x1	
                  [000000]   558  EV6__IER__SLEN__S = ^x20	
                  [000000]   559  EV6__IER__SLEN__V = ^x1	
                  [000000]   560  EV6__IER__SLEN__M = ^x1	
                  [000000]   561  EV6__IER__EIEN__S = ^x21	
                  [000000]   562  EV6__IER__EIEN__V = ^x6	
                  [000000]   563  EV6__IER__EIEN__M = ^x3f	
                  [000000]   564  EV6__IER__RSV2__S = ^x27	
                  [000000]   565  EV6__IER__RSV2__V = ^x19	
                  [000000]   566  EV6__IER__RSV2__M = ^x1ffffff	
                  [000000]   567  
                  [000000]   568  EV6__IER_CM = ^xb	
                  [000000]   569  EV6__IER_CM__RSV0__S = ^x0	
                  [000000]   570  EV6__IER_CM__RSV0__V = ^x3	
                  [000000]   571  EV6__IER_CM__RSV0__M = ^x7	
                  [000000]   572  EV6__IER_CM__CM__S = ^x3	
                  [000000]   573  EV6__IER_CM__CM__V = ^x2	
                  [000000]   574  EV6__IER_CM__CM__M = ^x3	
                  [000000]   575  EV6__IER_CM__RSV1__S = ^x5	
                  [000000]   576  EV6__IER_CM__RSV1__V = ^x8	
                  [000000]   577  EV6__IER_CM__RSV1__M = ^xff	
                  [000000]   578  EV6__IER_CM__ASTEN__S = ^xd	
                  [000000]   579  EV6__IER_CM__ASTEN__V = ^x1	
                  [000000]   580  EV6__IER_CM__ASTEN__M = ^x1	
                  [000000]   581  EV6__IER_CM__SIEN__S = ^xe	
                  [000000]   582  EV6__IER_CM__SIEN__V = ^xf	
                  [000000]   583  EV6__IER_CM__SIEN__M = ^x7fff	
                  [000000]   584  EV6__IER_CM__PCEN__S = ^x1d	
                  [000000]   585  EV6__IER_CM__PCEN__V = ^x2	
                  [000000]   586  EV6__IER_CM__PCEN__M = ^x3	
                  [000000]   587  EV6__IER_CM__CREN__S = ^x1f	
                  [000000]   588  EV6__IER_CM__CREN__V = ^x1	
                  [000000]   589  EV6__IER_CM__CREN__M = ^x1	
                  [000000]   590  EV6__IER_CM__SLEN__S = ^x20	
                  [000000]   591  EV6__IER_CM__SLEN__V = ^x1	
                  [000000]   592  EV6__IER_CM__SLEN__M = ^x1	
                  [000000]   593  EV6__IER_CM__EIEN__S = ^x21	
                  [000000]   594  EV6__IER_CM__EIEN__V = ^x6	
                  [000000]   595  EV6__IER_CM__EIEN__M = ^x3f	
                  [000000]   596  EV6__IER_CM__RSV2__S = ^x27	
                  [000000]   597  EV6__IER_CM__RSV2__V = ^x19	
                  [000000]   598  EV6__IER_CM__RSV2__M = ^x1ffffff	
                  [000000]   599  
                  [000000]   600  EV6__SIRR = ^xc	
                  [000000]   601  EV6__SIRR__RSV1__S = ^x0	
                  [000000]   602  EV6__SIRR__RSV1__V = ^xe	
                  [000000]   603  EV6__SIRR__RSV1__M = ^x3fff	
                  [000000]   604  EV6__SIRR__SIR__S = ^xe	
                  [000000]   605  EV6__SIRR__SIR__V = ^xf	
                  [000000]   606  EV6__SIRR__SIR__M = ^x7fff	
                  [000000]   607  EV6__SIRR__RSV2__S = ^x1d	
                  [000000]   608  EV6__SIRR__RSV2__V = ^x23	
                  [000000]   609  EV6__SIRR__RSV2__M = ^x7ffffffff	
                  [000000]   610  
                  [000000]   611  EV6__ISUM = ^xd	
                  [000000]   612  EV6__ISUM__RSV0__S = ^x0	
                  [000000]   613  EV6__ISUM__RSV0__V = ^x3	
                  [000000]   614  EV6__ISUM__RSV0__M = ^x7	
                  [000000]   615  EV6__ISUM__ASTK__S = ^x3	
                  [000000]   616  EV6__ISUM__ASTK__V = ^x1	
                  [000000]   617  EV6__ISUM__ASTK__M = ^x1	
                  [000000]   618  EV6__ISUM__ASTE__S = ^x4	
                  [000000]   619  EV6__ISUM__ASTE__V = ^x1	
                  [000000]   620  EV6__ISUM__ASTE__M = ^x1	
                  [000000]   621  EV6__ISUM__RSV1__S = ^x5	
                  [000000]   622  EV6__ISUM__RSV1__V = ^x4	
                  [000000]   623  EV6__ISUM__RSV1__M = ^xf	
                  [000000]   624  EV6__ISUM__ASTS__S = ^x9	
                  [000000]   625  EV6__ISUM__ASTS__V = ^x1	
                  [000000]   626  EV6__ISUM__ASTS__M = ^x1	
                  [000000]   627  EV6__ISUM__ASTU__S = ^xa	
                  [000000]   628  EV6__ISUM__ASTU__V = ^x1	
                  [000000]   629  EV6__ISUM__ASTU__M = ^x1	
                  [000000]   630  EV6__ISUM__RSV2__S = ^xb	
                  [000000]   631  EV6__ISUM__RSV2__V = ^x3	
                  [000000]   632  EV6__ISUM__RSV2__M = ^x7	
                  [000000]   633  EV6__ISUM__SI__S = ^xe	
                  [000000]   634  EV6__ISUM__SI__V = ^xf	
                  [000000]   635  EV6__ISUM__SI__M = ^x7fff	
                  [000000]   636  EV6__ISUM__PC__S = ^x1d	
                  [000000]   637  EV6__ISUM__PC__V = ^x2	
                  [000000]   638  EV6__ISUM__PC__M = ^x3	
                  [000000]   639  EV6__ISUM__CR__S = ^x1f	
                  [000000]   640  EV6__ISUM__CR__V = ^x1	
                  [000000]   641  EV6__ISUM__CR__M = ^x1	
                  [000000]   642  EV6__ISUM__SL__S = ^x20	
                  [000000]   643  EV6__ISUM__SL__V = ^x1	
                  [000000]   644  EV6__ISUM__SL__M = ^x1	
                  [000000]   645  EV6__ISUM__EI__S = ^x21	
                  [000000]   646  EV6__ISUM__EI__V = ^x6	
                  [000000]   647  EV6__ISUM__EI__M = ^x3f	
                  [000000]   648  EV6__ISUM__RSV3__S = ^x27	
                  [000000]   649  EV6__ISUM__RSV3__V = ^x19	
                  [000000]   650  EV6__ISUM__RSV3__M = ^x1ffffff	
                  [000000]   651  
                  [000000]   652  EV6__HW_INT_CLR = ^xe	
                  [000000]   653  EV6__HW_INT_CLR__RSV1__S = ^x0	
                  [000000]   654  EV6__HW_INT_CLR__RSV1__V = ^x1a	
                  [000000]   655  EV6__HW_INT_CLR__RSV1__M = ^x3ffffff	
                  [000000]   656  EV6__HW_INT_CLR__FBTP__S = ^x1a	
                  [000000]   657  EV6__HW_INT_CLR__FBTP__V = ^x1	
                  [000000]   658  EV6__HW_INT_CLR__FBTP__M = ^x1	
                  [000000]   659  EV6__HW_INT_CLR__FBDP__S = ^x1b	
                  [000000]   660  EV6__HW_INT_CLR__FBDP__V = ^x1	
                  [000000]   661  EV6__HW_INT_CLR__FBDP__M = ^x1	
                  [000000]   662  EV6__HW_INT_CLR__MCHK_D__S = ^x1c	
                  [000000]   663  EV6__HW_INT_CLR__MCHK_D__V = ^x1	
                  [000000]   664  EV6__HW_INT_CLR__MCHK_D__M = ^x1	
                  [000000]   665  EV6__HW_INT_CLR__PC__S = ^x1d	
                  [000000]   666  EV6__HW_INT_CLR__PC__V = ^x2	
                  [000000]   667  EV6__HW_INT_CLR__PC__M = ^x3	
                  [000000]   668  EV6__HW_INT_CLR__CR__S = ^x1f	
                  [000000]   669  EV6__HW_INT_CLR__CR__V = ^x1	
                  [000000]   670  EV6__HW_INT_CLR__CR__M = ^x1	
                  [000000]   671  EV6__HW_INT_CLR__SL__S = ^x20	
                  [000000]   672  EV6__HW_INT_CLR__SL__V = ^x1	
                  [000000]   673  EV6__HW_INT_CLR__SL__M = ^x1	
                  [000000]   674  EV6__HW_INT_CLR__RSV2__S = ^x21	
                  [000000]   675  EV6__HW_INT_CLR__RSV2__V = ^x1f	
                  [000000]   676  EV6__HW_INT_CLR__RSV2__M = ^x7fffffff	
                  [000000]   677  
                  [000000]   678  EV6__EXC_SUM = ^xf	
                  [000000]   679  EV6__EXC_SUM__SWC__S = ^x0	
                  [000000]   680  EV6__EXC_SUM__SWC__V = ^x1	
                  [000000]   681  EV6__EXC_SUM__SWC__M = ^x1	
                  [000000]   682  EV6__EXC_SUM__INV__S = ^x1	
                  [000000]   683  EV6__EXC_SUM__INV__V = ^x1	
                  [000000]   684  EV6__EXC_SUM__INV__M = ^x1	
                  [000000]   685  EV6__EXC_SUM__DZE__S = ^x2	
                  [000000]   686  EV6__EXC_SUM__DZE__V = ^x1	
                  [000000]   687  EV6__EXC_SUM__DZE__M = ^x1	
                  [000000]   688  EV6__EXC_SUM__FOV__S = ^x3	
                  [000000]   689  EV6__EXC_SUM__FOV__V = ^x1	
                  [000000]   690  EV6__EXC_SUM__FOV__M = ^x1	
                  [000000]   691  EV6__EXC_SUM__UNF__S = ^x4	
                  [000000]   692  EV6__EXC_SUM__UNF__V = ^x1	
                  [000000]   693  EV6__EXC_SUM__UNF__M = ^x1	
                  [000000]   694  EV6__EXC_SUM__INE__S = ^x5	
                  [000000]   695  EV6__EXC_SUM__INE__V = ^x1	
                  [000000]   696  EV6__EXC_SUM__INE__M = ^x1	
                  [000000]   697  EV6__EXC_SUM__IOV__S = ^x6	
                  [000000]   698  EV6__EXC_SUM__IOV__V = ^x1	
                  [000000]   699  EV6__EXC_SUM__IOV__M = ^x1	
                  [000000]   700  EV6__EXC_SUM__INT__S = ^x7	
                  [000000]   701  EV6__EXC_SUM__INT__V = ^x1	
                  [000000]   702  EV6__EXC_SUM__INT__M = ^x1	
                  [000000]   703  EV6__EXC_SUM__REG__S = ^x8	
                  [000000]   704  EV6__EXC_SUM__REG__V = ^x5	
                  [000000]   705  EV6__EXC_SUM__REG__M = ^x1f	
                  [000000]   706  EV6__EXC_SUM__BAD_IVA__S = ^xd	
                  [000000]   707  EV6__EXC_SUM__BAD_IVA__V = ^x1	
                  [000000]   708  EV6__EXC_SUM__BAD_IVA__M = ^x1	
                  [000000]   709  EV6__EXC_SUM__RSV1__S = ^xe	
                  [000000]   710  EV6__EXC_SUM__RSV1__V = ^x1b	
                  [000000]   711  EV6__EXC_SUM__RSV1__M = ^x7ffffff	
                  [000000]   712  EV6__EXC_SUM__PC_OVFL__S = ^x29	
                  [000000]   713  EV6__EXC_SUM__PC_OVFL__V = ^x1	
                  [000000]   714  EV6__EXC_SUM__PC_OVFL__M = ^x1	
                  [000000]   715  EV6__EXC_SUM__SET_INV__S = ^x2a	
                  [000000]   716  EV6__EXC_SUM__SET_INV__V = ^x1	
                  [000000]   717  EV6__EXC_SUM__SET_INV__M = ^x1	
                  [000000]   718  EV6__EXC_SUM__SET_DZE__S = ^x2b	
                  [000000]   719  EV6__EXC_SUM__SET_DZE__V = ^x1	
                  [000000]   720  EV6__EXC_SUM__SET_DZE__M = ^x1	
                  [000000]   721  EV6__EXC_SUM__SET_FOV__S = ^x2c	
                  [000000]   722  EV6__EXC_SUM__SET_FOV__V = ^x1	
                  [000000]   723  EV6__EXC_SUM__SET_FOV__M = ^x1	
                  [000000]   724  EV6__EXC_SUM__SET_UNF__S = ^x2d	
                  [000000]   725  EV6__EXC_SUM__SET_UNF__V = ^x1	
                  [000000]   726  EV6__EXC_SUM__SET_UNF__M = ^x1	
                  [000000]   727  EV6__EXC_SUM__SET_INE__S = ^x2e	
                  [000000]   728  EV6__EXC_SUM__SET_INE__V = ^x1	
                  [000000]   729  EV6__EXC_SUM__SET_INE__M = ^x1	
                  [000000]   730  EV6__EXC_SUM__SET_IOV__S = ^x2f	
                  [000000]   731  EV6__EXC_SUM__SET_IOV__V = ^x1	
                  [000000]   732  EV6__EXC_SUM__SET_IOV__M = ^x1	
                  [000000]   733  EV6__EXC_SUM__SEXT0__S = ^x30	
                  [000000]   734  EV6__EXC_SUM__SEXT0__V = ^x1	
                  [000000]   735  EV6__EXC_SUM__SEXT0__M = ^x1	
                  [000000]   736  EV6__EXC_SUM__SEXT1__S = ^x31	
                  [000000]   737  EV6__EXC_SUM__SEXT1__V = ^x1	
                  [000000]   738  EV6__EXC_SUM__SEXT1__M = ^x1	
                  [000000]   739  EV6__EXC_SUM__SEXT2__S = ^x32	
                  [000000]   740  EV6__EXC_SUM__SEXT2__V = ^x1	
                  [000000]   741  EV6__EXC_SUM__SEXT2__M = ^x1	
                  [000000]   742  EV6__EXC_SUM__SEXT3__S = ^x33	
                  [000000]   743  EV6__EXC_SUM__SEXT3__V = ^x1	
                  [000000]   744  EV6__EXC_SUM__SEXT3__M = ^x1	
                  [000000]   745  EV6__EXC_SUM__SEXT4__S = ^x34	
                  [000000]   746  EV6__EXC_SUM__SEXT4__V = ^x1	
                  [000000]   747  EV6__EXC_SUM__SEXT4__M = ^x1	
                  [000000]   748  EV6__EXC_SUM__SEXT5__S = ^x35	
                  [000000]   749  EV6__EXC_SUM__SEXT5__V = ^x1	
                  [000000]   750  EV6__EXC_SUM__SEXT5__M = ^x1	
                  [000000]   751  EV6__EXC_SUM__SEXT6__S = ^x36	
                  [000000]   752  EV6__EXC_SUM__SEXT6__V = ^x1	
                  [000000]   753  EV6__EXC_SUM__SEXT6__M = ^x1	
                  [000000]   754  EV6__EXC_SUM__SEXT7__S = ^x37	
                  [000000]   755  EV6__EXC_SUM__SEXT7__V = ^x1	
                  [000000]   756  EV6__EXC_SUM__SEXT7__M = ^x1	
                  [000000]   757  EV6__EXC_SUM__SEXT8__S = ^x38	
                  [000000]   758  EV6__EXC_SUM__SEXT8__V = ^x1	
                  [000000]   759  EV6__EXC_SUM__SEXT8__M = ^x1	
                  [000000]   760  EV6__EXC_SUM__SEXT9__S = ^x39	
                  [000000]   761  EV6__EXC_SUM__SEXT9__V = ^x1	
                  [000000]   762  EV6__EXC_SUM__SEXT9__M = ^x1	
                  [000000]   763  EV6__EXC_SUM__SEXT10__S = ^x3a	
                  [000000]   764  EV6__EXC_SUM__SEXT10__V = ^x1	
                  [000000]   765  EV6__EXC_SUM__SEXT10__M = ^x1	
                  [000000]   766  EV6__EXC_SUM__SEXT11__S = ^x3b	
                  [000000]   767  EV6__EXC_SUM__SEXT11__V = ^x1	
                  [000000]   768  EV6__EXC_SUM__SEXT11__M = ^x1	
                  [000000]   769  EV6__EXC_SUM__SEXT12__S = ^x3c	
                  [000000]   770  EV6__EXC_SUM__SEXT12__V = ^x1	
                  [000000]   771  EV6__EXC_SUM__SEXT12__M = ^x1	
                  [000000]   772  EV6__EXC_SUM__SEXT13__S = ^x3d	
                  [000000]   773  EV6__EXC_SUM__SEXT13__V = ^x1	
                  [000000]   774  EV6__EXC_SUM__SEXT13__M = ^x1	
                  [000000]   775  EV6__EXC_SUM__SEXT14__S = ^x3e	
                  [000000]   776  EV6__EXC_SUM__SEXT14__V = ^x1	
                  [000000]   777  EV6__EXC_SUM__SEXT14__M = ^x1	
                  [000000]   778  EV6__EXC_SUM__SEXT15__S = ^x3f	
                  [000000]   779  EV6__EXC_SUM__SEXT15__V = ^x1	
                  [000000]   780  EV6__EXC_SUM__SEXT15__M = ^x1	
                  [000000]   781  
                  [000000]   782  EV6__PAL_BASE = ^x10	
                  [000000]   783  EV6__PAL_BASE__RSV1__S = ^x0	
                  [000000]   784  EV6__PAL_BASE__RSV1__V = ^xf	
                  [000000]   785  EV6__PAL_BASE__RSV1__M = ^x7fff	
                  [000000]   786  EV6__PAL_BASE__PAL_BASE__S = ^xf	
                  [000000]   787  EV6__PAL_BASE__PAL_BASE__V = ^x1d	
                  [000000]   788  EV6__PAL_BASE__PAL_BASE__M = ^x1fffffff	
                  [000000]   789  EV6__PAL_BASE__RSV2__S = ^x2c	
                  [000000]   790  EV6__PAL_BASE__RSV2__V = ^x14	
                  [000000]   791  EV6__PAL_BASE__RSV2__M = ^xfffff	
                  [000000]   792  
                  [000000]   793  EV6__I_CTL = ^x11	
                  [000000]   794  EV6__I_CTL__SPCE__S = ^x0	
                  [000000]   795  EV6__I_CTL__SPCE__V = ^x1	
                  [000000]   796  EV6__I_CTL__SPCE__M = ^x1	
                  [000000]   797  EV6__I_CTL__IC_EN__S = ^x1	
                  [000000]   798  EV6__I_CTL__IC_EN__V = ^x2	
                  [000000]   799  EV6__I_CTL__IC_EN__M = ^x3	
                  [000000]   800  EV6__I_CTL__SPE__S = ^x3	
                  [000000]   801  EV6__I_CTL__SPE__V = ^x3	
                  [000000]   802  EV6__I_CTL__SPE__M = ^x7	
                  [000000]   803  EV6__I_CTL__SDE__S = ^x6	
                  [000000]   804  EV6__I_CTL__SDE__V = ^x2	
                  [000000]   805  EV6__I_CTL__SDE__M = ^x3	
                  [000000]   806  EV6__I_CTL__SBE__S = ^x8	
                  [000000]   807  EV6__I_CTL__SBE__V = ^x2	
                  [000000]   808  EV6__I_CTL__SBE__M = ^x3	
                  [000000]   809  EV6__I_CTL__BP_MODE__S = ^xa	
                  [000000]   810  EV6__I_CTL__BP_MODE__V = ^x2	
                  [000000]   811  EV6__I_CTL__BP_MODE__M = ^x3	
                  [000000]   812  EV6__I_CTL__HWE__S = ^xc	
                  [000000]   813  EV6__I_CTL__HWE__V = ^x1	
                  [000000]   814  EV6__I_CTL__HWE__M = ^x1	
                  [000000]   815  EV6__I_CTL__SL_XMIT__S = ^xd	
                  [000000]   816  EV6__I_CTL__SL_XMIT__V = ^x1	
                  [000000]   817  EV6__I_CTL__SL_XMIT__M = ^x1	
                  [000000]   818  EV6__I_CTL__SL_RCV__S = ^xe	
                  [000000]   819  EV6__I_CTL__SL_RCV__V = ^x1	
                  [000000]   820  EV6__I_CTL__SL_RCV__M = ^x1	
                  [000000]   821  EV6__I_CTL__VA_48__S = ^xf	
                  [000000]   822  EV6__I_CTL__VA_48__V = ^x1	
                  [000000]   823  EV6__I_CTL__VA_48__M = ^x1	
                  [000000]   824  EV6__I_CTL__VA_FORM_32__S = ^x10	
                  [000000]   825  EV6__I_CTL__VA_FORM_32__V = ^x1	
                  [000000]   826  EV6__I_CTL__VA_FORM_32__M = ^x1	
                  [000000]   827  EV6__I_CTL__SINGLE_ISSUE__S = ^x11	
                  [000000]   828  EV6__I_CTL__SINGLE_ISSUE__V = ^x1	
                  [000000]   829  EV6__I_CTL__SINGLE_ISSUE__M = ^x1	
                  [000000]   830  EV6__I_CTL__PCT0_EN__S = ^x12	
                  [000000]   831  EV6__I_CTL__PCT0_EN__V = ^x1	
                  [000000]   832  EV6__I_CTL__PCT0_EN__M = ^x1	
                  [000000]   833  EV6__I_CTL__PCT1_EN__S = ^x13	
                  [000000]   834  EV6__I_CTL__PCT1_EN__V = ^x1	
                  [000000]   835  EV6__I_CTL__PCT1_EN__M = ^x1	
                  [000000]   836  EV6__I_CTL__CALL_PAL_R23__S = ^x14	
                  [000000]   837  EV6__I_CTL__CALL_PAL_R23__V = ^x1	
                  [000000]   838  EV6__I_CTL__CALL_PAL_R23__M = ^x1	
                  [000000]   839  EV6__I_CTL__MCHK_EN__S = ^x15	
                  [000000]   840  EV6__I_CTL__MCHK_EN__V = ^x1	
                  [000000]   841  EV6__I_CTL__MCHK_EN__M = ^x1	
                  [000000]   842  EV6__I_CTL__TB_MB_EN__S = ^x16	
                  [000000]   843  EV6__I_CTL__TB_MB_EN__V = ^x1	
                  [000000]   844  EV6__I_CTL__TB_MB_EN__M = ^x1	
                  [000000]   845  EV6__I_CTL__BIST_FAIL__S = ^x17	
                  [000000]   846  EV6__I_CTL__BIST_FAIL__V = ^x1	
                  [000000]   847  EV6__I_CTL__BIST_FAIL__M = ^x1	
                  [000000]   848  EV6__I_CTL__CHIP_ID__S = ^x18	
                  [000000]   849  EV6__I_CTL__CHIP_ID__V = ^x6	
                  [000000]   850  EV6__I_CTL__CHIP_ID__M = ^x3f	
                  [000000]   851  EV6__I_CTL__VPTB__S = ^x1e	
                  [000000]   852  EV6__I_CTL__VPTB__V = ^x12	
                  [000000]   853  EV6__I_CTL__VPTB__M = ^x3ffff	
                  [000000]   854  EV6__I_CTL__VPTB_SEXT0__S = ^x30	
                  [000000]   855  EV6__I_CTL__VPTB_SEXT0__V = ^x1	
                  [000000]   856  EV6__I_CTL__VPTB_SEXT0__M = ^x1	
                  [000000]   857  EV6__I_CTL__VPTB_SEXT1__S = ^x31	
                  [000000]   858  EV6__I_CTL__VPTB_SEXT1__V = ^x1	
                  [000000]   859  EV6__I_CTL__VPTB_SEXT1__M = ^x1	
                  [000000]   860  EV6__I_CTL__VPTB_SEXT2__S = ^x32	
                  [000000]   861  EV6__I_CTL__VPTB_SEXT2__V = ^x1	
                  [000000]   862  EV6__I_CTL__VPTB_SEXT2__M = ^x1	
                  [000000]   863  EV6__I_CTL__VPTB_SEXT3__S = ^x33	
                  [000000]   864  EV6__I_CTL__VPTB_SEXT3__V = ^x1	
                  [000000]   865  EV6__I_CTL__VPTB_SEXT3__M = ^x1	
                  [000000]   866  EV6__I_CTL__VPTB_SEXT4__S = ^x34	
                  [000000]   867  EV6__I_CTL__VPTB_SEXT4__V = ^x1	
                  [000000]   868  EV6__I_CTL__VPTB_SEXT4__M = ^x1	
                  [000000]   869  EV6__I_CTL__VPTB_SEXT5__S = ^x35	
                  [000000]   870  EV6__I_CTL__VPTB_SEXT5__V = ^x1	
                  [000000]   871  EV6__I_CTL__VPTB_SEXT5__M = ^x1	
                  [000000]   872  EV6__I_CTL__VPTB_SEXT6__S = ^x36	
                  [000000]   873  EV6__I_CTL__VPTB_SEXT6__V = ^x1	
                  [000000]   874  EV6__I_CTL__VPTB_SEXT6__M = ^x1	
                  [000000]   875  EV6__I_CTL__VPTB_SEXT7__S = ^x37	
                  [000000]   876  EV6__I_CTL__VPTB_SEXT7__V = ^x1	
                  [000000]   877  EV6__I_CTL__VPTB_SEXT7__M = ^x1	
                  [000000]   878  EV6__I_CTL__VPTB_SEXT8__S = ^x38	
                  [000000]   879  EV6__I_CTL__VPTB_SEXT8__V = ^x1	
                  [000000]   880  EV6__I_CTL__VPTB_SEXT8__M = ^x1	
                  [000000]   881  EV6__I_CTL__VPTB_SEXT9__S = ^x39	
                  [000000]   882  EV6__I_CTL__VPTB_SEXT9__V = ^x1	
                  [000000]   883  EV6__I_CTL__VPTB_SEXT9__M = ^x1	
                  [000000]   884  EV6__I_CTL__VPTB_SEXT10__S = ^x3a	
                  [000000]   885  EV6__I_CTL__VPTB_SEXT10__V = ^x1	
                  [000000]   886  EV6__I_CTL__VPTB_SEXT10__M = ^x1	
                  [000000]   887  EV6__I_CTL__VPTB_SEXT11__S = ^x3b	
                  [000000]   888  EV6__I_CTL__VPTB_SEXT11__V = ^x1	
                  [000000]   889  EV6__I_CTL__VPTB_SEXT11__M = ^x1	
                  [000000]   890  EV6__I_CTL__VPTB_SEXT12__S = ^x3c	
                  [000000]   891  EV6__I_CTL__VPTB_SEXT12__V = ^x1	
                  [000000]   892  EV6__I_CTL__VPTB_SEXT12__M = ^x1	
                  [000000]   893  EV6__I_CTL__VPTB_SEXT13__S = ^x3d	
                  [000000]   894  EV6__I_CTL__VPTB_SEXT13__V = ^x1	
                  [000000]   895  EV6__I_CTL__VPTB_SEXT13__M = ^x1	
                  [000000]   896  EV6__I_CTL__VPTB_SEXT14__S = ^x3e	
                  [000000]   897  EV6__I_CTL__VPTB_SEXT14__V = ^x1	
                  [000000]   898  EV6__I_CTL__VPTB_SEXT14__M = ^x1	
                  [000000]   899  EV6__I_CTL__VPTB_SEXT15__S = ^x3f	
                  [000000]   900  EV6__I_CTL__VPTB_SEXT15__V = ^x1	
                  [000000]   901  EV6__I_CTL__VPTB_SEXT15__M = ^x1	
                  [000000]   902  
                  [000000]   903  EV6__IC_FLUSH_ASM = ^x12	
                  [000000]   904  EV6__IC_FLUSH_ASM__RSV__S = ^x0	
                  [000000]   905  EV6__IC_FLUSH_ASM__RSV__V = ^x40	
                  [000000]   906  EV6__IC_FLUSH_ASM__RSV__M = ^xffffffffffffffff	
                  [000000]   907  
                  [000000]   908  EV6__IC_FLUSH = ^x13	
                  [000000]   909  EV6__IC_FLUSH__RSV__S = ^x0	
                  [000000]   910  EV6__IC_FLUSH__RSV__V = ^x40	
                  [000000]   911  EV6__IC_FLUSH__RSV__M = ^xffffffffffffffff	
                  [000000]   912  
                  [000000]   913  EV6__PCTR_CTL = ^x14	
                  [000000]   914  EV6__PCTR_CTL__TAK__S = ^x0	
                  [000000]   915  EV6__PCTR_CTL__TAK__V = ^x1	
                  [000000]   916  EV6__PCTR_CTL__TAK__M = ^x1	
                  [000000]   917  EV6__PCTR_CTL__VAL__S = ^x1	
                  [000000]   918  EV6__PCTR_CTL__VAL__V = ^x1	
                  [000000]   919  EV6__PCTR_CTL__VAL__M = ^x1	
                  [000000]   920  EV6__PCTR_CTL__SL1__S = ^x2	
                  [000000]   921  EV6__PCTR_CTL__SL1__V = ^x2	
                  [000000]   922  EV6__PCTR_CTL__SL1__M = ^x3	
                  [000000]   923  EV6__PCTR_CTL__SL0__S = ^x4	
                  [000000]   924  EV6__PCTR_CTL__SL0__V = ^x1	
                  [000000]   925  EV6__PCTR_CTL__SL0__M = ^x1	
                  [000000]   926  EV6__PCTR_CTL__RSV1__S = ^x5	
                  [000000]   927  EV6__PCTR_CTL__RSV1__V = ^x1	
                  [000000]   928  EV6__PCTR_CTL__RSV1__M = ^x1	
                  [000000]   929  EV6__PCTR_CTL__PCTR1__S = ^x6	
                  [000000]   930  EV6__PCTR_CTL__PCTR1__V = ^x14	
                  [000000]   931  EV6__PCTR_CTL__PCTR1__M = ^xfffff	
                  [000000]   932  EV6__PCTR_CTL__PM_KILL__S = ^x1a	
                  [000000]   933  EV6__PCTR_CTL__PM_KILL__V = ^x1	
                  [000000]   934  EV6__PCTR_CTL__PM_KILL__M = ^x1	
                  [000000]   935  EV6__PCTR_CTL__PM_STALL__S = ^x1b	
                  [000000]   936  EV6__PCTR_CTL__PM_STALL__V = ^x1	
                  [000000]   937  EV6__PCTR_CTL__PM_STALL__M = ^x1	
                  [000000]   938  EV6__PCTR_CTL__PCTR0__S = ^x1c	
                  [000000]   939  EV6__PCTR_CTL__PCTR0__V = ^x14	
                  [000000]   940  EV6__PCTR_CTL__PCTR0__M = ^xfffff	
                  [000000]   941  EV6__PCTR_CTL__RSV2__S = ^x30	
                  [000000]   942  EV6__PCTR_CTL__RSV2__V = ^x10	
                  [000000]   943  EV6__PCTR_CTL__RSV2__M = ^xffff	
                  [000000]   944  
                  [000000]   945  EV6__CLR_MAP = ^x15	
                  [000000]   946  EV6__CLR_MAP__RSV__S = ^x0	
                  [000000]   947  EV6__CLR_MAP__RSV__V = ^x40	
                  [000000]   948  EV6__CLR_MAP__RSV__M = ^xffffffffffffffff	
                  [000000]   949  
                  [000000]   950  EV6__I_STAT = ^x16	
                  [000000]   951  EV6__I_STAT__RSV1__S = ^x0	
                  [000000]   952  EV6__I_STAT__RSV1__V = ^x1d	
                  [000000]   953  EV6__I_STAT__RSV1__M = ^x1fffffff	
                  [000000]   954  EV6__I_STAT__PAR__S = ^x1d	
                  [000000]   955  EV6__I_STAT__PAR__V = ^x1	
                  [000000]   956  EV6__I_STAT__PAR__M = ^x1	
                  [000000]   957  EV6__I_STAT__OVR__S = ^x1e	
                  [000000]   958  EV6__I_STAT__OVR__V = ^x3	
                  [000000]   959  EV6__I_STAT__OVR__M = ^x7	
                  [000000]   960  EV6__I_STAT__ICM__S = ^x21	
                  [000000]   961  EV6__I_STAT__ICM__V = ^x1	
                  [000000]   962  EV6__I_STAT__ICM__M = ^x1	
                  [000000]   963  EV6__I_STAT__TRAP_TYPE__S = ^x22	
                  [000000]   964  EV6__I_STAT__TRAP_TYPE__V = ^x4	
                  [000000]   965  EV6__I_STAT__TRAP_TYPE__M = ^xf	
                  [000000]   966  EV6__I_STAT__LS0__S = ^x26	
                  [000000]   967  EV6__I_STAT__LS0__V = ^x1	
                  [000000]   968  EV6__I_STAT__LS0__M = ^x1	
                  [000000]   969  EV6__I_STAT__TRP__S = ^x27	
                  [000000]   970  EV6__I_STAT__TRP__V = ^x1	
                  [000000]   971  EV6__I_STAT__TRP__M = ^x1	
                  [000000]   972  EV6__I_STAT__MIS__S = ^x28	
                  [000000]   973  EV6__I_STAT__MIS__V = ^x1	
                  [000000]   974  EV6__I_STAT__MIS__M = ^x1	
                  [000000]   975  EV6__I_STAT__RSV2__S = ^x29	
                  [000000]   976  EV6__I_STAT__RSV2__V = ^x17	
                  [000000]   977  EV6__I_STAT__RSV2__M = ^x7fffff	
                  [000000]   978  
                  [000000]   979  EV6__SLEEP = ^x17	
                  [000000]   980  EV6__SLEEP__RSV__S = ^x0	
                  [000000]   981  EV6__SLEEP__RSV__V = ^x40	
                  [000000]   982  EV6__SLEEP__RSV__M = ^xffffffffffffffff	
                  [000000]   983  
                  [000000]   984  EV6__ASN = ^x41	
                  [000000]   985  EV6__ASN__RSV0__S = ^x0	
                  [000000]   986  EV6__ASN__RSV0__V = ^x1	
                  [000000]   987  EV6__ASN__RSV0__M = ^x1	
                  [000000]   988  EV6__ASN__PPCE__S = ^x1	
                  [000000]   989  EV6__ASN__PPCE__V = ^x1	
                  [000000]   990  EV6__ASN__PPCE__M = ^x1	
                  [000000]   991  EV6__ASN__FPE__S = ^x2	
                  [000000]   992  EV6__ASN__FPE__V = ^x1	
                  [000000]   993  EV6__ASN__FPE__M = ^x1	
                  [000000]   994  EV6__ASN__RSV1__S = ^x3	
                  [000000]   995  EV6__ASN__RSV1__V = ^x2	
                  [000000]   996  EV6__ASN__RSV1__M = ^x3	
                  [000000]   997  EV6__ASN__ASTER__S = ^x5	
                  [000000]   998  EV6__ASN__ASTER__V = ^x4	
                  [000000]   999  EV6__ASN__ASTER__M = ^xf	
                  [000000]  1000  EV6__ASN__ASTRR__S = ^x9	
                  [000000]  1001  EV6__ASN__ASTRR__V = ^x4	
                  [000000]  1002  EV6__ASN__ASTRR__M = ^xf	
                  [000000]  1003  EV6__ASN__RSV2__S = ^xd	
                  [000000]  1004  EV6__ASN__RSV2__V = ^x1a	
                  [000000]  1005  EV6__ASN__RSV2__M = ^x3ffffff	
                  [000000]  1006  EV6__ASN__ASN__S = ^x27	
                  [000000]  1007  EV6__ASN__ASN__V = ^x8	
                  [000000]  1008  EV6__ASN__ASN__M = ^xff	
                  [000000]  1009  EV6__ASN__RSV3__S = ^x2f	
                  [000000]  1010  EV6__ASN__RSV3__V = ^x11	
                  [000000]  1011  EV6__ASN__RSV3__M = ^x1ffff	
                  [000000]  1012  
                  [000000]  1013  EV6__ASTER = ^x42	
                  [000000]  1014  EV6__ASTER__RSV0__S = ^x0	
                  [000000]  1015  EV6__ASTER__RSV0__V = ^x1	
                  [000000]  1016  EV6__ASTER__RSV0__M = ^x1	
                  [000000]  1017  EV6__ASTER__PPCE__S = ^x1	
                  [000000]  1018  EV6__ASTER__PPCE__V = ^x1	
                  [000000]  1019  EV6__ASTER__PPCE__M = ^x1	
                  [000000]  1020  EV6__ASTER__FPE__S = ^x2	
                  [000000]  1021  EV6__ASTER__FPE__V = ^x1	
                  [000000]  1022  EV6__ASTER__FPE__M = ^x1	
                  [000000]  1023  EV6__ASTER__RSV1__S = ^x3	
                  [000000]  1024  EV6__ASTER__RSV1__V = ^x2	
                  [000000]  1025  EV6__ASTER__RSV1__M = ^x3	
                  [000000]  1026  EV6__ASTER__ASTER__S = ^x5	
                  [000000]  1027  EV6__ASTER__ASTER__V = ^x4	
                  [000000]  1028  EV6__ASTER__ASTER__M = ^xf	
                  [000000]  1029  EV6__ASTER__ASTRR__S = ^x9	
                  [000000]  1030  EV6__ASTER__ASTRR__V = ^x4	
                  [000000]  1031  EV6__ASTER__ASTRR__M = ^xf	
                  [000000]  1032  EV6__ASTER__RSV2__S = ^xd	
                  [000000]  1033  EV6__ASTER__RSV2__V = ^x1a	
                  [000000]  1034  EV6__ASTER__RSV2__M = ^x3ffffff	
                  [000000]  1035  EV6__ASTER__ASN__S = ^x27	
                  [000000]  1036  EV6__ASTER__ASN__V = ^x8	
                  [000000]  1037  EV6__ASTER__ASN__M = ^xff	
                  [000000]  1038  EV6__ASTER__RSV3__S = ^x2f	
                  [000000]  1039  EV6__ASTER__RSV3__V = ^x11	
                  [000000]  1040  EV6__ASTER__RSV3__M = ^x1ffff	
                  [000000]  1041  
                  [000000]  1042  EV6__ASTRR = ^x44	
                  [000000]  1043  EV6__ASTRR__RSV0__S = ^x0	
                  [000000]  1044  EV6__ASTRR__RSV0__V = ^x1	
                  [000000]  1045  EV6__ASTRR__RSV0__M = ^x1	
                  [000000]  1046  EV6__ASTRR__PPCE__S = ^x1	
                  [000000]  1047  EV6__ASTRR__PPCE__V = ^x1	
                  [000000]  1048  EV6__ASTRR__PPCE__M = ^x1	
                  [000000]  1049  EV6__ASTRR__FPE__S = ^x2	
                  [000000]  1050  EV6__ASTRR__FPE__V = ^x1	
                  [000000]  1051  EV6__ASTRR__FPE__M = ^x1	
                  [000000]  1052  EV6__ASTRR__RSV1__S = ^x3	
                  [000000]  1053  EV6__ASTRR__RSV1__V = ^x2	
                  [000000]  1054  EV6__ASTRR__RSV1__M = ^x3	
                  [000000]  1055  EV6__ASTRR__ASTER__S = ^x5	
                  [000000]  1056  EV6__ASTRR__ASTER__V = ^x4	
                  [000000]  1057  EV6__ASTRR__ASTER__M = ^xf	
                  [000000]  1058  EV6__ASTRR__ASTRR__S = ^x9	
                  [000000]  1059  EV6__ASTRR__ASTRR__V = ^x4	
                  [000000]  1060  EV6__ASTRR__ASTRR__M = ^xf	
                  [000000]  1061  EV6__ASTRR__RSV2__S = ^xd	
                  [000000]  1062  EV6__ASTRR__RSV2__V = ^x1a	
                  [000000]  1063  EV6__ASTRR__RSV2__M = ^x3ffffff	
                  [000000]  1064  EV6__ASTRR__ASN__S = ^x27	
                  [000000]  1065  EV6__ASTRR__ASN__V = ^x8	
                  [000000]  1066  EV6__ASTRR__ASN__M = ^xff	
                  [000000]  1067  EV6__ASTRR__RSV3__S = ^x2f	
                  [000000]  1068  EV6__ASTRR__RSV3__V = ^x11	
                  [000000]  1069  EV6__ASTRR__RSV3__M = ^x1ffff	
                  [000000]  1070  
                  [000000]  1071  EV6__PPCE = ^x48	
                  [000000]  1072  EV6__PPCE__RSV0__S = ^x0	
                  [000000]  1073  EV6__PPCE__RSV0__V = ^x1	
                  [000000]  1074  EV6__PPCE__RSV0__M = ^x1	
                  [000000]  1075  EV6__PPCE__PPCE__S = ^x1	
                  [000000]  1076  EV6__PPCE__PPCE__V = ^x1	
                  [000000]  1077  EV6__PPCE__PPCE__M = ^x1	
                  [000000]  1078  EV6__PPCE__FPE__S = ^x2	
                  [000000]  1079  EV6__PPCE__FPE__V = ^x1	
                  [000000]  1080  EV6__PPCE__FPE__M = ^x1	
                  [000000]  1081  EV6__PPCE__RSV1__S = ^x3	
                  [000000]  1082  EV6__PPCE__RSV1__V = ^x2	
                  [000000]  1083  EV6__PPCE__RSV1__M = ^x3	
                  [000000]  1084  EV6__PPCE__ASTER__S = ^x5	
                  [000000]  1085  EV6__PPCE__ASTER__V = ^x4	
                  [000000]  1086  EV6__PPCE__ASTER__M = ^xf	
                  [000000]  1087  EV6__PPCE__ASTRR__S = ^x9	
                  [000000]  1088  EV6__PPCE__ASTRR__V = ^x4	
                  [000000]  1089  EV6__PPCE__ASTRR__M = ^xf	
                  [000000]  1090  EV6__PPCE__RSV2__S = ^xd	
                  [000000]  1091  EV6__PPCE__RSV2__V = ^x1a	
                  [000000]  1092  EV6__PPCE__RSV2__M = ^x3ffffff	
                  [000000]  1093  EV6__PPCE__ASN__S = ^x27	
                  [000000]  1094  EV6__PPCE__ASN__V = ^x8	
                  [000000]  1095  EV6__PPCE__ASN__M = ^xff	
                  [000000]  1096  EV6__PPCE__RSV3__S = ^x2f	
                  [000000]  1097  EV6__PPCE__RSV3__V = ^x11	
                  [000000]  1098  EV6__PPCE__RSV3__M = ^x1ffff	
                  [000000]  1099  
                  [000000]  1100  EV6__FPE = ^x50	
                  [000000]  1101  EV6__FPE__RSV0__S = ^x0	
                  [000000]  1102  EV6__FPE__RSV0__V = ^x1	
                  [000000]  1103  EV6__FPE__RSV0__M = ^x1	
                  [000000]  1104  EV6__FPE__PPCE__S = ^x1	
                  [000000]  1105  EV6__FPE__PPCE__V = ^x1	
                  [000000]  1106  EV6__FPE__PPCE__M = ^x1	
                  [000000]  1107  EV6__FPE__FPE__S = ^x2	
                  [000000]  1108  EV6__FPE__FPE__V = ^x1	
                  [000000]  1109  EV6__FPE__FPE__M = ^x1	
                  [000000]  1110  EV6__FPE__RSV1__S = ^x3	
                  [000000]  1111  EV6__FPE__RSV1__V = ^x2	
                  [000000]  1112  EV6__FPE__RSV1__M = ^x3	
                  [000000]  1113  EV6__FPE__ASTER__S = ^x5	
                  [000000]  1114  EV6__FPE__ASTER__V = ^x4	
                  [000000]  1115  EV6__FPE__ASTER__M = ^xf	
                  [000000]  1116  EV6__FPE__ASTRR__S = ^x9	
                  [000000]  1117  EV6__FPE__ASTRR__V = ^x4	
                  [000000]  1118  EV6__FPE__ASTRR__M = ^xf	
                  [000000]  1119  EV6__FPE__RSV2__S = ^xd	
                  [000000]  1120  EV6__FPE__RSV2__V = ^x1a	
                  [000000]  1121  EV6__FPE__RSV2__M = ^x3ffffff	
                  [000000]  1122  EV6__FPE__ASN__S = ^x27	
                  [000000]  1123  EV6__FPE__ASN__V = ^x8	
                  [000000]  1124  EV6__FPE__ASN__M = ^xff	
                  [000000]  1125  EV6__FPE__RSV3__S = ^x2f	
                  [000000]  1126  EV6__FPE__RSV3__V = ^x11	
                  [000000]  1127  EV6__FPE__RSV3__M = ^x1ffff	
                  [000000]  1128  
                  [000000]  1129  EV6__ASN_ASTER = ^x43	
                  [000000]  1130  EV6__ASN_ASTER__RSV0__S = ^x0	
                  [000000]  1131  EV6__ASN_ASTER__RSV0__V = ^x1	
                  [000000]  1132  EV6__ASN_ASTER__RSV0__M = ^x1	
                  [000000]  1133  EV6__ASN_ASTER__PPCE__S = ^x1	
                  [000000]  1134  EV6__ASN_ASTER__PPCE__V = ^x1	
                  [000000]  1135  EV6__ASN_ASTER__PPCE__M = ^x1	
                  [000000]  1136  EV6__ASN_ASTER__FPE__S = ^x2	
                  [000000]  1137  EV6__ASN_ASTER__FPE__V = ^x1	
                  [000000]  1138  EV6__ASN_ASTER__FPE__M = ^x1	
                  [000000]  1139  EV6__ASN_ASTER__RSV1__S = ^x3	
                  [000000]  1140  EV6__ASN_ASTER__RSV1__V = ^x2	
                  [000000]  1141  EV6__ASN_ASTER__RSV1__M = ^x3	
                  [000000]  1142  EV6__ASN_ASTER__ASTER__S = ^x5	
                  [000000]  1143  EV6__ASN_ASTER__ASTER__V = ^x4	
                  [000000]  1144  EV6__ASN_ASTER__ASTER__M = ^xf	
                  [000000]  1145  EV6__ASN_ASTER__ASTRR__S = ^x9	
                  [000000]  1146  EV6__ASN_ASTER__ASTRR__V = ^x4	
                  [000000]  1147  EV6__ASN_ASTER__ASTRR__M = ^xf	
                  [000000]  1148  EV6__ASN_ASTER__RSV2__S = ^xd	
                  [000000]  1149  EV6__ASN_ASTER__RSV2__V = ^x1a	
                  [000000]  1150  EV6__ASN_ASTER__RSV2__M = ^x3ffffff	
                  [000000]  1151  EV6__ASN_ASTER__ASN__S = ^x27	
                  [000000]  1152  EV6__ASN_ASTER__ASN__V = ^x8	
                  [000000]  1153  EV6__ASN_ASTER__ASN__M = ^xff	
                  [000000]  1154  EV6__ASN_ASTER__RSV3__S = ^x2f	
                  [000000]  1155  EV6__ASN_ASTER__RSV3__V = ^x11	
                  [000000]  1156  EV6__ASN_ASTER__RSV3__M = ^x1ffff	
                  [000000]  1157  
                  [000000]  1158  EV6__ASN_ASTRR = ^x45	
                  [000000]  1159  EV6__ASN_ASTRR__RSV0__S = ^x0	
                  [000000]  1160  EV6__ASN_ASTRR__RSV0__V = ^x1	
                  [000000]  1161  EV6__ASN_ASTRR__RSV0__M = ^x1	
                  [000000]  1162  EV6__ASN_ASTRR__PPCE__S = ^x1	
                  [000000]  1163  EV6__ASN_ASTRR__PPCE__V = ^x1	
                  [000000]  1164  EV6__ASN_ASTRR__PPCE__M = ^x1	
                  [000000]  1165  EV6__ASN_ASTRR__FPE__S = ^x2	
                  [000000]  1166  EV6__ASN_ASTRR__FPE__V = ^x1	
                  [000000]  1167  EV6__ASN_ASTRR__FPE__M = ^x1	
                  [000000]  1168  EV6__ASN_ASTRR__RSV1__S = ^x3	
                  [000000]  1169  EV6__ASN_ASTRR__RSV1__V = ^x2	
                  [000000]  1170  EV6__ASN_ASTRR__RSV1__M = ^x3	
                  [000000]  1171  EV6__ASN_ASTRR__ASTER__S = ^x5	
                  [000000]  1172  EV6__ASN_ASTRR__ASTER__V = ^x4	
                  [000000]  1173  EV6__ASN_ASTRR__ASTER__M = ^xf	
                  [000000]  1174  EV6__ASN_ASTRR__ASTRR__S = ^x9	
                  [000000]  1175  EV6__ASN_ASTRR__ASTRR__V = ^x4	
                  [000000]  1176  EV6__ASN_ASTRR__ASTRR__M = ^xf	
                  [000000]  1177  EV6__ASN_ASTRR__RSV2__S = ^xd	
                  [000000]  1178  EV6__ASN_ASTRR__RSV2__V = ^x1a	
                  [000000]  1179  EV6__ASN_ASTRR__RSV2__M = ^x3ffffff	
                  [000000]  1180  EV6__ASN_ASTRR__ASN__S = ^x27	
                  [000000]  1181  EV6__ASN_ASTRR__ASN__V = ^x8	
                  [000000]  1182  EV6__ASN_ASTRR__ASN__M = ^xff	
                  [000000]  1183  EV6__ASN_ASTRR__RSV3__S = ^x2f	
                  [000000]  1184  EV6__ASN_ASTRR__RSV3__V = ^x11	
                  [000000]  1185  EV6__ASN_ASTRR__RSV3__M = ^x1ffff	
                  [000000]  1186  
                  [000000]  1187  EV6__ASN_PPCE = ^x49	
                  [000000]  1188  EV6__ASN_PPCE__RSV0__S = ^x0	
                  [000000]  1189  EV6__ASN_PPCE__RSV0__V = ^x1	
                  [000000]  1190  EV6__ASN_PPCE__RSV0__M = ^x1	
                  [000000]  1191  EV6__ASN_PPCE__PPCE__S = ^x1	
                  [000000]  1192  EV6__ASN_PPCE__PPCE__V = ^x1	
                  [000000]  1193  EV6__ASN_PPCE__PPCE__M = ^x1	
                  [000000]  1194  EV6__ASN_PPCE__FPE__S = ^x2	
                  [000000]  1195  EV6__ASN_PPCE__FPE__V = ^x1	
                  [000000]  1196  EV6__ASN_PPCE__FPE__M = ^x1	
                  [000000]  1197  EV6__ASN_PPCE__RSV1__S = ^x3	
                  [000000]  1198  EV6__ASN_PPCE__RSV1__V = ^x2	
                  [000000]  1199  EV6__ASN_PPCE__RSV1__M = ^x3	
                  [000000]  1200  EV6__ASN_PPCE__ASTER__S = ^x5	
                  [000000]  1201  EV6__ASN_PPCE__ASTER__V = ^x4	
                  [000000]  1202  EV6__ASN_PPCE__ASTER__M = ^xf	
                  [000000]  1203  EV6__ASN_PPCE__ASTRR__S = ^x9	
                  [000000]  1204  EV6__ASN_PPCE__ASTRR__V = ^x4	
                  [000000]  1205  EV6__ASN_PPCE__ASTRR__M = ^xf	
                  [000000]  1206  EV6__ASN_PPCE__RSV2__S = ^xd	
                  [000000]  1207  EV6__ASN_PPCE__RSV2__V = ^x1a	
                  [000000]  1208  EV6__ASN_PPCE__RSV2__M = ^x3ffffff	
                  [000000]  1209  EV6__ASN_PPCE__ASN__S = ^x27	
                  [000000]  1210  EV6__ASN_PPCE__ASN__V = ^x8	
                  [000000]  1211  EV6__ASN_PPCE__ASN__M = ^xff	
                  [000000]  1212  EV6__ASN_PPCE__RSV3__S = ^x2f	
                  [000000]  1213  EV6__ASN_PPCE__RSV3__V = ^x11	
                  [000000]  1214  EV6__ASN_PPCE__RSV3__M = ^x1ffff	
                  [000000]  1215  
                  [000000]  1216  EV6__ASN_FPE = ^x51	
                  [000000]  1217  EV6__ASN_FPE__RSV0__S = ^x0	
                  [000000]  1218  EV6__ASN_FPE__RSV0__V = ^x1	
                  [000000]  1219  EV6__ASN_FPE__RSV0__M = ^x1	
                  [000000]  1220  EV6__ASN_FPE__PPCE__S = ^x1	
                  [000000]  1221  EV6__ASN_FPE__PPCE__V = ^x1	
                  [000000]  1222  EV6__ASN_FPE__PPCE__M = ^x1	
                  [000000]  1223  EV6__ASN_FPE__FPE__S = ^x2	
                  [000000]  1224  EV6__ASN_FPE__FPE__V = ^x1	
                  [000000]  1225  EV6__ASN_FPE__FPE__M = ^x1	
                  [000000]  1226  EV6__ASN_FPE__RSV1__S = ^x3	
                  [000000]  1227  EV6__ASN_FPE__RSV1__V = ^x2	
                  [000000]  1228  EV6__ASN_FPE__RSV1__M = ^x3	
                  [000000]  1229  EV6__ASN_FPE__ASTER__S = ^x5	
                  [000000]  1230  EV6__ASN_FPE__ASTER__V = ^x4	
                  [000000]  1231  EV6__ASN_FPE__ASTER__M = ^xf	
                  [000000]  1232  EV6__ASN_FPE__ASTRR__S = ^x9	
                  [000000]  1233  EV6__ASN_FPE__ASTRR__V = ^x4	
                  [000000]  1234  EV6__ASN_FPE__ASTRR__M = ^xf	
                  [000000]  1235  EV6__ASN_FPE__RSV2__S = ^xd	
                  [000000]  1236  EV6__ASN_FPE__RSV2__V = ^x1a	
                  [000000]  1237  EV6__ASN_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1238  EV6__ASN_FPE__ASN__S = ^x27	
                  [000000]  1239  EV6__ASN_FPE__ASN__V = ^x8	
                  [000000]  1240  EV6__ASN_FPE__ASN__M = ^xff	
                  [000000]  1241  EV6__ASN_FPE__RSV3__S = ^x2f	
                  [000000]  1242  EV6__ASN_FPE__RSV3__V = ^x11	
                  [000000]  1243  EV6__ASN_FPE__RSV3__M = ^x1ffff	
                  [000000]  1244  
                  [000000]  1245  EV6__ASTER_ASTRR = ^x46	
                  [000000]  1246  EV6__ASTER_ASTRR__RSV0__S = ^x0	
                  [000000]  1247  EV6__ASTER_ASTRR__RSV0__V = ^x1	
                  [000000]  1248  EV6__ASTER_ASTRR__RSV0__M = ^x1	
                  [000000]  1249  EV6__ASTER_ASTRR__PPCE__S = ^x1	
                  [000000]  1250  EV6__ASTER_ASTRR__PPCE__V = ^x1	
                  [000000]  1251  EV6__ASTER_ASTRR__PPCE__M = ^x1	
                  [000000]  1252  EV6__ASTER_ASTRR__FPE__S = ^x2	
                  [000000]  1253  EV6__ASTER_ASTRR__FPE__V = ^x1	
                  [000000]  1254  EV6__ASTER_ASTRR__FPE__M = ^x1	
                  [000000]  1255  EV6__ASTER_ASTRR__RSV1__S = ^x3	
                  [000000]  1256  EV6__ASTER_ASTRR__RSV1__V = ^x2	
                  [000000]  1257  EV6__ASTER_ASTRR__RSV1__M = ^x3	
                  [000000]  1258  EV6__ASTER_ASTRR__ASTER__S = ^x5	
                  [000000]  1259  EV6__ASTER_ASTRR__ASTER__V = ^x4	
                  [000000]  1260  EV6__ASTER_ASTRR__ASTER__M = ^xf	
                  [000000]  1261  EV6__ASTER_ASTRR__ASTRR__S = ^x9	
                  [000000]  1262  EV6__ASTER_ASTRR__ASTRR__V = ^x4	
                  [000000]  1263  EV6__ASTER_ASTRR__ASTRR__M = ^xf	
                  [000000]  1264  EV6__ASTER_ASTRR__RSV2__S = ^xd	
                  [000000]  1265  EV6__ASTER_ASTRR__RSV2__V = ^x1a	
                  [000000]  1266  EV6__ASTER_ASTRR__RSV2__M = ^x3ffffff	
                  [000000]  1267  EV6__ASTER_ASTRR__ASN__S = ^x27	
                  [000000]  1268  EV6__ASTER_ASTRR__ASN__V = ^x8	
                  [000000]  1269  EV6__ASTER_ASTRR__ASN__M = ^xff	
                  [000000]  1270  EV6__ASTER_ASTRR__RSV3__S = ^x2f	
                  [000000]  1271  EV6__ASTER_ASTRR__RSV3__V = ^x11	
                  [000000]  1272  EV6__ASTER_ASTRR__RSV3__M = ^x1ffff	
                  [000000]  1273  
                  [000000]  1274  EV6__ASTER_PPCE = ^x4a	
                  [000000]  1275  EV6__ASTER_PPCE__RSV0__S = ^x0	
                  [000000]  1276  EV6__ASTER_PPCE__RSV0__V = ^x1	
                  [000000]  1277  EV6__ASTER_PPCE__RSV0__M = ^x1	
                  [000000]  1278  EV6__ASTER_PPCE__PPCE__S = ^x1	
                  [000000]  1279  EV6__ASTER_PPCE__PPCE__V = ^x1	
                  [000000]  1280  EV6__ASTER_PPCE__PPCE__M = ^x1	
                  [000000]  1281  EV6__ASTER_PPCE__FPE__S = ^x2	
                  [000000]  1282  EV6__ASTER_PPCE__FPE__V = ^x1	
                  [000000]  1283  EV6__ASTER_PPCE__FPE__M = ^x1	
                  [000000]  1284  EV6__ASTER_PPCE__RSV1__S = ^x3	
                  [000000]  1285  EV6__ASTER_PPCE__RSV1__V = ^x2	
                  [000000]  1286  EV6__ASTER_PPCE__RSV1__M = ^x3	
                  [000000]  1287  EV6__ASTER_PPCE__ASTER__S = ^x5	
                  [000000]  1288  EV6__ASTER_PPCE__ASTER__V = ^x4	
                  [000000]  1289  EV6__ASTER_PPCE__ASTER__M = ^xf	
                  [000000]  1290  EV6__ASTER_PPCE__ASTRR__S = ^x9	
                  [000000]  1291  EV6__ASTER_PPCE__ASTRR__V = ^x4	
                  [000000]  1292  EV6__ASTER_PPCE__ASTRR__M = ^xf	
                  [000000]  1293  EV6__ASTER_PPCE__RSV2__S = ^xd	
                  [000000]  1294  EV6__ASTER_PPCE__RSV2__V = ^x1a	
                  [000000]  1295  EV6__ASTER_PPCE__RSV2__M = ^x3ffffff	
                  [000000]  1296  EV6__ASTER_PPCE__ASN__S = ^x27	
                  [000000]  1297  EV6__ASTER_PPCE__ASN__V = ^x8	
                  [000000]  1298  EV6__ASTER_PPCE__ASN__M = ^xff	
                  [000000]  1299  EV6__ASTER_PPCE__RSV3__S = ^x2f	
                  [000000]  1300  EV6__ASTER_PPCE__RSV3__V = ^x11	
                  [000000]  1301  EV6__ASTER_PPCE__RSV3__M = ^x1ffff	
                  [000000]  1302  
                  [000000]  1303  EV6__ASTER_FPE = ^x52	
                  [000000]  1304  EV6__ASTER_FPE__RSV0__S = ^x0	
                  [000000]  1305  EV6__ASTER_FPE__RSV0__V = ^x1	
                  [000000]  1306  EV6__ASTER_FPE__RSV0__M = ^x1	
                  [000000]  1307  EV6__ASTER_FPE__PPCE__S = ^x1	
                  [000000]  1308  EV6__ASTER_FPE__PPCE__V = ^x1	
                  [000000]  1309  EV6__ASTER_FPE__PPCE__M = ^x1	
                  [000000]  1310  EV6__ASTER_FPE__FPE__S = ^x2	
                  [000000]  1311  EV6__ASTER_FPE__FPE__V = ^x1	
                  [000000]  1312  EV6__ASTER_FPE__FPE__M = ^x1	
                  [000000]  1313  EV6__ASTER_FPE__RSV1__S = ^x3	
                  [000000]  1314  EV6__ASTER_FPE__RSV1__V = ^x2	
                  [000000]  1315  EV6__ASTER_FPE__RSV1__M = ^x3	
                  [000000]  1316  EV6__ASTER_FPE__ASTER__S = ^x5	
                  [000000]  1317  EV6__ASTER_FPE__ASTER__V = ^x4	
                  [000000]  1318  EV6__ASTER_FPE__ASTER__M = ^xf	
                  [000000]  1319  EV6__ASTER_FPE__ASTRR__S = ^x9	
                  [000000]  1320  EV6__ASTER_FPE__ASTRR__V = ^x4	
                  [000000]  1321  EV6__ASTER_FPE__ASTRR__M = ^xf	
                  [000000]  1322  EV6__ASTER_FPE__RSV2__S = ^xd	
                  [000000]  1323  EV6__ASTER_FPE__RSV2__V = ^x1a	
                  [000000]  1324  EV6__ASTER_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1325  EV6__ASTER_FPE__ASN__S = ^x27	
                  [000000]  1326  EV6__ASTER_FPE__ASN__V = ^x8	
                  [000000]  1327  EV6__ASTER_FPE__ASN__M = ^xff	
                  [000000]  1328  EV6__ASTER_FPE__RSV3__S = ^x2f	
                  [000000]  1329  EV6__ASTER_FPE__RSV3__V = ^x11	
                  [000000]  1330  EV6__ASTER_FPE__RSV3__M = ^x1ffff	
                  [000000]  1331  
                  [000000]  1332  EV6__ASTRR_PPCE = ^x4c	
                  [000000]  1333  EV6__ASTRR_PPCE__RSV0__S = ^x0	
                  [000000]  1334  EV6__ASTRR_PPCE__RSV0__V = ^x1	
                  [000000]  1335  EV6__ASTRR_PPCE__RSV0__M = ^x1	
                  [000000]  1336  EV6__ASTRR_PPCE__PPCE__S = ^x1	
                  [000000]  1337  EV6__ASTRR_PPCE__PPCE__V = ^x1	
                  [000000]  1338  EV6__ASTRR_PPCE__PPCE__M = ^x1	
                  [000000]  1339  EV6__ASTRR_PPCE__FPE__S = ^x2	
                  [000000]  1340  EV6__ASTRR_PPCE__FPE__V = ^x1	
                  [000000]  1341  EV6__ASTRR_PPCE__FPE__M = ^x1	
                  [000000]  1342  EV6__ASTRR_PPCE__RSV1__S = ^x3	
                  [000000]  1343  EV6__ASTRR_PPCE__RSV1__V = ^x2	
                  [000000]  1344  EV6__ASTRR_PPCE__RSV1__M = ^x3	
                  [000000]  1345  EV6__ASTRR_PPCE__ASTER__S = ^x5	
                  [000000]  1346  EV6__ASTRR_PPCE__ASTER__V = ^x4	
                  [000000]  1347  EV6__ASTRR_PPCE__ASTER__M = ^xf	
                  [000000]  1348  EV6__ASTRR_PPCE__ASTRR__S = ^x9	
                  [000000]  1349  EV6__ASTRR_PPCE__ASTRR__V = ^x4	
                  [000000]  1350  EV6__ASTRR_PPCE__ASTRR__M = ^xf	
                  [000000]  1351  EV6__ASTRR_PPCE__RSV2__S = ^xd	
                  [000000]  1352  EV6__ASTRR_PPCE__RSV2__V = ^x1a	
                  [000000]  1353  EV6__ASTRR_PPCE__RSV2__M = ^x3ffffff	
                  [000000]  1354  EV6__ASTRR_PPCE__ASN__S = ^x27	
                  [000000]  1355  EV6__ASTRR_PPCE__ASN__V = ^x8	
                  [000000]  1356  EV6__ASTRR_PPCE__ASN__M = ^xff	
                  [000000]  1357  EV6__ASTRR_PPCE__RSV3__S = ^x2f	
                  [000000]  1358  EV6__ASTRR_PPCE__RSV3__V = ^x11	
                  [000000]  1359  EV6__ASTRR_PPCE__RSV3__M = ^x1ffff	
                  [000000]  1360  
                  [000000]  1361  EV6__ASTRR_FPE = ^x54	
                  [000000]  1362  EV6__ASTRR_FPE__RSV0__S = ^x0	
                  [000000]  1363  EV6__ASTRR_FPE__RSV0__V = ^x1	
                  [000000]  1364  EV6__ASTRR_FPE__RSV0__M = ^x1	
                  [000000]  1365  EV6__ASTRR_FPE__PPCE__S = ^x1	
                  [000000]  1366  EV6__ASTRR_FPE__PPCE__V = ^x1	
                  [000000]  1367  EV6__ASTRR_FPE__PPCE__M = ^x1	
                  [000000]  1368  EV6__ASTRR_FPE__FPE__S = ^x2	
                  [000000]  1369  EV6__ASTRR_FPE__FPE__V = ^x1	
                  [000000]  1370  EV6__ASTRR_FPE__FPE__M = ^x1	
                  [000000]  1371  EV6__ASTRR_FPE__RSV1__S = ^x3	
                  [000000]  1372  EV6__ASTRR_FPE__RSV1__V = ^x2	
                  [000000]  1373  EV6__ASTRR_FPE__RSV1__M = ^x3	
                  [000000]  1374  EV6__ASTRR_FPE__ASTER__S = ^x5	
                  [000000]  1375  EV6__ASTRR_FPE__ASTER__V = ^x4	
                  [000000]  1376  EV6__ASTRR_FPE__ASTER__M = ^xf	
                  [000000]  1377  EV6__ASTRR_FPE__ASTRR__S = ^x9	
                  [000000]  1378  EV6__ASTRR_FPE__ASTRR__V = ^x4	
                  [000000]  1379  EV6__ASTRR_FPE__ASTRR__M = ^xf	
                  [000000]  1380  EV6__ASTRR_FPE__RSV2__S = ^xd	
                  [000000]  1381  EV6__ASTRR_FPE__RSV2__V = ^x1a	
                  [000000]  1382  EV6__ASTRR_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1383  EV6__ASTRR_FPE__ASN__S = ^x27	
                  [000000]  1384  EV6__ASTRR_FPE__ASN__V = ^x8	
                  [000000]  1385  EV6__ASTRR_FPE__ASN__M = ^xff	
                  [000000]  1386  EV6__ASTRR_FPE__RSV3__S = ^x2f	
                  [000000]  1387  EV6__ASTRR_FPE__RSV3__V = ^x11	
                  [000000]  1388  EV6__ASTRR_FPE__RSV3__M = ^x1ffff	
                  [000000]  1389  
                  [000000]  1390  EV6__PPCE_FPE = ^x58	
                  [000000]  1391  EV6__PPCE_FPE__RSV0__S = ^x0	
                  [000000]  1392  EV6__PPCE_FPE__RSV0__V = ^x1	
                  [000000]  1393  EV6__PPCE_FPE__RSV0__M = ^x1	
                  [000000]  1394  EV6__PPCE_FPE__PPCE__S = ^x1	
                  [000000]  1395  EV6__PPCE_FPE__PPCE__V = ^x1	
                  [000000]  1396  EV6__PPCE_FPE__PPCE__M = ^x1	
                  [000000]  1397  EV6__PPCE_FPE__FPE__S = ^x2	
                  [000000]  1398  EV6__PPCE_FPE__FPE__V = ^x1	
                  [000000]  1399  EV6__PPCE_FPE__FPE__M = ^x1	
                  [000000]  1400  EV6__PPCE_FPE__RSV1__S = ^x3	
                  [000000]  1401  EV6__PPCE_FPE__RSV1__V = ^x2	
                  [000000]  1402  EV6__PPCE_FPE__RSV1__M = ^x3	
                  [000000]  1403  EV6__PPCE_FPE__ASTER__S = ^x5	
                  [000000]  1404  EV6__PPCE_FPE__ASTER__V = ^x4	
                  [000000]  1405  EV6__PPCE_FPE__ASTER__M = ^xf	
                  [000000]  1406  EV6__PPCE_FPE__ASTRR__S = ^x9	
                  [000000]  1407  EV6__PPCE_FPE__ASTRR__V = ^x4	
                  [000000]  1408  EV6__PPCE_FPE__ASTRR__M = ^xf	
                  [000000]  1409  EV6__PPCE_FPE__RSV2__S = ^xd	
                  [000000]  1410  EV6__PPCE_FPE__RSV2__V = ^x1a	
                  [000000]  1411  EV6__PPCE_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1412  EV6__PPCE_FPE__ASN__S = ^x27	
                  [000000]  1413  EV6__PPCE_FPE__ASN__V = ^x8	
                  [000000]  1414  EV6__PPCE_FPE__ASN__M = ^xff	
                  [000000]  1415  EV6__PPCE_FPE__RSV3__S = ^x2f	
                  [000000]  1416  EV6__PPCE_FPE__RSV3__V = ^x11	
                  [000000]  1417  EV6__PPCE_FPE__RSV3__M = ^x1ffff	
                  [000000]  1418  
                  [000000]  1419  EV6__ASN_ASTER_ASTRR = ^x47	
                  [000000]  1420  EV6__ASN_ASTER_ASTRR__RSV0__S = ^x0	
                  [000000]  1421  EV6__ASN_ASTER_ASTRR__RSV0__V = ^x1	
                  [000000]  1422  EV6__ASN_ASTER_ASTRR__RSV0__M = ^x1	
                  [000000]  1423  EV6__ASN_ASTER_ASTRR__PPCE__S = ^x1	
                  [000000]  1424  EV6__ASN_ASTER_ASTRR__PPCE__V = ^x1	
                  [000000]  1425  EV6__ASN_ASTER_ASTRR__PPCE__M = ^x1	
                  [000000]  1426  EV6__ASN_ASTER_ASTRR__FPE__S = ^x2	
                  [000000]  1427  EV6__ASN_ASTER_ASTRR__FPE__V = ^x1	
                  [000000]  1428  EV6__ASN_ASTER_ASTRR__FPE__M = ^x1	
                  [000000]  1429  EV6__ASN_ASTER_ASTRR__RSV1__S = ^x3	
                  [000000]  1430  EV6__ASN_ASTER_ASTRR__RSV1__V = ^x2	
                  [000000]  1431  EV6__ASN_ASTER_ASTRR__RSV1__M = ^x3	
                  [000000]  1432  EV6__ASN_ASTER_ASTRR__ASTER__S = ^x5	
                  [000000]  1433  EV6__ASN_ASTER_ASTRR__ASTER__V = ^x4	
                  [000000]  1434  EV6__ASN_ASTER_ASTRR__ASTER__M = ^xf	
                  [000000]  1435  EV6__ASN_ASTER_ASTRR__ASTRR__S = ^x9	
                  [000000]  1436  EV6__ASN_ASTER_ASTRR__ASTRR__V = ^x4	
                  [000000]  1437  EV6__ASN_ASTER_ASTRR__ASTRR__M = ^xf	
                  [000000]  1438  EV6__ASN_ASTER_ASTRR__RSV2__S = ^xd	
                  [000000]  1439  EV6__ASN_ASTER_ASTRR__RSV2__V = ^x1a	
                  [000000]  1440  EV6__ASN_ASTER_ASTRR__RSV2__M = ^x3ffffff	
                  [000000]  1441  EV6__ASN_ASTER_ASTRR__ASN__S = ^x27	
                  [000000]  1442  EV6__ASN_ASTER_ASTRR__ASN__V = ^x8	
                  [000000]  1443  EV6__ASN_ASTER_ASTRR__ASN__M = ^xff	
                  [000000]  1444  EV6__ASN_ASTER_ASTRR__RSV3__S = ^x2f	
                  [000000]  1445  EV6__ASN_ASTER_ASTRR__RSV3__V = ^x11	
                  [000000]  1446  EV6__ASN_ASTER_ASTRR__RSV3__M = ^x1ffff	
                  [000000]  1447  
                  [000000]  1448  EV6__ASN_ASTER_PPCE = ^x4b	
                  [000000]  1449  EV6__ASN_ASTER_PPCE__RSV0__S = ^x0	
                  [000000]  1450  EV6__ASN_ASTER_PPCE__RSV0__V = ^x1	
                  [000000]  1451  EV6__ASN_ASTER_PPCE__RSV0__M = ^x1	
                  [000000]  1452  EV6__ASN_ASTER_PPCE__PPCE__S = ^x1	
                  [000000]  1453  EV6__ASN_ASTER_PPCE__PPCE__V = ^x1	
                  [000000]  1454  EV6__ASN_ASTER_PPCE__PPCE__M = ^x1	
                  [000000]  1455  EV6__ASN_ASTER_PPCE__FPE__S = ^x2	
                  [000000]  1456  EV6__ASN_ASTER_PPCE__FPE__V = ^x1	
                  [000000]  1457  EV6__ASN_ASTER_PPCE__FPE__M = ^x1	
                  [000000]  1458  EV6__ASN_ASTER_PPCE__RSV1__S = ^x3	
                  [000000]  1459  EV6__ASN_ASTER_PPCE__RSV1__V = ^x2	
                  [000000]  1460  EV6__ASN_ASTER_PPCE__RSV1__M = ^x3	
                  [000000]  1461  EV6__ASN_ASTER_PPCE__ASTER__S = ^x5	
                  [000000]  1462  EV6__ASN_ASTER_PPCE__ASTER__V = ^x4	
                  [000000]  1463  EV6__ASN_ASTER_PPCE__ASTER__M = ^xf	
                  [000000]  1464  EV6__ASN_ASTER_PPCE__ASTRR__S = ^x9	
                  [000000]  1465  EV6__ASN_ASTER_PPCE__ASTRR__V = ^x4	
                  [000000]  1466  EV6__ASN_ASTER_PPCE__ASTRR__M = ^xf	
                  [000000]  1467  EV6__ASN_ASTER_PPCE__RSV2__S = ^xd	
                  [000000]  1468  EV6__ASN_ASTER_PPCE__RSV2__V = ^x1a	
                  [000000]  1469  EV6__ASN_ASTER_PPCE__RSV2__M = ^x3ffffff	
                  [000000]  1470  EV6__ASN_ASTER_PPCE__ASN__S = ^x27	
                  [000000]  1471  EV6__ASN_ASTER_PPCE__ASN__V = ^x8	
                  [000000]  1472  EV6__ASN_ASTER_PPCE__ASN__M = ^xff	
                  [000000]  1473  EV6__ASN_ASTER_PPCE__RSV3__S = ^x2f	
                  [000000]  1474  EV6__ASN_ASTER_PPCE__RSV3__V = ^x11	
                  [000000]  1475  EV6__ASN_ASTER_PPCE__RSV3__M = ^x1ffff	
                  [000000]  1476  
                  [000000]  1477  EV6__ASN_ASTER_FPE = ^x53	
                  [000000]  1478  EV6__ASN_ASTER_FPE__RSV0__S = ^x0	
                  [000000]  1479  EV6__ASN_ASTER_FPE__RSV0__V = ^x1	
                  [000000]  1480  EV6__ASN_ASTER_FPE__RSV0__M = ^x1	
                  [000000]  1481  EV6__ASN_ASTER_FPE__PPCE__S = ^x1	
                  [000000]  1482  EV6__ASN_ASTER_FPE__PPCE__V = ^x1	
                  [000000]  1483  EV6__ASN_ASTER_FPE__PPCE__M = ^x1	
                  [000000]  1484  EV6__ASN_ASTER_FPE__FPE__S = ^x2	
                  [000000]  1485  EV6__ASN_ASTER_FPE__FPE__V = ^x1	
                  [000000]  1486  EV6__ASN_ASTER_FPE__FPE__M = ^x1	
                  [000000]  1487  EV6__ASN_ASTER_FPE__RSV1__S = ^x3	
                  [000000]  1488  EV6__ASN_ASTER_FPE__RSV1__V = ^x2	
                  [000000]  1489  EV6__ASN_ASTER_FPE__RSV1__M = ^x3	
                  [000000]  1490  EV6__ASN_ASTER_FPE__ASTER__S = ^x5	
                  [000000]  1491  EV6__ASN_ASTER_FPE__ASTER__V = ^x4	
                  [000000]  1492  EV6__ASN_ASTER_FPE__ASTER__M = ^xf	
                  [000000]  1493  EV6__ASN_ASTER_FPE__ASTRR__S = ^x9	
                  [000000]  1494  EV6__ASN_ASTER_FPE__ASTRR__V = ^x4	
                  [000000]  1495  EV6__ASN_ASTER_FPE__ASTRR__M = ^xf	
                  [000000]  1496  EV6__ASN_ASTER_FPE__RSV2__S = ^xd	
                  [000000]  1497  EV6__ASN_ASTER_FPE__RSV2__V = ^x1a	
                  [000000]  1498  EV6__ASN_ASTER_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1499  EV6__ASN_ASTER_FPE__ASN__S = ^x27	
                  [000000]  1500  EV6__ASN_ASTER_FPE__ASN__V = ^x8	
                  [000000]  1501  EV6__ASN_ASTER_FPE__ASN__M = ^xff	
                  [000000]  1502  EV6__ASN_ASTER_FPE__RSV3__S = ^x2f	
                  [000000]  1503  EV6__ASN_ASTER_FPE__RSV3__V = ^x11	
                  [000000]  1504  EV6__ASN_ASTER_FPE__RSV3__M = ^x1ffff	
                  [000000]  1505  
                  [000000]  1506  EV6__ASN_ASTRR_PPCE = ^x4d	
                  [000000]  1507  EV6__ASN_ASTRR_PPCE__RSV0__S = ^x0	
                  [000000]  1508  EV6__ASN_ASTRR_PPCE__RSV0__V = ^x1	
                  [000000]  1509  EV6__ASN_ASTRR_PPCE__RSV0__M = ^x1	
                  [000000]  1510  EV6__ASN_ASTRR_PPCE__PPCE__S = ^x1	
                  [000000]  1511  EV6__ASN_ASTRR_PPCE__PPCE__V = ^x1	
                  [000000]  1512  EV6__ASN_ASTRR_PPCE__PPCE__M = ^x1	
                  [000000]  1513  EV6__ASN_ASTRR_PPCE__FPE__S = ^x2	
                  [000000]  1514  EV6__ASN_ASTRR_PPCE__FPE__V = ^x1	
                  [000000]  1515  EV6__ASN_ASTRR_PPCE__FPE__M = ^x1	
                  [000000]  1516  EV6__ASN_ASTRR_PPCE__RSV1__S = ^x3	
                  [000000]  1517  EV6__ASN_ASTRR_PPCE__RSV1__V = ^x2	
                  [000000]  1518  EV6__ASN_ASTRR_PPCE__RSV1__M = ^x3	
                  [000000]  1519  EV6__ASN_ASTRR_PPCE__ASTER__S = ^x5	
                  [000000]  1520  EV6__ASN_ASTRR_PPCE__ASTER__V = ^x4	
                  [000000]  1521  EV6__ASN_ASTRR_PPCE__ASTER__M = ^xf	
                  [000000]  1522  EV6__ASN_ASTRR_PPCE__ASTRR__S = ^x9	
                  [000000]  1523  EV6__ASN_ASTRR_PPCE__ASTRR__V = ^x4	
                  [000000]  1524  EV6__ASN_ASTRR_PPCE__ASTRR__M = ^xf	
                  [000000]  1525  EV6__ASN_ASTRR_PPCE__RSV2__S = ^xd	
                  [000000]  1526  EV6__ASN_ASTRR_PPCE__RSV2__V = ^x1a	
                  [000000]  1527  EV6__ASN_ASTRR_PPCE__RSV2__M = ^x3ffffff	
                  [000000]  1528  EV6__ASN_ASTRR_PPCE__ASN__S = ^x27	
                  [000000]  1529  EV6__ASN_ASTRR_PPCE__ASN__V = ^x8	
                  [000000]  1530  EV6__ASN_ASTRR_PPCE__ASN__M = ^xff	
                  [000000]  1531  EV6__ASN_ASTRR_PPCE__RSV3__S = ^x2f	
                  [000000]  1532  EV6__ASN_ASTRR_PPCE__RSV3__V = ^x11	
                  [000000]  1533  EV6__ASN_ASTRR_PPCE__RSV3__M = ^x1ffff	
                  [000000]  1534  
                  [000000]  1535  EV6__ASN_ASTRR_FPE = ^x55	
                  [000000]  1536  EV6__ASN_ASTRR_FPE__RSV0__S = ^x0	
                  [000000]  1537  EV6__ASN_ASTRR_FPE__RSV0__V = ^x1	
                  [000000]  1538  EV6__ASN_ASTRR_FPE__RSV0__M = ^x1	
                  [000000]  1539  EV6__ASN_ASTRR_FPE__PPCE__S = ^x1	
                  [000000]  1540  EV6__ASN_ASTRR_FPE__PPCE__V = ^x1	
                  [000000]  1541  EV6__ASN_ASTRR_FPE__PPCE__M = ^x1	
                  [000000]  1542  EV6__ASN_ASTRR_FPE__FPE__S = ^x2	
                  [000000]  1543  EV6__ASN_ASTRR_FPE__FPE__V = ^x1	
                  [000000]  1544  EV6__ASN_ASTRR_FPE__FPE__M = ^x1	
                  [000000]  1545  EV6__ASN_ASTRR_FPE__RSV1__S = ^x3	
                  [000000]  1546  EV6__ASN_ASTRR_FPE__RSV1__V = ^x2	
                  [000000]  1547  EV6__ASN_ASTRR_FPE__RSV1__M = ^x3	
                  [000000]  1548  EV6__ASN_ASTRR_FPE__ASTER__S = ^x5	
                  [000000]  1549  EV6__ASN_ASTRR_FPE__ASTER__V = ^x4	
                  [000000]  1550  EV6__ASN_ASTRR_FPE__ASTER__M = ^xf	
                  [000000]  1551  EV6__ASN_ASTRR_FPE__ASTRR__S = ^x9	
                  [000000]  1552  EV6__ASN_ASTRR_FPE__ASTRR__V = ^x4	
                  [000000]  1553  EV6__ASN_ASTRR_FPE__ASTRR__M = ^xf	
                  [000000]  1554  EV6__ASN_ASTRR_FPE__RSV2__S = ^xd	
                  [000000]  1555  EV6__ASN_ASTRR_FPE__RSV2__V = ^x1a	
                  [000000]  1556  EV6__ASN_ASTRR_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1557  EV6__ASN_ASTRR_FPE__ASN__S = ^x27	
                  [000000]  1558  EV6__ASN_ASTRR_FPE__ASN__V = ^x8	
                  [000000]  1559  EV6__ASN_ASTRR_FPE__ASN__M = ^xff	
                  [000000]  1560  EV6__ASN_ASTRR_FPE__RSV3__S = ^x2f	
                  [000000]  1561  EV6__ASN_ASTRR_FPE__RSV3__V = ^x11	
                  [000000]  1562  EV6__ASN_ASTRR_FPE__RSV3__M = ^x1ffff	
                  [000000]  1563  
                  [000000]  1564  EV6__ASN_PPCE_FPE = ^x59	
                  [000000]  1565  EV6__ASN_PPCE_FPE__RSV0__S = ^x0	
                  [000000]  1566  EV6__ASN_PPCE_FPE__RSV0__V = ^x1	
                  [000000]  1567  EV6__ASN_PPCE_FPE__RSV0__M = ^x1	
                  [000000]  1568  EV6__ASN_PPCE_FPE__PPCE__S = ^x1	
                  [000000]  1569  EV6__ASN_PPCE_FPE__PPCE__V = ^x1	
                  [000000]  1570  EV6__ASN_PPCE_FPE__PPCE__M = ^x1	
                  [000000]  1571  EV6__ASN_PPCE_FPE__FPE__S = ^x2	
                  [000000]  1572  EV6__ASN_PPCE_FPE__FPE__V = ^x1	
                  [000000]  1573  EV6__ASN_PPCE_FPE__FPE__M = ^x1	
                  [000000]  1574  EV6__ASN_PPCE_FPE__RSV1__S = ^x3	
                  [000000]  1575  EV6__ASN_PPCE_FPE__RSV1__V = ^x2	
                  [000000]  1576  EV6__ASN_PPCE_FPE__RSV1__M = ^x3	
                  [000000]  1577  EV6__ASN_PPCE_FPE__ASTER__S = ^x5	
                  [000000]  1578  EV6__ASN_PPCE_FPE__ASTER__V = ^x4	
                  [000000]  1579  EV6__ASN_PPCE_FPE__ASTER__M = ^xf	
                  [000000]  1580  EV6__ASN_PPCE_FPE__ASTRR__S = ^x9	
                  [000000]  1581  EV6__ASN_PPCE_FPE__ASTRR__V = ^x4	
                  [000000]  1582  EV6__ASN_PPCE_FPE__ASTRR__M = ^xf	
                  [000000]  1583  EV6__ASN_PPCE_FPE__RSV2__S = ^xd	
                  [000000]  1584  EV6__ASN_PPCE_FPE__RSV2__V = ^x1a	
                  [000000]  1585  EV6__ASN_PPCE_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1586  EV6__ASN_PPCE_FPE__ASN__S = ^x27	
                  [000000]  1587  EV6__ASN_PPCE_FPE__ASN__V = ^x8	
                  [000000]  1588  EV6__ASN_PPCE_FPE__ASN__M = ^xff	
                  [000000]  1589  EV6__ASN_PPCE_FPE__RSV3__S = ^x2f	
                  [000000]  1590  EV6__ASN_PPCE_FPE__RSV3__V = ^x11	
                  [000000]  1591  EV6__ASN_PPCE_FPE__RSV3__M = ^x1ffff	
                  [000000]  1592  
                  [000000]  1593  EV6__ASTER_ASTRR_PPCE = ^x4e	
                  [000000]  1594  EV6__ASTER_ASTRR_PPCE__RSV0__S = ^x0	
                  [000000]  1595  EV6__ASTER_ASTRR_PPCE__RSV0__V = ^x1	
                  [000000]  1596  EV6__ASTER_ASTRR_PPCE__RSV0__M = ^x1	
                  [000000]  1597  EV6__ASTER_ASTRR_PPCE__PPCE__S = ^x1	
                  [000000]  1598  EV6__ASTER_ASTRR_PPCE__PPCE__V = ^x1	
                  [000000]  1599  EV6__ASTER_ASTRR_PPCE__PPCE__M = ^x1	
                  [000000]  1600  EV6__ASTER_ASTRR_PPCE__FPE__S = ^x2	
                  [000000]  1601  EV6__ASTER_ASTRR_PPCE__FPE__V = ^x1	
                  [000000]  1602  EV6__ASTER_ASTRR_PPCE__FPE__M = ^x1	
                  [000000]  1603  EV6__ASTER_ASTRR_PPCE__RSV1__S = ^x3	
                  [000000]  1604  EV6__ASTER_ASTRR_PPCE__RSV1__V = ^x2	
                  [000000]  1605  EV6__ASTER_ASTRR_PPCE__RSV1__M = ^x3	
                  [000000]  1606  EV6__ASTER_ASTRR_PPCE__ASTER__S = ^x5	
                  [000000]  1607  EV6__ASTER_ASTRR_PPCE__ASTER__V = ^x4	
                  [000000]  1608  EV6__ASTER_ASTRR_PPCE__ASTER__M = ^xf	
                  [000000]  1609  EV6__ASTER_ASTRR_PPCE__ASTRR__S = ^x9	
                  [000000]  1610  EV6__ASTER_ASTRR_PPCE__ASTRR__V = ^x4	
                  [000000]  1611  EV6__ASTER_ASTRR_PPCE__ASTRR__M = ^xf	
                  [000000]  1612  EV6__ASTER_ASTRR_PPCE__RSV2__S = ^xd	
                  [000000]  1613  EV6__ASTER_ASTRR_PPCE__RSV2__V = ^x1a	
                  [000000]  1614  EV6__ASTER_ASTRR_PPCE__RSV2__M = ^x3ffffff	
                  [000000]  1615  EV6__ASTER_ASTRR_PPCE__ASN__S = ^x27	
                  [000000]  1616  EV6__ASTER_ASTRR_PPCE__ASN__V = ^x8	
                  [000000]  1617  EV6__ASTER_ASTRR_PPCE__ASN__M = ^xff	
                  [000000]  1618  EV6__ASTER_ASTRR_PPCE__RSV3__S = ^x2f	
                  [000000]  1619  EV6__ASTER_ASTRR_PPCE__RSV3__V = ^x11	
                  [000000]  1620  EV6__ASTER_ASTRR_PPCE__RSV3__M = ^x1ffff	
                  [000000]  1621  
                  [000000]  1622  EV6__ASTER_ASTRR_FPE = ^x56	
                  [000000]  1623  EV6__ASTER_ASTRR_FPE__RSV0__S = ^x0	
                  [000000]  1624  EV6__ASTER_ASTRR_FPE__RSV0__V = ^x1	
                  [000000]  1625  EV6__ASTER_ASTRR_FPE__RSV0__M = ^x1	
                  [000000]  1626  EV6__ASTER_ASTRR_FPE__PPCE__S = ^x1	
                  [000000]  1627  EV6__ASTER_ASTRR_FPE__PPCE__V = ^x1	
                  [000000]  1628  EV6__ASTER_ASTRR_FPE__PPCE__M = ^x1	
                  [000000]  1629  EV6__ASTER_ASTRR_FPE__FPE__S = ^x2	
                  [000000]  1630  EV6__ASTER_ASTRR_FPE__FPE__V = ^x1	
                  [000000]  1631  EV6__ASTER_ASTRR_FPE__FPE__M = ^x1	
                  [000000]  1632  EV6__ASTER_ASTRR_FPE__RSV1__S = ^x3	
                  [000000]  1633  EV6__ASTER_ASTRR_FPE__RSV1__V = ^x2	
                  [000000]  1634  EV6__ASTER_ASTRR_FPE__RSV1__M = ^x3	
                  [000000]  1635  EV6__ASTER_ASTRR_FPE__ASTER__S = ^x5	
                  [000000]  1636  EV6__ASTER_ASTRR_FPE__ASTER__V = ^x4	
                  [000000]  1637  EV6__ASTER_ASTRR_FPE__ASTER__M = ^xf	
                  [000000]  1638  EV6__ASTER_ASTRR_FPE__ASTRR__S = ^x9	
                  [000000]  1639  EV6__ASTER_ASTRR_FPE__ASTRR__V = ^x4	
                  [000000]  1640  EV6__ASTER_ASTRR_FPE__ASTRR__M = ^xf	
                  [000000]  1641  EV6__ASTER_ASTRR_FPE__RSV2__S = ^xd	
                  [000000]  1642  EV6__ASTER_ASTRR_FPE__RSV2__V = ^x1a	
                  [000000]  1643  EV6__ASTER_ASTRR_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1644  EV6__ASTER_ASTRR_FPE__ASN__S = ^x27	
                  [000000]  1645  EV6__ASTER_ASTRR_FPE__ASN__V = ^x8	
                  [000000]  1646  EV6__ASTER_ASTRR_FPE__ASN__M = ^xff	
                  [000000]  1647  EV6__ASTER_ASTRR_FPE__RSV3__S = ^x2f	
                  [000000]  1648  EV6__ASTER_ASTRR_FPE__RSV3__V = ^x11	
                  [000000]  1649  EV6__ASTER_ASTRR_FPE__RSV3__M = ^x1ffff	
                  [000000]  1650  
                  [000000]  1651  EV6__ASTER_PPCE_FPE = ^x5a	
                  [000000]  1652  EV6__ASTER_PPCE_FPE__RSV0__S = ^x0	
                  [000000]  1653  EV6__ASTER_PPCE_FPE__RSV0__V = ^x1	
                  [000000]  1654  EV6__ASTER_PPCE_FPE__RSV0__M = ^x1	
                  [000000]  1655  EV6__ASTER_PPCE_FPE__PPCE__S = ^x1	
                  [000000]  1656  EV6__ASTER_PPCE_FPE__PPCE__V = ^x1	
                  [000000]  1657  EV6__ASTER_PPCE_FPE__PPCE__M = ^x1	
                  [000000]  1658  EV6__ASTER_PPCE_FPE__FPE__S = ^x2	
                  [000000]  1659  EV6__ASTER_PPCE_FPE__FPE__V = ^x1	
                  [000000]  1660  EV6__ASTER_PPCE_FPE__FPE__M = ^x1	
                  [000000]  1661  EV6__ASTER_PPCE_FPE__RSV1__S = ^x3	
                  [000000]  1662  EV6__ASTER_PPCE_FPE__RSV1__V = ^x2	
                  [000000]  1663  EV6__ASTER_PPCE_FPE__RSV1__M = ^x3	
                  [000000]  1664  EV6__ASTER_PPCE_FPE__ASTER__S = ^x5	
                  [000000]  1665  EV6__ASTER_PPCE_FPE__ASTER__V = ^x4	
                  [000000]  1666  EV6__ASTER_PPCE_FPE__ASTER__M = ^xf	
                  [000000]  1667  EV6__ASTER_PPCE_FPE__ASTRR__S = ^x9	
                  [000000]  1668  EV6__ASTER_PPCE_FPE__ASTRR__V = ^x4	
                  [000000]  1669  EV6__ASTER_PPCE_FPE__ASTRR__M = ^xf	
                  [000000]  1670  EV6__ASTER_PPCE_FPE__RSV2__S = ^xd	
                  [000000]  1671  EV6__ASTER_PPCE_FPE__RSV2__V = ^x1a	
                  [000000]  1672  EV6__ASTER_PPCE_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1673  EV6__ASTER_PPCE_FPE__ASN__S = ^x27	
                  [000000]  1674  EV6__ASTER_PPCE_FPE__ASN__V = ^x8	
                  [000000]  1675  EV6__ASTER_PPCE_FPE__ASN__M = ^xff	
                  [000000]  1676  EV6__ASTER_PPCE_FPE__RSV3__S = ^x2f	
                  [000000]  1677  EV6__ASTER_PPCE_FPE__RSV3__V = ^x11	
                  [000000]  1678  EV6__ASTER_PPCE_FPE__RSV3__M = ^x1ffff	
                  [000000]  1679  
                  [000000]  1680  EV6__ASTRR_PPCE_FPE = ^x5c	
                  [000000]  1681  EV6__ASTRR_PPCE_FPE__RSV0__S = ^x0	
                  [000000]  1682  EV6__ASTRR_PPCE_FPE__RSV0__V = ^x1	
                  [000000]  1683  EV6__ASTRR_PPCE_FPE__RSV0__M = ^x1	
                  [000000]  1684  EV6__ASTRR_PPCE_FPE__PPCE__S = ^x1	
                  [000000]  1685  EV6__ASTRR_PPCE_FPE__PPCE__V = ^x1	
                  [000000]  1686  EV6__ASTRR_PPCE_FPE__PPCE__M = ^x1	
                  [000000]  1687  EV6__ASTRR_PPCE_FPE__FPE__S = ^x2	
                  [000000]  1688  EV6__ASTRR_PPCE_FPE__FPE__V = ^x1	
                  [000000]  1689  EV6__ASTRR_PPCE_FPE__FPE__M = ^x1	
                  [000000]  1690  EV6__ASTRR_PPCE_FPE__RSV1__S = ^x3	
                  [000000]  1691  EV6__ASTRR_PPCE_FPE__RSV1__V = ^x2	
                  [000000]  1692  EV6__ASTRR_PPCE_FPE__RSV1__M = ^x3	
                  [000000]  1693  EV6__ASTRR_PPCE_FPE__ASTER__S = ^x5	
                  [000000]  1694  EV6__ASTRR_PPCE_FPE__ASTER__V = ^x4	
                  [000000]  1695  EV6__ASTRR_PPCE_FPE__ASTER__M = ^xf	
                  [000000]  1696  EV6__ASTRR_PPCE_FPE__ASTRR__S = ^x9	
                  [000000]  1697  EV6__ASTRR_PPCE_FPE__ASTRR__V = ^x4	
                  [000000]  1698  EV6__ASTRR_PPCE_FPE__ASTRR__M = ^xf	
                  [000000]  1699  EV6__ASTRR_PPCE_FPE__RSV2__S = ^xd	
                  [000000]  1700  EV6__ASTRR_PPCE_FPE__RSV2__V = ^x1a	
                  [000000]  1701  EV6__ASTRR_PPCE_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1702  EV6__ASTRR_PPCE_FPE__ASN__S = ^x27	
                  [000000]  1703  EV6__ASTRR_PPCE_FPE__ASN__V = ^x8	
                  [000000]  1704  EV6__ASTRR_PPCE_FPE__ASN__M = ^xff	
                  [000000]  1705  EV6__ASTRR_PPCE_FPE__RSV3__S = ^x2f	
                  [000000]  1706  EV6__ASTRR_PPCE_FPE__RSV3__V = ^x11	
                  [000000]  1707  EV6__ASTRR_PPCE_FPE__RSV3__M = ^x1ffff	
                  [000000]  1708  
                  [000000]  1709  EV6__ASN_ASTER_ASTRR_PPCE = ^x4f	
                  [000000]  1710  EV6__ASN_ASTER_ASTRR_PPCE__RSV0__S = ^x0	
                  [000000]  1711  EV6__ASN_ASTER_ASTRR_PPCE__RSV0__V = ^x1	
                  [000000]  1712  EV6__ASN_ASTER_ASTRR_PPCE__RSV0__M = ^x1	
                  [000000]  1713  EV6__ASN_ASTER_ASTRR_PPCE__PPCE__S = ^x1	
                  [000000]  1714  EV6__ASN_ASTER_ASTRR_PPCE__PPCE__V = ^x1	
                  [000000]  1715  EV6__ASN_ASTER_ASTRR_PPCE__PPCE__M = ^x1	
                  [000000]  1716  EV6__ASN_ASTER_ASTRR_PPCE__FPE__S = ^x2	
                  [000000]  1717  EV6__ASN_ASTER_ASTRR_PPCE__FPE__V = ^x1	
                  [000000]  1718  EV6__ASN_ASTER_ASTRR_PPCE__FPE__M = ^x1	
                  [000000]  1719  EV6__ASN_ASTER_ASTRR_PPCE__RSV1__S = ^x3	
                  [000000]  1720  EV6__ASN_ASTER_ASTRR_PPCE__RSV1__V = ^x2	
                  [000000]  1721  EV6__ASN_ASTER_ASTRR_PPCE__RSV1__M = ^x3	
                  [000000]  1722  EV6__ASN_ASTER_ASTRR_PPCE__ASTER__S = ^x5	
                  [000000]  1723  EV6__ASN_ASTER_ASTRR_PPCE__ASTER__V = ^x4	
                  [000000]  1724  EV6__ASN_ASTER_ASTRR_PPCE__ASTER__M = ^xf	
                  [000000]  1725  EV6__ASN_ASTER_ASTRR_PPCE__ASTRR__S = ^x9	
                  [000000]  1726  EV6__ASN_ASTER_ASTRR_PPCE__ASTRR__V = ^x4	
                  [000000]  1727  EV6__ASN_ASTER_ASTRR_PPCE__ASTRR__M = ^xf	
                  [000000]  1728  EV6__ASN_ASTER_ASTRR_PPCE__RSV2__S = ^xd	
                  [000000]  1729  EV6__ASN_ASTER_ASTRR_PPCE__RSV2__V = ^x1a	
                  [000000]  1730  EV6__ASN_ASTER_ASTRR_PPCE__RSV2__M = ^x3ffffff	
                  [000000]  1731  EV6__ASN_ASTER_ASTRR_PPCE__ASN__S = ^x27	
                  [000000]  1732  EV6__ASN_ASTER_ASTRR_PPCE__ASN__V = ^x8	
                  [000000]  1733  EV6__ASN_ASTER_ASTRR_PPCE__ASN__M = ^xff	
                  [000000]  1734  EV6__ASN_ASTER_ASTRR_PPCE__RSV3__S = ^x2f	
                  [000000]  1735  EV6__ASN_ASTER_ASTRR_PPCE__RSV3__V = ^x11	
                  [000000]  1736  EV6__ASN_ASTER_ASTRR_PPCE__RSV3__M = ^x1ffff	
                  [000000]  1737  
                  [000000]  1738  EV6__ASN_ASTER_ASTRR_FPE = ^x57	
                  [000000]  1739  EV6__ASN_ASTER_ASTRR_FPE__RSV0__S = ^x0	
                  [000000]  1740  EV6__ASN_ASTER_ASTRR_FPE__RSV0__V = ^x1	
                  [000000]  1741  EV6__ASN_ASTER_ASTRR_FPE__RSV0__M = ^x1	
                  [000000]  1742  EV6__ASN_ASTER_ASTRR_FPE__PPCE__S = ^x1	
                  [000000]  1743  EV6__ASN_ASTER_ASTRR_FPE__PPCE__V = ^x1	
                  [000000]  1744  EV6__ASN_ASTER_ASTRR_FPE__PPCE__M = ^x1	
                  [000000]  1745  EV6__ASN_ASTER_ASTRR_FPE__FPE__S = ^x2	
                  [000000]  1746  EV6__ASN_ASTER_ASTRR_FPE__FPE__V = ^x1	
                  [000000]  1747  EV6__ASN_ASTER_ASTRR_FPE__FPE__M = ^x1	
                  [000000]  1748  EV6__ASN_ASTER_ASTRR_FPE__RSV1__S = ^x3	
                  [000000]  1749  EV6__ASN_ASTER_ASTRR_FPE__RSV1__V = ^x2	
                  [000000]  1750  EV6__ASN_ASTER_ASTRR_FPE__RSV1__M = ^x3	
                  [000000]  1751  EV6__ASN_ASTER_ASTRR_FPE__ASTER__S = ^x5	
                  [000000]  1752  EV6__ASN_ASTER_ASTRR_FPE__ASTER__V = ^x4	
                  [000000]  1753  EV6__ASN_ASTER_ASTRR_FPE__ASTER__M = ^xf	
                  [000000]  1754  EV6__ASN_ASTER_ASTRR_FPE__ASTRR__S = ^x9	
                  [000000]  1755  EV6__ASN_ASTER_ASTRR_FPE__ASTRR__V = ^x4	
                  [000000]  1756  EV6__ASN_ASTER_ASTRR_FPE__ASTRR__M = ^xf	
                  [000000]  1757  EV6__ASN_ASTER_ASTRR_FPE__RSV2__S = ^xd	
                  [000000]  1758  EV6__ASN_ASTER_ASTRR_FPE__RSV2__V = ^x1a	
                  [000000]  1759  EV6__ASN_ASTER_ASTRR_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1760  EV6__ASN_ASTER_ASTRR_FPE__ASN__S = ^x27	
                  [000000]  1761  EV6__ASN_ASTER_ASTRR_FPE__ASN__V = ^x8	
                  [000000]  1762  EV6__ASN_ASTER_ASTRR_FPE__ASN__M = ^xff	
                  [000000]  1763  EV6__ASN_ASTER_ASTRR_FPE__RSV3__S = ^x2f	
                  [000000]  1764  EV6__ASN_ASTER_ASTRR_FPE__RSV3__V = ^x11	
                  [000000]  1765  EV6__ASN_ASTER_ASTRR_FPE__RSV3__M = ^x1ffff	
                  [000000]  1766  
                  [000000]  1767  EV6__ASN_ASTER_PPCE_FPE = ^x5b	
                  [000000]  1768  EV6__ASN_ASTER_PPCE_FPE__RSV0__S = ^x0	
                  [000000]  1769  EV6__ASN_ASTER_PPCE_FPE__RSV0__V = ^x1	
                  [000000]  1770  EV6__ASN_ASTER_PPCE_FPE__RSV0__M = ^x1	
                  [000000]  1771  EV6__ASN_ASTER_PPCE_FPE__PPCE__S = ^x1	
                  [000000]  1772  EV6__ASN_ASTER_PPCE_FPE__PPCE__V = ^x1	
                  [000000]  1773  EV6__ASN_ASTER_PPCE_FPE__PPCE__M = ^x1	
                  [000000]  1774  EV6__ASN_ASTER_PPCE_FPE__FPE__S = ^x2	
                  [000000]  1775  EV6__ASN_ASTER_PPCE_FPE__FPE__V = ^x1	
                  [000000]  1776  EV6__ASN_ASTER_PPCE_FPE__FPE__M = ^x1	
                  [000000]  1777  EV6__ASN_ASTER_PPCE_FPE__RSV1__S = ^x3	
                  [000000]  1778  EV6__ASN_ASTER_PPCE_FPE__RSV1__V = ^x2	
                  [000000]  1779  EV6__ASN_ASTER_PPCE_FPE__RSV1__M = ^x3	
                  [000000]  1780  EV6__ASN_ASTER_PPCE_FPE__ASTER__S = ^x5	
                  [000000]  1781  EV6__ASN_ASTER_PPCE_FPE__ASTER__V = ^x4	
                  [000000]  1782  EV6__ASN_ASTER_PPCE_FPE__ASTER__M = ^xf	
                  [000000]  1783  EV6__ASN_ASTER_PPCE_FPE__ASTRR__S = ^x9	
                  [000000]  1784  EV6__ASN_ASTER_PPCE_FPE__ASTRR__V = ^x4	
                  [000000]  1785  EV6__ASN_ASTER_PPCE_FPE__ASTRR__M = ^xf	
                  [000000]  1786  EV6__ASN_ASTER_PPCE_FPE__RSV2__S = ^xd	
                  [000000]  1787  EV6__ASN_ASTER_PPCE_FPE__RSV2__V = ^x1a	
                  [000000]  1788  EV6__ASN_ASTER_PPCE_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1789  EV6__ASN_ASTER_PPCE_FPE__ASN__S = ^x27	
                  [000000]  1790  EV6__ASN_ASTER_PPCE_FPE__ASN__V = ^x8	
                  [000000]  1791  EV6__ASN_ASTER_PPCE_FPE__ASN__M = ^xff	
                  [000000]  1792  EV6__ASN_ASTER_PPCE_FPE__RSV3__S = ^x2f	
                  [000000]  1793  EV6__ASN_ASTER_PPCE_FPE__RSV3__V = ^x11	
                  [000000]  1794  EV6__ASN_ASTER_PPCE_FPE__RSV3__M = ^x1ffff	
                  [000000]  1795  
                  [000000]  1796  EV6__ASN_ASTRR_PPCE_FPE = ^x5d	
                  [000000]  1797  EV6__ASN_ASTRR_PPCE_FPE__RSV0__S = ^x0	
                  [000000]  1798  EV6__ASN_ASTRR_PPCE_FPE__RSV0__V = ^x1	
                  [000000]  1799  EV6__ASN_ASTRR_PPCE_FPE__RSV0__M = ^x1	
                  [000000]  1800  EV6__ASN_ASTRR_PPCE_FPE__PPCE__S = ^x1	
                  [000000]  1801  EV6__ASN_ASTRR_PPCE_FPE__PPCE__V = ^x1	
                  [000000]  1802  EV6__ASN_ASTRR_PPCE_FPE__PPCE__M = ^x1	
                  [000000]  1803  EV6__ASN_ASTRR_PPCE_FPE__FPE__S = ^x2	
                  [000000]  1804  EV6__ASN_ASTRR_PPCE_FPE__FPE__V = ^x1	
                  [000000]  1805  EV6__ASN_ASTRR_PPCE_FPE__FPE__M = ^x1	
                  [000000]  1806  EV6__ASN_ASTRR_PPCE_FPE__RSV1__S = ^x3	
                  [000000]  1807  EV6__ASN_ASTRR_PPCE_FPE__RSV1__V = ^x2	
                  [000000]  1808  EV6__ASN_ASTRR_PPCE_FPE__RSV1__M = ^x3	
                  [000000]  1809  EV6__ASN_ASTRR_PPCE_FPE__ASTER__S = ^x5	
                  [000000]  1810  EV6__ASN_ASTRR_PPCE_FPE__ASTER__V = ^x4	
                  [000000]  1811  EV6__ASN_ASTRR_PPCE_FPE__ASTER__M = ^xf	
                  [000000]  1812  EV6__ASN_ASTRR_PPCE_FPE__ASTRR__S = ^x9	
                  [000000]  1813  EV6__ASN_ASTRR_PPCE_FPE__ASTRR__V = ^x4	
                  [000000]  1814  EV6__ASN_ASTRR_PPCE_FPE__ASTRR__M = ^xf	
                  [000000]  1815  EV6__ASN_ASTRR_PPCE_FPE__RSV2__S = ^xd	
                  [000000]  1816  EV6__ASN_ASTRR_PPCE_FPE__RSV2__V = ^x1a	
                  [000000]  1817  EV6__ASN_ASTRR_PPCE_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1818  EV6__ASN_ASTRR_PPCE_FPE__ASN__S = ^x27	
                  [000000]  1819  EV6__ASN_ASTRR_PPCE_FPE__ASN__V = ^x8	
                  [000000]  1820  EV6__ASN_ASTRR_PPCE_FPE__ASN__M = ^xff	
                  [000000]  1821  EV6__ASN_ASTRR_PPCE_FPE__RSV3__S = ^x2f	
                  [000000]  1822  EV6__ASN_ASTRR_PPCE_FPE__RSV3__V = ^x11	
                  [000000]  1823  EV6__ASN_ASTRR_PPCE_FPE__RSV3__M = ^x1ffff	
                  [000000]  1824  
                  [000000]  1825  EV6__ASTER_ASTRR_PPCE_FPE = ^x5e	
                  [000000]  1826  EV6__ASTER_ASTRR_PPCE_FPE__RSV0__S = ^x0	
                  [000000]  1827  EV6__ASTER_ASTRR_PPCE_FPE__RSV0__V = ^x1	
                  [000000]  1828  EV6__ASTER_ASTRR_PPCE_FPE__RSV0__M = ^x1	
                  [000000]  1829  EV6__ASTER_ASTRR_PPCE_FPE__PPCE__S = ^x1	
                  [000000]  1830  EV6__ASTER_ASTRR_PPCE_FPE__PPCE__V = ^x1	
                  [000000]  1831  EV6__ASTER_ASTRR_PPCE_FPE__PPCE__M = ^x1	
                  [000000]  1832  EV6__ASTER_ASTRR_PPCE_FPE__FPE__S = ^x2	
                  [000000]  1833  EV6__ASTER_ASTRR_PPCE_FPE__FPE__V = ^x1	
                  [000000]  1834  EV6__ASTER_ASTRR_PPCE_FPE__FPE__M = ^x1	
                  [000000]  1835  EV6__ASTER_ASTRR_PPCE_FPE__RSV1__S = ^x3	
                  [000000]  1836  EV6__ASTER_ASTRR_PPCE_FPE__RSV1__V = ^x2	
                  [000000]  1837  EV6__ASTER_ASTRR_PPCE_FPE__RSV1__M = ^x3	
                  [000000]  1838  EV6__ASTER_ASTRR_PPCE_FPE__ASTER__S = ^x5	
                  [000000]  1839  EV6__ASTER_ASTRR_PPCE_FPE__ASTER__V = ^x4	
                  [000000]  1840  EV6__ASTER_ASTRR_PPCE_FPE__ASTER__M = ^xf	
                  [000000]  1841  EV6__ASTER_ASTRR_PPCE_FPE__ASTRR__S = ^x9	
                  [000000]  1842  EV6__ASTER_ASTRR_PPCE_FPE__ASTRR__V = ^x4	
                  [000000]  1843  EV6__ASTER_ASTRR_PPCE_FPE__ASTRR__M = ^xf	
                  [000000]  1844  EV6__ASTER_ASTRR_PPCE_FPE__RSV2__S = ^xd	
                  [000000]  1845  EV6__ASTER_ASTRR_PPCE_FPE__RSV2__V = ^x1a	
                  [000000]  1846  EV6__ASTER_ASTRR_PPCE_FPE__RSV2__M = ^x3ffffff	
                  [000000]  1847  EV6__ASTER_ASTRR_PPCE_FPE__ASN__S = ^x27	
                  [000000]  1848  EV6__ASTER_ASTRR_PPCE_FPE__ASN__V = ^x8	
                  [000000]  1849  EV6__ASTER_ASTRR_PPCE_FPE__ASN__M = ^xff	
                  [000000]  1850  EV6__ASTER_ASTRR_PPCE_FPE__RSV3__S = ^x2f	
                  [000000]  1851  EV6__ASTER_ASTRR_PPCE_FPE__RSV3__V = ^x11	
                  [000000]  1852  EV6__ASTER_ASTRR_PPCE_FPE__RSV3__M = ^x1ffff	
                  [000000]  1853  
                  [000000]  1854  EV6__PROCESS_CONTEXT = ^x5f	
                  [000000]  1855  EV6__PROCESS_CONTEXT__RSV0__S = ^x0	
                  [000000]  1856  EV6__PROCESS_CONTEXT__RSV0__V = ^x1	
                  [000000]  1857  EV6__PROCESS_CONTEXT__RSV0__M = ^x1	
                  [000000]  1858  EV6__PROCESS_CONTEXT__PPCE__S = ^x1	
                  [000000]  1859  EV6__PROCESS_CONTEXT__PPCE__V = ^x1	
                  [000000]  1860  EV6__PROCESS_CONTEXT__PPCE__M = ^x1	
                  [000000]  1861  EV6__PROCESS_CONTEXT__FPE__S = ^x2	
                  [000000]  1862  EV6__PROCESS_CONTEXT__FPE__V = ^x1	
                  [000000]  1863  EV6__PROCESS_CONTEXT__FPE__M = ^x1	
                  [000000]  1864  EV6__PROCESS_CONTEXT__RSV1__S = ^x3	
                  [000000]  1865  EV6__PROCESS_CONTEXT__RSV1__V = ^x2	
                  [000000]  1866  EV6__PROCESS_CONTEXT__RSV1__M = ^x3	
                  [000000]  1867  EV6__PROCESS_CONTEXT__ASTER__S = ^x5	
                  [000000]  1868  EV6__PROCESS_CONTEXT__ASTER__V = ^x4	
                  [000000]  1869  EV6__PROCESS_CONTEXT__ASTER__M = ^xf	
                  [000000]  1870  EV6__PROCESS_CONTEXT__ASTRR__S = ^x9	
                  [000000]  1871  EV6__PROCESS_CONTEXT__ASTRR__V = ^x4	
                  [000000]  1872  EV6__PROCESS_CONTEXT__ASTRR__M = ^xf	
                  [000000]  1873  EV6__PROCESS_CONTEXT__RSV2__S = ^xd	
                  [000000]  1874  EV6__PROCESS_CONTEXT__RSV2__V = ^x1a	
                  [000000]  1875  EV6__PROCESS_CONTEXT__RSV2__M = ^x3ffffff	
                  [000000]  1876  EV6__PROCESS_CONTEXT__ASN__S = ^x27	
                  [000000]  1877  EV6__PROCESS_CONTEXT__ASN__V = ^x8	
                  [000000]  1878  EV6__PROCESS_CONTEXT__ASN__M = ^xff	
                  [000000]  1879  EV6__PROCESS_CONTEXT__RSV3__S = ^x2f	
                  [000000]  1880  EV6__PROCESS_CONTEXT__RSV3__V = ^x11	
                  [000000]  1881  EV6__PROCESS_CONTEXT__RSV3__M = ^x1ffff	
                  [000000]  1882  
                  [000000]  1883  EV6__DTB_TAG0 = ^x20	
                  [000000]  1884  EV6__DTB_TAG0__RSV1__S = ^x0	
                  [000000]  1885  EV6__DTB_TAG0__RSV1__V = ^xd	
                  [000000]  1886  EV6__DTB_TAG0__RSV1__M = ^x1fff	
                  [000000]  1887  EV6__DTB_TAG0__VA__S = ^xd	
                  [000000]  1888  EV6__DTB_TAG0__VA__V = ^x23	
                  [000000]  1889  EV6__DTB_TAG0__VA__M = ^x7ffffffff	
                  [000000]  1890  EV6__DTB_TAG0__RSV2__S = ^x30	
                  [000000]  1891  EV6__DTB_TAG0__RSV2__V = ^x10	
                  [000000]  1892  EV6__DTB_TAG0__RSV2__M = ^xffff	
                  [000000]  1893  
                  [000000]  1894  EV6__DTB_TAG1 = ^xa0	
                  [000000]  1895  EV6__DTB_TAG1__RSV1__S = ^x0	
                  [000000]  1896  EV6__DTB_TAG1__RSV1__V = ^xd	
                  [000000]  1897  EV6__DTB_TAG1__RSV1__M = ^x1fff	
                  [000000]  1898  EV6__DTB_TAG1__VA__S = ^xd	
                  [000000]  1899  EV6__DTB_TAG1__VA__V = ^x23	
                  [000000]  1900  EV6__DTB_TAG1__VA__M = ^x7ffffffff	
                  [000000]  1901  EV6__DTB_TAG1__RSV2__S = ^x30	
                  [000000]  1902  EV6__DTB_TAG1__RSV2__V = ^x10	
                  [000000]  1903  EV6__DTB_TAG1__RSV2__M = ^xffff	
                  [000000]  1904  
                  [000000]  1905  EV6__DTB_PTE0 = ^x21	
                  [000000]  1906  EV6__DTB_PTE0__RSV1__S = ^x0	
                  [000000]  1907  EV6__DTB_PTE0__RSV1__V = ^x1	
                  [000000]  1908  EV6__DTB_PTE0__RSV1__M = ^x1	
                  [000000]  1909  EV6__DTB_PTE0__FOR__S = ^x1	
                  [000000]  1910  EV6__DTB_PTE0__FOR__V = ^x1	
                  [000000]  1911  EV6__DTB_PTE0__FOR__M = ^x1	
                  [000000]  1912  EV6__DTB_PTE0__FOW__S = ^x2	
                  [000000]  1913  EV6__DTB_PTE0__FOW__V = ^x1	
                  [000000]  1914  EV6__DTB_PTE0__FOW__M = ^x1	
                  [000000]  1915  EV6__DTB_PTE0__RSV2__S = ^x3	
                  [000000]  1916  EV6__DTB_PTE0__RSV2__V = ^x1	
                  [000000]  1917  EV6__DTB_PTE0__RSV2__M = ^x1	
                  [000000]  1918  EV6__DTB_PTE0__ASM__S = ^x4	
                  [000000]  1919  EV6__DTB_PTE0__ASM__V = ^x1	
                  [000000]  1920  EV6__DTB_PTE0__ASM__M = ^x1	
                  [000000]  1921  EV6__DTB_PTE0__GH__S = ^x5	
                  [000000]  1922  EV6__DTB_PTE0__GH__V = ^x2	
                  [000000]  1923  EV6__DTB_PTE0__GH__M = ^x3	
                  [000000]  1924  EV6__DTB_PTE0__RSV3__S = ^x7	
                  [000000]  1925  EV6__DTB_PTE0__RSV3__V = ^x1	
                  [000000]  1926  EV6__DTB_PTE0__RSV3__M = ^x1	
                  [000000]  1927  EV6__DTB_PTE0__KRE__S = ^x8	
                  [000000]  1928  EV6__DTB_PTE0__KRE__V = ^x1	
                  [000000]  1929  EV6__DTB_PTE0__KRE__M = ^x1	
                  [000000]  1930  EV6__DTB_PTE0__ERE__S = ^x9	
                  [000000]  1931  EV6__DTB_PTE0__ERE__V = ^x1	
                  [000000]  1932  EV6__DTB_PTE0__ERE__M = ^x1	
                  [000000]  1933  EV6__DTB_PTE0__SRE__S = ^xa	
                  [000000]  1934  EV6__DTB_PTE0__SRE__V = ^x1	
                  [000000]  1935  EV6__DTB_PTE0__SRE__M = ^x1	
                  [000000]  1936  EV6__DTB_PTE0__URE__S = ^xb	
                  [000000]  1937  EV6__DTB_PTE0__URE__V = ^x1	
                  [000000]  1938  EV6__DTB_PTE0__URE__M = ^x1	
                  [000000]  1939  EV6__DTB_PTE0__KWE__S = ^xc	
                  [000000]  1940  EV6__DTB_PTE0__KWE__V = ^x1	
                  [000000]  1941  EV6__DTB_PTE0__KWE__M = ^x1	
                  [000000]  1942  EV6__DTB_PTE0__EWE__S = ^xd	
                  [000000]  1943  EV6__DTB_PTE0__EWE__V = ^x1	
                  [000000]  1944  EV6__DTB_PTE0__EWE__M = ^x1	
                  [000000]  1945  EV6__DTB_PTE0__SWE__S = ^xe	
                  [000000]  1946  EV6__DTB_PTE0__SWE__V = ^x1	
                  [000000]  1947  EV6__DTB_PTE0__SWE__M = ^x1	
                  [000000]  1948  EV6__DTB_PTE0__UWE__S = ^xf	
                  [000000]  1949  EV6__DTB_PTE0__UWE__V = ^x1	
                  [000000]  1950  EV6__DTB_PTE0__UWE__M = ^x1	
                  [000000]  1951  EV6__DTB_PTE0__RSV4__S = ^x10	
                  [000000]  1952  EV6__DTB_PTE0__RSV4__V = ^x10	
                  [000000]  1953  EV6__DTB_PTE0__RSV4__M = ^xffff	
                  [000000]  1954  EV6__DTB_PTE0__PFN__S = ^x20	
                  [000000]  1955  EV6__DTB_PTE0__PFN__V = ^x1f	
                  [000000]  1956  EV6__DTB_PTE0__PFN__M = ^x7fffffff	
                  [000000]  1957  EV6__DTB_PTE0__RSV5__S = ^x3f	
                  [000000]  1958  EV6__DTB_PTE0__RSV5__V = ^x1	
                  [000000]  1959  EV6__DTB_PTE0__RSV5__M = ^x1	
                  [000000]  1960  
                  [000000]  1961  EV6__DTB_PTE1 = ^xa1	
                  [000000]  1962  EV6__DTB_PTE1__RSV1__S = ^x0	
                  [000000]  1963  EV6__DTB_PTE1__RSV1__V = ^x1	
                  [000000]  1964  EV6__DTB_PTE1__RSV1__M = ^x1	
                  [000000]  1965  EV6__DTB_PTE1__FOR__S = ^x1	
                  [000000]  1966  EV6__DTB_PTE1__FOR__V = ^x1	
                  [000000]  1967  EV6__DTB_PTE1__FOR__M = ^x1	
                  [000000]  1968  EV6__DTB_PTE1__FOW__S = ^x2	
                  [000000]  1969  EV6__DTB_PTE1__FOW__V = ^x1	
                  [000000]  1970  EV6__DTB_PTE1__FOW__M = ^x1	
                  [000000]  1971  EV6__DTB_PTE1__RSV2__S = ^x3	
                  [000000]  1972  EV6__DTB_PTE1__RSV2__V = ^x1	
                  [000000]  1973  EV6__DTB_PTE1__RSV2__M = ^x1	
                  [000000]  1974  EV6__DTB_PTE1__ASM__S = ^x4	
                  [000000]  1975  EV6__DTB_PTE1__ASM__V = ^x1	
                  [000000]  1976  EV6__DTB_PTE1__ASM__M = ^x1	
                  [000000]  1977  EV6__DTB_PTE1__GH__S = ^x5	
                  [000000]  1978  EV6__DTB_PTE1__GH__V = ^x2	
                  [000000]  1979  EV6__DTB_PTE1__GH__M = ^x3	
                  [000000]  1980  EV6__DTB_PTE1__RSV3__S = ^x7	
                  [000000]  1981  EV6__DTB_PTE1__RSV3__V = ^x1	
                  [000000]  1982  EV6__DTB_PTE1__RSV3__M = ^x1	
                  [000000]  1983  EV6__DTB_PTE1__KRE__S = ^x8	
                  [000000]  1984  EV6__DTB_PTE1__KRE__V = ^x1	
                  [000000]  1985  EV6__DTB_PTE1__KRE__M = ^x1	
                  [000000]  1986  EV6__DTB_PTE1__ERE__S = ^x9	
                  [000000]  1987  EV6__DTB_PTE1__ERE__V = ^x1	
                  [000000]  1988  EV6__DTB_PTE1__ERE__M = ^x1	
                  [000000]  1989  EV6__DTB_PTE1__SRE__S = ^xa	
                  [000000]  1990  EV6__DTB_PTE1__SRE__V = ^x1	
                  [000000]  1991  EV6__DTB_PTE1__SRE__M = ^x1	
                  [000000]  1992  EV6__DTB_PTE1__URE__S = ^xb	
                  [000000]  1993  EV6__DTB_PTE1__URE__V = ^x1	
                  [000000]  1994  EV6__DTB_PTE1__URE__M = ^x1	
                  [000000]  1995  EV6__DTB_PTE1__KWE__S = ^xc	
                  [000000]  1996  EV6__DTB_PTE1__KWE__V = ^x1	
                  [000000]  1997  EV6__DTB_PTE1__KWE__M = ^x1	
                  [000000]  1998  EV6__DTB_PTE1__EWE__S = ^xd	
                  [000000]  1999  EV6__DTB_PTE1__EWE__V = ^x1	
                  [000000]  2000  EV6__DTB_PTE1__EWE__M = ^x1	
                  [000000]  2001  EV6__DTB_PTE1__SWE__S = ^xe	
                  [000000]  2002  EV6__DTB_PTE1__SWE__V = ^x1	
                  [000000]  2003  EV6__DTB_PTE1__SWE__M = ^x1	
                  [000000]  2004  EV6__DTB_PTE1__UWE__S = ^xf	
                  [000000]  2005  EV6__DTB_PTE1__UWE__V = ^x1	
                  [000000]  2006  EV6__DTB_PTE1__UWE__M = ^x1	
                  [000000]  2007  EV6__DTB_PTE1__RSV4__S = ^x10	
                  [000000]  2008  EV6__DTB_PTE1__RSV4__V = ^x10	
                  [000000]  2009  EV6__DTB_PTE1__RSV4__M = ^xffff	
                  [000000]  2010  EV6__DTB_PTE1__PFN__S = ^x20	
                  [000000]  2011  EV6__DTB_PTE1__PFN__V = ^x1f	
                  [000000]  2012  EV6__DTB_PTE1__PFN__M = ^x7fffffff	
                  [000000]  2013  EV6__DTB_PTE1__RSV5__S = ^x3f	
                  [000000]  2014  EV6__DTB_PTE1__RSV5__V = ^x1	
                  [000000]  2015  EV6__DTB_PTE1__RSV5__M = ^x1	
                  [000000]  2016  
                  [000000]  2017  EV6__DTB_IAP = ^xa2	
                  [000000]  2018  EV6__DTB_IAP__RSV__S = ^x0	
                  [000000]  2019  EV6__DTB_IAP__RSV__V = ^x40	
                  [000000]  2020  EV6__DTB_IAP__RSV__M = ^xffffffffffffffff	
                  [000000]  2021  
                  [000000]  2022  EV6__DTB_IA = ^xa3	
                  [000000]  2023  EV6__DTB_IA__RSV__S = ^x0	
                  [000000]  2024  EV6__DTB_IA__RSV__V = ^x40	
                  [000000]  2025  EV6__DTB_IA__RSV__M = ^xffffffffffffffff	
                  [000000]  2026  
                  [000000]  2027  EV6__DTB_IS0 = ^x24	
                  [000000]  2028  EV6__DTB_IS0__RSV1__S = ^x0	
                  [000000]  2029  EV6__DTB_IS0__RSV1__V = ^xd	
                  [000000]  2030  EV6__DTB_IS0__RSV1__M = ^x1fff	
                  [000000]  2031  EV6__DTB_IS0__VA__S = ^xd	
                  [000000]  2032  EV6__DTB_IS0__VA__V = ^x23	
                  [000000]  2033  EV6__DTB_IS0__VA__M = ^x7ffffffff	
                  [000000]  2034  EV6__DTB_IS0__RSV2__S = ^x30	
                  [000000]  2035  EV6__DTB_IS0__RSV2__V = ^x10	
                  [000000]  2036  EV6__DTB_IS0__RSV2__M = ^xffff	
                  [000000]  2037  
                  [000000]  2038  EV6__DTB_IS1 = ^xa4	
                  [000000]  2039  EV6__DTB_IS1__RSV1__S = ^x0	
                  [000000]  2040  EV6__DTB_IS1__RSV1__V = ^xd	
                  [000000]  2041  EV6__DTB_IS1__RSV1__M = ^x1fff	
                  [000000]  2042  EV6__DTB_IS1__VA__S = ^xd	
                  [000000]  2043  EV6__DTB_IS1__VA__V = ^x23	
                  [000000]  2044  EV6__DTB_IS1__VA__M = ^x7ffffffff	
                  [000000]  2045  EV6__DTB_IS1__RSV2__S = ^x30	
                  [000000]  2046  EV6__DTB_IS1__RSV2__V = ^x10	
                  [000000]  2047  EV6__DTB_IS1__RSV2__M = ^xffff	
                  [000000]  2048  
                  [000000]  2049  EV6__DTB_ASN0 = ^x25	
                  [000000]  2050  EV6__DTB_ASN0__RSV__S = ^x0	
                  [000000]  2051  EV6__DTB_ASN0__RSV__V = ^x38	
                  [000000]  2052  EV6__DTB_ASN0__RSV__M = ^xffffffffffffff	
                  [000000]  2053  EV6__DTB_ASN0__ASN__S = ^x38	
                  [000000]  2054  EV6__DTB_ASN0__ASN__V = ^x8	
                  [000000]  2055  EV6__DTB_ASN0__ASN__M = ^xff	
                  [000000]  2056  
                  [000000]  2057  EV6__DTB_ASN1 = ^xa5	
                  [000000]  2058  EV6__DTB_ASN1__RSV__S = ^x0	
                  [000000]  2059  EV6__DTB_ASN1__RSV__V = ^x38	
                  [000000]  2060  EV6__DTB_ASN1__RSV__M = ^xffffffffffffff	
                  [000000]  2061  EV6__DTB_ASN1__ASN__S = ^x38	
                  [000000]  2062  EV6__DTB_ASN1__ASN__V = ^x8	
                  [000000]  2063  EV6__DTB_ASN1__ASN__M = ^xff	
                  [000000]  2064  
                  [000000]  2065  EV6__DTB_ALT_MODE = ^x26	
                  [000000]  2066  EV6__DTB_ALT_MODE__MODE__S = ^x0	
                  [000000]  2067  EV6__DTB_ALT_MODE__MODE__V = ^x2	
                  [000000]  2068  EV6__DTB_ALT_MODE__MODE__M = ^x3	
                  [000000]  2069  EV6__DTB_ALT_MODE__RSV1__S = ^x2	
                  [000000]  2070  EV6__DTB_ALT_MODE__RSV1__V = ^x3e	
                  [000000]  2071  EV6__DTB_ALT_MODE__RSV1__M = ^x3fffffffffffffff	
                  [000000]  2072  
                  [000000]  2073  EV6__MM_STAT = ^x27	
                  [000000]  2074  EV6__MM_STAT__WR__S = ^x0	
                  [000000]  2075  EV6__MM_STAT__WR__V = ^x1	
                  [000000]  2076  EV6__MM_STAT__WR__M = ^x1	
                  [000000]  2077  EV6__MM_STAT__ACV__S = ^x1	
                  [000000]  2078  EV6__MM_STAT__ACV__V = ^x1	
                  [000000]  2079  EV6__MM_STAT__ACV__M = ^x1	
                  [000000]  2080  EV6__MM_STAT__FOR__S = ^x2	
                  [000000]  2081  EV6__MM_STAT__FOR__V = ^x1	
                  [000000]  2082  EV6__MM_STAT__FOR__M = ^x1	
                  [000000]  2083  EV6__MM_STAT__FOW__S = ^x3	
                  [000000]  2084  EV6__MM_STAT__FOW__V = ^x1	
                  [000000]  2085  EV6__MM_STAT__FOW__M = ^x1	
                  [000000]  2086  EV6__MM_STAT__OPCODE__S = ^x4	
                  [000000]  2087  EV6__MM_STAT__OPCODE__V = ^x6	
                  [000000]  2088  EV6__MM_STAT__OPCODE__M = ^x3f	
                  [000000]  2089  EV6__MM_STAT__DC_TAG_PERR__S = ^xa	
                  [000000]  2090  EV6__MM_STAT__DC_TAG_PERR__V = ^x1	
                  [000000]  2091  EV6__MM_STAT__DC_TAG_PERR__M = ^x1	
                  [000000]  2092  EV6__MM_STAT__RSV1__S = ^xb	
                  [000000]  2093  EV6__MM_STAT__RSV1__V = ^x35	
                  [000000]  2094  EV6__MM_STAT__RSV1__M = ^x1fffffffffffff	
                  [000000]  2095  
                  [000000]  2096  EV6__M_CTL = ^x28	
                  [000000]  2097  EV6__M_CTL__RSV1__S = ^x0	
                  [000000]  2098  EV6__M_CTL__RSV1__V = ^x1	
                  [000000]  2099  EV6__M_CTL__RSV1__M = ^x1	
                  [000000]  2100  EV6__M_CTL__SPE__S = ^x1	
                  [000000]  2101  EV6__M_CTL__SPE__V = ^x3	
                  [000000]  2102  EV6__M_CTL__SPE__M = ^x7	
                  [000000]  2103  EV6__M_CTL__SPEC_ST_CONS__S = ^x4	
                  [000000]  2104  EV6__M_CTL__SPEC_ST_CONS__V = ^x2	
                  [000000]  2105  EV6__M_CTL__SPEC_ST_CONS__M = ^x3	
                  [000000]  2106  EV6__M_CTL__RSV2__S = ^x6	
                  [000000]  2107  EV6__M_CTL__RSV2__V = ^x3a	
                  [000000]  2108  EV6__M_CTL__RSV2__M = ^x3ffffffffffffff	
                  [000000]  2109  
                  [000000]  2110  EV6__DC_CTL = ^x29	
                  [000000]  2111  EV6__DC_CTL__SET_EN__S = ^x0	
                  [000000]  2112  EV6__DC_CTL__SET_EN__V = ^x2	
                  [000000]  2113  EV6__DC_CTL__SET_EN__M = ^x3	
                  [000000]  2114  EV6__DC_CTL__F_HIT__S = ^x2	
                  [000000]  2115  EV6__DC_CTL__F_HIT__V = ^x1	
                  [000000]  2116  EV6__DC_CTL__F_HIT__M = ^x1	
                  [000000]  2117  EV6__DC_CTL__FLUSH__S = ^x3	
                  [000000]  2118  EV6__DC_CTL__FLUSH__V = ^x1	
                  [000000]  2119  EV6__DC_CTL__FLUSH__M = ^x1	
                  [000000]  2120  EV6__DC_CTL__F_BAD_TPAR__S = ^x4	
                  [000000]  2121  EV6__DC_CTL__F_BAD_TPAR__V = ^x1	
                  [000000]  2122  EV6__DC_CTL__F_BAD_TPAR__M = ^x1	
                  [000000]  2123  EV6__DC_CTL__F_BAD_DECC__S = ^x5	
                  [000000]  2124  EV6__DC_CTL__F_BAD_DECC__V = ^x1	
                  [000000]  2125  EV6__DC_CTL__F_BAD_DECC__M = ^x1	
                  [000000]  2126  EV6__DC_CTL__DCTAG_PAR_EN__S = ^x6	
                  [000000]  2127  EV6__DC_CTL__DCTAG_PAR_EN__V = ^x1	
                  [000000]  2128  EV6__DC_CTL__DCTAG_PAR_EN__M = ^x1	
                  [000000]  2129  EV6__DC_CTL__DCDAT_ERR_EN__S = ^x7	
                  [000000]  2130  EV6__DC_CTL__DCDAT_ERR_EN__V = ^x1	
                  [000000]  2131  EV6__DC_CTL__DCDAT_ERR_EN__M = ^x1	
                  [000000]  2132  EV6__DC_CTL__RSV1__S = ^x8	
                  [000000]  2133  EV6__DC_CTL__RSV1__V = ^x38	
                  [000000]  2134  EV6__DC_CTL__RSV1__M = ^xffffffffffffff	
                  [000000]  2135  
                  [000000]  2136  EV6__DC_STAT = ^x2a	
                  [000000]  2137  EV6__DC_STAT__TPERR_P0__S = ^x0	
                  [000000]  2138  EV6__DC_STAT__TPERR_P0__V = ^x1	
                  [000000]  2139  EV6__DC_STAT__TPERR_P0__M = ^x1	
                  [000000]  2140  EV6__DC_STAT__TPERR_P1__S = ^x1	
                  [000000]  2141  EV6__DC_STAT__TPERR_P1__V = ^x1	
                  [000000]  2142  EV6__DC_STAT__TPERR_P1__M = ^x1	
                  [000000]  2143  EV6__DC_STAT__ECC_ERR_ST__S = ^x2	
                  [000000]  2144  EV6__DC_STAT__ECC_ERR_ST__V = ^x1	
                  [000000]  2145  EV6__DC_STAT__ECC_ERR_ST__M = ^x1	
                  [000000]  2146  EV6__DC_STAT__ECC_ERR_LD__S = ^x3	
                  [000000]  2147  EV6__DC_STAT__ECC_ERR_LD__V = ^x1	
                  [000000]  2148  EV6__DC_STAT__ECC_ERR_LD__M = ^x1	
                  [000000]  2149  EV6__DC_STAT__SEO__S = ^x4	
                  [000000]  2150  EV6__DC_STAT__SEO__V = ^x1	
                  [000000]  2151  EV6__DC_STAT__SEO__M = ^x1	
                  [000000]  2152  EV6__DC_STAT__RSV1__S = ^x5	
                  [000000]  2153  EV6__DC_STAT__RSV1__V = ^x3b	
                  [000000]  2154  EV6__DC_STAT__RSV1__M = ^x7ffffffffffffff	
                  [000000]  2155  
                  [000000]  2156  EV6__DATA = ^x2b	
                  [000000]  2157  EV6__DATA__C_DATA__S = ^x0	
                  [000000]  2158  EV6__DATA__C_DATA__V = ^x6	
                  [000000]  2159  EV6__DATA__C_DATA__M = ^x3f	
                  [000000]  2160  EV6__DATA__RSV1__S = ^x6	
                  [000000]  2161  EV6__DATA__RSV1__V = ^x3a	
                  [000000]  2162  EV6__DATA__RSV1__M = ^x3ffffffffffffff	
                  [000000]  2163  
                  [000000]  2164  EV6__SHIFT_CONTROL = ^x2c	
                  [000000]  2165  EV6__SHIFT_CONTROL__C_SHIFT__S = ^x0	
                  [000000]  2166  EV6__SHIFT_CONTROL__C_SHIFT__V = ^x1	
                  [000000]  2167  EV6__SHIFT_CONTROL__C_SHIFT__M = ^x1	
                  [000000]  2168  EV6__SHIFT_CONTROL__RSV1__S = ^x1	
                  [000000]  2169  EV6__SHIFT_CONTROL__RSV1__V = ^x3f	
                  [000000]  2170  EV6__SHIFT_CONTROL__RSV1__M = ^x7fffffffffffffff	
                  [000000]  2171  
                  [000000]  2172  EV6__FEN = ^x10000	
                  [000000]  2173  EV6__FEN__FEN__S = ^x0	
                  [000000]  2174  EV6__FEN__FEN__V = ^x1	
                  [000000]  2175  EV6__FEN__FEN__M = ^x1	
                  [000000]  2176  EV6__FEN__RSV2__S = ^x1	
                  [000000]  2177  EV6__FEN__RSV2__V = ^x3f	
                  [000000]  2178  EV6__FEN__RSV2__M = ^x7fffffffffffffff	
                  [000000]  2179  
                  [000000]  2180  EV6__FPCR = ^x10001	
                  [000000]  2181  EV6__FPCR__RSV1__S = ^x0	
                  [000000]  2182  EV6__FPCR__RSV1__V = ^x30	
                  [000000]  2183  EV6__FPCR__RSV1__M = ^xffffffffffff	
                  [000000]  2184  EV6__FPCR__DNZ__S = ^x30	
                  [000000]  2185  EV6__FPCR__DNZ__V = ^x1	
                  [000000]  2186  EV6__FPCR__DNZ__M = ^x1	
                  [000000]  2187  EV6__FPCR__INVD__S = ^x31	
                  [000000]  2188  EV6__FPCR__INVD__V = ^x1	
                  [000000]  2189  EV6__FPCR__INVD__M = ^x1	
                  [000000]  2190  EV6__FPCR__DZED__S = ^x32	
                  [000000]  2191  EV6__FPCR__DZED__V = ^x1	
                  [000000]  2192  EV6__FPCR__DZED__M = ^x1	
                  [000000]  2193  EV6__FPCR__OVFD__S = ^x33	
                  [000000]  2194  EV6__FPCR__OVFD__V = ^x1	
                  [000000]  2195  EV6__FPCR__OVFD__M = ^x1	
                  [000000]  2196  EV6__FPCR__INV__S = ^x34	
                  [000000]  2197  EV6__FPCR__INV__V = ^x1	
                  [000000]  2198  EV6__FPCR__INV__M = ^x1	
                  [000000]  2199  EV6__FPCR__DZE__S = ^x35	
                  [000000]  2200  EV6__FPCR__DZE__V = ^x1	
                  [000000]  2201  EV6__FPCR__DZE__M = ^x1	
                  [000000]  2202  EV6__FPCR__OVF__S = ^x36	
                  [000000]  2203  EV6__FPCR__OVF__V = ^x1	
                  [000000]  2204  EV6__FPCR__OVF__M = ^x1	
                  [000000]  2205  EV6__FPCR__UNF__S = ^x37	
                  [000000]  2206  EV6__FPCR__UNF__V = ^x1	
                  [000000]  2207  EV6__FPCR__UNF__M = ^x1	
                  [000000]  2208  EV6__FPCR__INE__S = ^x38	
                  [000000]  2209  EV6__FPCR__INE__V = ^x1	
                  [000000]  2210  EV6__FPCR__INE__M = ^x1	
                  [000000]  2211  EV6__FPCR__IOV__S = ^x39	
                  [000000]  2212  EV6__FPCR__IOV__V = ^x1	
                  [000000]  2213  EV6__FPCR__IOV__M = ^x1	
                  [000000]  2214  EV6__FPCR__DYN__S = ^x3a	
                  [000000]  2215  EV6__FPCR__DYN__V = ^x2	
                  [000000]  2216  EV6__FPCR__DYN__M = ^x3	
                  [000000]  2217  EV6__FPCR__UNDZ__S = ^x3c	
                  [000000]  2218  EV6__FPCR__UNDZ__V = ^x1	
                  [000000]  2219  EV6__FPCR__UNDZ__M = ^x1	
                  [000000]  2220  EV6__FPCR__UNFD__S = ^x3d	
                  [000000]  2221  EV6__FPCR__UNFD__V = ^x1	
                  [000000]  2222  EV6__FPCR__UNFD__M = ^x1	
                  [000000]  2223  EV6__FPCR__INED__S = ^x3e	
                  [000000]  2224  EV6__FPCR__INED__V = ^x1	
                  [000000]  2225  EV6__FPCR__INED__M = ^x1	
                  [000000]  2226  EV6__FPCR__SUM__S = ^x3f	
                  [000000]  2227  EV6__FPCR__SUM__V = ^x1	
                  [000000]  2228  EV6__FPCR__SUM__M = ^x1	
                  [000000]  2229  
                  [000000]  2230  EV6__HW_INT_REG = ^x1000e	
                  [000000]  2231  EV6__HW_INT_REG__RSV1__S = ^x0	
                  [000000]  2232  EV6__HW_INT_REG__RSV1__V = ^x1a	
                  [000000]  2233  EV6__HW_INT_REG__RSV1__M = ^x3ffffff	
                  [000000]  2234  EV6__HW_INT_REG__FBTP__S = ^x1a	
                  [000000]  2235  EV6__HW_INT_REG__FBTP__V = ^x1	
                  [000000]  2236  EV6__HW_INT_REG__FBTP__M = ^x1	
                  [000000]  2237  EV6__HW_INT_REG__FBDP__S = ^x1b	
                  [000000]  2238  EV6__HW_INT_REG__FBDP__V = ^x1	
                  [000000]  2239  EV6__HW_INT_REG__FBDP__M = ^x1	
                  [000000]  2240  EV6__HW_INT_REG__MCHK_D__S = ^x1c	
                  [000000]  2241  EV6__HW_INT_REG__MCHK_D__V = ^x1	
                  [000000]  2242  EV6__HW_INT_REG__MCHK_D__M = ^x1	
                  [000000]  2243  EV6__HW_INT_REG__PC__S = ^x1d	
                  [000000]  2244  EV6__HW_INT_REG__PC__V = ^x2	
                  [000000]  2245  EV6__HW_INT_REG__PC__M = ^x3	
                  [000000]  2246  EV6__HW_INT_REG__CR__S = ^x1f	
                  [000000]  2247  EV6__HW_INT_REG__CR__V = ^x1	
                  [000000]  2248  EV6__HW_INT_REG__CR__M = ^x1	
                  [000000]  2249  EV6__HW_INT_REG__SL__S = ^x20	
                  [000000]  2250  EV6__HW_INT_REG__SL__V = ^x1	
                  [000000]  2251  EV6__HW_INT_REG__SL__M = ^x1	
                  [000000]  2252  EV6__HW_INT_REG__RSV2__S = ^x21	
                  [000000]  2253  EV6__HW_INT_REG__RSV2__V = ^x1f	
                  [000000]  2254  EV6__HW_INT_REG__RSV2__M = ^x7fffffff	
                  [000000]  2255  
                  [000000]  2256  EV6__PMPC = ^x5	
                  [000000]  2257  EV6__PMPC__PAL__S = ^x0	
                  [000000]  2258  EV6__PMPC__PAL__V = ^x1	
                  [000000]  2259  EV6__PMPC__PAL__M = ^x1	
                  [000000]  2260  EV6__PMPC__RSV__S = ^x1	
                  [000000]  2261  EV6__PMPC__RSV__V = ^x1	
                  [000000]  2262  EV6__PMPC__RSV__M = ^x1	
                  [000000]  2263  EV6__PMPC__PC__S = ^x2	
                  [000000]  2264  EV6__PMPC__PC__V = ^x3e	
                  [000000]  2265  EV6__PMPC__PC__M = ^x3fffffffffffffff	
                  [000000]  2266  
                  [000000]  2267  EV6_SCB__CC = ^x20	
                  [000000]  2268  EV6_SCB__CC_CTL = ^x20	
                  [000000]  2269  EV6_SCB__VA = ^xf0	
                  [000000]  2270  EV6_SCB__VA_FORM = ^xf0	
                  [000000]  2271  EV6_SCB__VA_CTL = ^x20	
                  [000000]  2272  EV6_SCB__ITB_TAG = ^x40	
                  [000000]  2273  EV6_SCB__ITB_PTE = ^x11	
                  [000000]  2274  EV6_SCB__ITB_IAP = ^x10	
                  [000000]  2275  EV6_SCB__ITB_IA = ^x10	
                  [000000]  2276  EV6_SCB__ITB_IS = ^x50	
                  [000000]  2277  EV6_SCB__PMPC = ^x10	
                  [000000]  2278  EV6_SCB__EXC_ADDR = ^x0	
                  [000000]  2279  EV6_SCB__IVA_FORM = ^x10	
                  [000000]  2280  EV6_SCB__PS = ^x10	
                  [000000]  2281  EV6_SCB__IER = ^x10	
                  [000000]  2282  EV6_SCB__IER_CM = ^x10	
                  [000000]  2283  EV6_SCB__SIRR = ^x10	
                  [000000]  2284  EV6_SCB__ISUM = ^x0	
                  [000000]  2285  EV6_SCB__HW_INT_CLR = ^x10	
                  [000000]  2286  EV6_SCB__EXC_SUM = ^x0	
                  [000000]  2287  EV6_SCB__PAL_BASE = ^x10	
                  [000000]  2288  EV6_SCB__I_CTL = ^x10	
                  [000000]  2289  EV6_SCB__IC_FLUSH = ^x10	
                  [000000]  2290  EV6_SCB__IC_FLUSH_ASM = ^x10	
                  [000000]  2291  EV6_SCB__PCTR_CTL = ^x10	
                  [000000]  2292  EV6_SCB__CLR_MAP = ^xf0	
                  [000000]  2293  EV6_SCB__I_STAT = ^x10	
                  [000000]  2294  EV6_SCB__ASN = ^x10	
                  [000000]  2295  EV6_SCB__ASTER = ^x10	
                  [000000]  2296  EV6_SCB__ASTRR = ^x10	
                  [000000]  2297  EV6_SCB__PPCE = ^x10	
                  [000000]  2298  EV6_SCB__FPE = ^x10	
                  [000000]  2299  EV6_SCB__PROCESS_CONTEXT = ^x10	
                  [000000]  2300  EV6_SCB__DTB_TAG0 = ^x44	
                  [000000]  2301  EV6_SCB__DTB_TAG1 = ^x22	
                  [000000]  2302  EV6_SCB__DTB_PTE0 = ^x11	
                  [000000]  2303  EV6_SCB__DTB_PTE1 = ^x88	
                  [000000]  2304  EV6_SCB__DTB_IAP = ^x80	
                  [000000]  2305  EV6_SCB__DTB_IA = ^x80	
                  [000000]  2306  EV6_SCB__DTB_IS0 = ^x40	
                  [000000]  2307  EV6_SCB__DTB_IS1 = ^x80	
                  [000000]  2308  EV6_SCB__DTB_ASN0 = ^x10	
                  [000000]  2309  EV6_SCB__DTB_ASN1 = ^x80	
                  [000000]  2310  EV6_SCB__DTB_ALT_MODE = ^x40	
                  [000000]  2311  EV6_SCB__MM_STAT = ^x0	
                  [000000]  2312  EV6_SCB__M_CTL = ^x40	
                  [000000]  2313  EV6_SCB__DC_CTL = ^x40	
                  [000000]  2314  EV6_SCB__DC_STAT = ^x40	
                  [000000]  2315  EV6_SCB__DATA = ^x40	
                  [000000]  2316  EV6_SCB__SHIFT_CONTROL = ^x40	
                  [000000]  2317  EV6_SCB__SLEEP = ^xf0	
                  [000000]  2318  
File: ev6_redefine_defs.mar
                  [000000]     1   EV6__CC = <EV6__CC @ 8> ! EV6_SCB__CC
                  [000000]     2   EV6__CC_CTL = <EV6__CC_CTL @ 8> ! EV6_SCB__CC_CTL
                  [000000]     3   EV6__VA = <EV6__VA @ 8> ! EV6_SCB__VA
                  [000000]     4   EV6__VA_FORM = <EV6__VA_FORM @ 8> ! EV6_SCB__VA_FORM
                  [000000]     5   EV6__VA_FORM_48 = <EV6__VA_FORM @ 8> ! EV6_SCB__VA_FORM
                  [000000]     6   EV6__VA_FORM_32 = <EV6__VA_FORM @ 8> ! EV6_SCB__VA_FORM
                  [000000]     7   EV6__VA_CTL = <EV6__VA_CTL @ 8> ! EV6_SCB__VA_CTL
                  [000000]     8   EV6__ITB_TAG = <EV6__ITB_TAG @ 8> ! EV6_SCB__ITB_TAG
                  [000000]     9   EV6__ITB_PTE = <EV6__ITB_PTE @ 8> ! EV6_SCB__ITB_PTE
                  [000000]    10   EV6__ITB_IAP = <EV6__ITB_IAP @ 8> ! EV6_SCB__ITB_IAP
                  [000000]    11   EV6__ITB_IA = <EV6__ITB_IA @ 8> ! EV6_SCB__ITB_IA
                  [000000]    12   EV6__ITB_IS = <EV6__ITB_IS @ 8> ! EV6_SCB__ITB_IS
                  [000000]    13   EV6__PMPC = <EV6__PMPC @ 8> ! EV6_SCB__PMPC
                  [000000]    14   EV6__EXC_ADDR = <EV6__EXC_ADDR @ 8> ! EV6_SCB__EXC_ADDR
                  [000000]    15   EV6__IVA_FORM = <EV6__IVA_FORM @ 8> ! EV6_SCB__IVA_FORM
                  [000000]    16   EV6__IVA_FORM_48 = <EV6__IVA_FORM @ 8> ! EV6_SCB__IVA_FORM
                  [000000]    17   EV6__IVA_FORM_32 = <EV6__IVA_FORM @ 8> ! EV6_SCB__IVA_FORM
                  [000000]    18   EV6__PS = <EV6__PS @ 8> ! EV6_SCB__PS
                  [000000]    19   EV6__IER = <EV6__IER @ 8> ! EV6_SCB__IER
                  [000000]    20   EV6__IER_CM = <EV6__IER_CM @ 8> ! EV6_SCB__IER_CM
                  [000000]    21   EV6__SIRR = <EV6__SIRR @ 8> ! EV6_SCB__SIRR
                  [000000]    22   EV6__ISUM = <EV6__ISUM @ 8> ! EV6_SCB__ISUM
                  [000000]    23   EV6__HW_INT_CLR = <EV6__HW_INT_CLR @ 8> ! EV6_SCB__HW_INT_CLR
                  [000000]    24   EV6__EXC_SUM = <EV6__EXC_SUM @ 8> ! EV6_SCB__EXC_SUM
                  [000000]    25   EV6__PAL_BASE = <EV6__PAL_BASE @ 8> ! EV6_SCB__PAL_BASE
                  [000000]    26   EV6__I_CTL = <EV6__I_CTL @ 8> ! EV6_SCB__I_CTL
                  [000000]    27   EV6__IC_FLUSH = <EV6__IC_FLUSH @ 8> ! EV6_SCB__IC_FLUSH
                  [000000]    28   EV6__IC_FLUSH_ASM = <EV6__IC_FLUSH_ASM @ 8> ! EV6_SCB__IC_FLUSH_ASM
                  [000000]    29   EV6__PCTR_CTL = <EV6__PCTR_CTL @ 8> ! EV6_SCB__PCTR_CTL
                  [000000]    30   EV6__CLR_MAP = <EV6__CLR_MAP @ 8> ! EV6_SCB__CLR_MAP
                  [000000]    31   EV6__I_STAT = <EV6__I_STAT @ 8> ! EV6_SCB__I_STAT
                  [000000]    32   EV6__ASN = <EV6__ASN @ 8> ! EV6_SCB__ASN
                  [000000]    33   EV6__ASTER = <EV6__ASTER @ 8> ! EV6_SCB__ASTER
                  [000000]    34   EV6__ASTRR = <EV6__ASTRR @ 8> ! EV6_SCB__ASTRR
                  [000000]    35   EV6__PPCE = <EV6__PPCE @ 8> ! EV6_SCB__PPCE
                  [000000]    36   EV6__FPE = <EV6__FPE @ 8> ! EV6_SCB__FPE
                  [000000]    37   EV6__ASN_ASTER = <EV6__ASN_ASTER @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    38   EV6__ASN_ASTRR = <EV6__ASN_ASTRR @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    39   EV6__ASN_PPCE = <EV6__ASN_PPCE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    40   EV6__ASN_FPE = <EV6__ASN_FPE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    41   EV6__ASTER_ASTRR = <EV6__ASTER_ASTRR @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    42   EV6__ASTER_PPCE = <EV6__ASTER_PPCE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    43   EV6__ASTER_FPE = <EV6__ASTER_FPE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    44   EV6__ASTRR_PPCE = <EV6__ASTRR_PPCE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    45   EV6__ASTRR_FPE  = <EV6__ASTRR_FPE  @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    46   EV6__PPCE_FPE = <EV6__PPCE_FPE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    47   EV6__ASN_ASTER_ASTRR = <EV6__ASN_ASTER_ASTRR @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    48   EV6__ASN_ASTER_PPCE = <EV6__ASN_ASTER_PPCE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    49   EV6__ASN_ASTER_FPE = <EV6__ASN_ASTER_FPE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    50   EV6__ASN_ASTRR_PPCE = <EV6__ASN_ASTRR_PPCE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    51   EV6__ASN_ASTRR_FPE = <EV6__ASN_ASTRR_FPE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    52   EV6__ASN_PPCE_FPE  = <EV6__ASN_PPCE_FPE  @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    53   EV6__ASTER_ASTRR_PPCE = <EV6__ASTER_ASTRR_PPCE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    54   EV6__ASTER_ASTRR_FPE = <EV6__ASTER_ASTRR_FPE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    55   EV6__ASTER_PPCE_FPE  = <EV6__ASTER_PPCE_FPE  @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    56   EV6__ASTRR_PPCE_FPE = <EV6__ASTRR_PPCE_FPE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    57   EV6__ASN_ASTER_ASTRR_PPCE = <EV6__ASN_ASTER_ASTRR_PPCE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    58   EV6__ASN_ASTER_ASTRR_FPE = <EV6__ASN_ASTER_ASTRR_FPE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    59   EV6__ASN_ASTER_PPCE_FPE = <EV6__ASN_ASTER_PPCE_FPE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    60   EV6__ASN_ASTRR_PPCE_FPE = <EV6__ASN_ASTRR_PPCE_FPE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    61   EV6__ASTER_ASTRR_PPCE_FPE = <EV6__ASTER_ASTRR_PPCE_FPE @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    62   EV6__PROCESS_CONTEXT = <EV6__PROCESS_CONTEXT @ 8> ! EV6_SCB__PROCESS_CONTEXT
                  [000000]    63   EV6__DTB_TAG0 = <EV6__DTB_TAG0 @ 8> ! EV6_SCB__DTB_TAG0
                  [000000]    64   EV6__DTB_TAG1 = <EV6__DTB_TAG1 @ 8> ! EV6_SCB__DTB_TAG1
                  [000000]    65   EV6__DTB_PTE0 = <EV6__DTB_PTE0 @ 8> ! EV6_SCB__DTB_PTE0
                  [000000]    66   EV6__DTB_PTE1 = <EV6__DTB_PTE1 @ 8> ! EV6_SCB__DTB_PTE1
                  [000000]    67   EV6__DTB_IAP = <EV6__DTB_IAP @ 8> ! EV6_SCB__DTB_IAP
                  [000000]    68   EV6__DTB_IA = <EV6__DTB_IA @ 8> ! EV6_SCB__DTB_IA
                  [000000]    69   EV6__DTB_IS0 = <EV6__DTB_IS0 @ 8> ! EV6_SCB__DTB_IS0
                  [000000]    70   EV6__DTB_IS1 = <EV6__DTB_IS1 @ 8> ! EV6_SCB__DTB_IS1
                  [000000]    71   EV6__DTB_ASN0 = <EV6__DTB_ASN0 @ 8> ! EV6_SCB__DTB_ASN0
                  [000000]    72   EV6__DTB_ASN1 = <EV6__DTB_ASN1 @ 8> ! EV6_SCB__DTB_ASN1
                  [000000]    73   EV6__DTB_ALT_MODE = <EV6__DTB_ALT_MODE @ 8> ! EV6_SCB__DTB_ALT_MODE
                  [000000]    74   EV6__MM_STAT = <EV6__MM_STAT @ 8> ! EV6_SCB__MM_STAT
                  [000000]    75   EV6__M_CTL = <EV6__M_CTL @ 8> ! EV6_SCB__M_CTL
                  [000000]    76   EV6__DC_CTL = <EV6__DC_CTL @ 8> ! EV6_SCB__DC_CTL
                  [000000]    77   EV6__DC_STAT = <EV6__DC_STAT @ 8> ! EV6_SCB__DC_STAT
                  [000000]    78   EV6__DATA = <EV6__DATA @ 8> ! EV6_SCB__DATA
                  [000000]    79   EV6__SHIFT_CONTROL = <EV6__SHIFT_CONTROL @ 8> ! EV6_SCB__SHIFT_CONTROL
                  [000000]    80   EV6__SLEEP = <EV6__SLEEP @ 8> ! EV6_SCB__SLEEP
                  [000000]    81  
File: ev6_osf_dbm.mar
                  [000000]     1  ;+
                  [000000]     2  ; ev6_osf_dbm.mar
                  [000000]     3  ;-
                  [000000]     4  
                  [000000]     5  ;+
                  [000000]     6  ; Last Edit:	20-Oct-98
                  [000000]     7  ;-
                  [000000]     8  	osfpal = 1
                  [000000]     9  	beh_model = 0
                  [000000]    10  	focus = 0
                  [000000]    11  	srom = 1
                  [000000]    12  	srm_console = 0
                  [000000]    13  	reference_platform = 1
                  [000000]    14  	dbm_serial_io = 1
                  [000000]    15  	check_interrupt_pending = 1
                  [000000]    16  	mchk_en = 0
                  [000000]    17  	outled = 1
                  [000000]    18  	force_ecc = 1
                  [000000]    19  	clrmap = 0
                  [000000]    20  	kseg_hack = 0
                  [000000]    21  	va_48 = 1
File: ev6_pal_temps.mar
                  [000000]     1  ;; Alpha assembly macro (-m) output created by DEFNR
                  [000000]     2  ;   
                  [000000]     3  ;  EV6_PAL_TEMPS.DNR  
                  [000000]     4  ;   
                  [000000]     5  ;   
                  [000000]     6  ;  LAST EDIT:	13-OCT-98  
                  [000000]     7  ;   
                  [000000]     8  ;  EDIT HISTORY  
                  [000000]     9  ;  WHO	WHEN		WHAT  
                  [000000]    10  ;  ---	----		----  
                  [000000]    11  ;  ES	19-SEP-96	JUST HAVE M_CTL AND DC_CTL IN IMPURE ONLY.  
                  [000000]    12  ;  ES	18-JUN-97	ADD P_MISC.  
                  [000000]    13  ;  ES	01-AUG-97	PUT M_CTL BACK INTO PAL_TEMPS AND IMPURE.  
                  [000000]    14  ;  ES	24-SEP-97	ADD A RESERVE LOCATION FOR DEBUGGING, ETC.  
                  [000000]    15  ;  ES	29-JUN-98	ADDED PT__SYS_EVENT  
                  [000000]    16  ;  ES	06-OCT-98	FOR SPINLOCK HACK, ADDED  
                  [000000]    17  ; 				PT__PCTR_SAVE  
                  [000000]    18  ; 				PT__PCTR_FLAG  
                  [000000]    19  ; 				PT__PCTR_R4  
                  [000000]    20  ; 				PT__PCTR_PEND  
                  [000000]    21  ; 				PT__PCTR_VMS  
                  [000000]    22  ;   
                  [000000]    23  ;   
                  [000000]    24  ;  DEFINE PREFIX AS PT  
                  [000000]    25  ;   
                  [000000]    26  ;   
                  [000000]    27  ;  DEFINE OFFSETS  
                  [000000]    28  ;   
                  [000000]    29  
                  [000000]    30  PT__VPTB = ^x0	
                  [000000]    31  PT__PTBR = ^x8	
                  [000000]    32  PT__PCBB = ^x10	
                  [000000]    33  PT__KSP = ^x18	
                  [000000]    34  PT__USP = ^x20	; OSF ONLY 
                  [000000]    35  PT__KGP = ^x28	; OSF ONLY 
                  [000000]    36  PT__ENT_ARITH = ^x30	; OSF ONLY 
                  [000000]    37  PT__ENT_IF = ^x38	; OSF ONLY 
                  [000000]    38  PT__ENT_INT = ^x40	; OSF ONLY 
                  [000000]    39  PT__ENT_MM = ^x48	; OSF ONLY 
                  [000000]    40  PT__ENT_SYS = ^x50	; OSF ONLY 
                  [000000]    41  PT__ENT_UNA = ^x58	; OSF ONLY 
                  [000000]    42  PT__STACK_PC = ^x60	; OSF ONLY 
                  [000000]    43  PT__NEW_A0 = ^x68	; OSF ONLY 
                  [000000]    44  PT__NEW_A1 = ^x70	; OSF ONLY 
                  [000000]    45  PT__NEW_A2 = ^x78	; OSF ONLY 
                  [000000]    46  PT__SYSVAL = ^x80	; OSF ONLY 
                  [000000]    47  PT__IMPURE = ^x88	
                  [000000]    48  PT__P_MISC = ^x90	
                  [000000]    49  PT__WHAMI = ^x98	
                  [000000]    50  PT__SCC = ^xa0	
                  [000000]    51  PT__PRBR = ^xa8	
                  [000000]    52  PT__TRAP = ^xb0	
                  [000000]    53  PT__VA_CTL = ^xb8	
                  [000000]    54  PT__M_CTL = ^xc0	
                  [000000]    55  PT__HALT_CODE = ^xc8	
                  [000000]    56  PT__VPTE_PC = ^xd0	
                  [000000]    57  PT__REG = ^xd8	
                  [000000]    58  PT__OPCODE = ^xe0	
                  [000000]    59  PT__R0 = ^xe8	
                  [000000]    60  PT__R1 = ^xf0	
                  [000000]    61  PT__R2 = ^xf8	
                  [000000]    62  PT__R3 = ^x100	
                  [000000]    63  PT__R8 = ^x108	
                  [000000]    64  PT__R9 = ^x110	
                  [000000]    65  PT__R25 = ^x118	
                  [000000]    66  PT__R26 = ^x120	
                  [000000]    67  PT__NEW_PS = ^x128	; PS FOR POST INTERRUPT 
                  [000000]    68  PT__CH_MODE = ^x130	
                  [000000]    69  PT__CH_SP = ^x138	
                  [000000]    70  PT__CALL_PAL_PC = ^x140	
                  [000000]    71  PT__DTB_ALT_MODE = ^x148	
                  [000000]    72  PT__FAULT_PC = ^x150	
                  [000000]    73  PT__FAULT_SCB = ^x158	
                  [000000]    74  PT__FAULT_R4 = ^x160	; VA/MASK 
                  [000000]    75  PT__FAULT_R5 = ^x168	; MMF/EXC_SUM 
                  [000000]    76  PT__SCBB = ^x170	
                  [000000]    77  PT__RSV_FOR_PAL = ^x178	; RESERVED FOR PALCODE 
                  [000000]    78  PT__SYS_EVENT = ^x180	
                  [000000]    79  PT__PCTR_SAVE = ^x188	
                  [000000]    80  PT__PCTR_FLAG = ^x190	
                  [000000]    81  PT__PCTR_R4 = ^x198	
                  [000000]    82  PT__PCTR_PEND = ^x1a0	
                  [000000]    83  PT__PCTR_VMS = ^x1a8	
                  [000000]    84  
File: ev6_alpha_defs.mar
                  [000000]     1  ;+
                  [000000]     2  ; ev6_alpha_defs.mar
                  [000000]     3  ;
                  [000000]     4  ; This file is for ev6 specific definitions not covered by
                  [000000]     5  ; ev6_defs.mar and ev6_redefine_defs.mar
                  [000000]     6  ;-
                  [000000]     7  
                  [000000]     8  ;+
                  [000000]     9  ; Last Edit:	21-Oct-98
                  [000000]    10  ;
                  [000000]    11  ; Edit History
                  [000000]    12  ;
                  [000000]    13  ; Who	Rev	When		What
                  [000000]    14  ; ---	---	----		----
                  [000000]    15  ; ES		12-Sep-96	Added 'jump through 0' halt code
                  [000000]    16  ; ES		21-Nov-96	Took out cbox shift chain values
                  [000000]    17  ; ES		10-Apr-97	Redefined cbox status register
                  [000000]    18  ; ES		31-Oct-97	Add HALT__DC_TAG_PERR_FROM_PAL
                  [000000]    19  ;				Fixed machine check codes
                  [000000]    20  ; ES		03-Feb-98	Added C_STAT bit
                  [000000]    21  ; ES		19-Mar-98	Added MCHK__SYS_CORR_ECC
                  [000000]    22  ; ES		29-Jun-98	Added HALT__LFU_START and
                  [000000]    23  ;					MCHK__SYS_EVENT
                  [000000]    24  ; ES		21-Oct-98	Added MCHK__ISTREAM_CMOV,
                  [000000]    25  ;					MCHK__ISTREAM_CMOV_FAULT
                  [000000]    26  ;-
                  [000000]    27  
                  [000000]    28  ;
                  [000000]    29  ; PAL_SHADOW_DEF
                  [000000]    30  ;
                  [000000]    31  .macro	PAL_SHADOW_DEFS
                  [000000]    32  	p4	=   4
                  [000000]    33  	p5	=   5
                  [000000]    34  	p6	=   6
                  [000000]    35  	p7	=   7
                  [000000]    36  	p20	=  20
                  [000000]    37  	p21	=  21
                  [000000]    38  	p_temp	=  21
                  [000000]    39  	p22	=  22
                  [000000]    40  	p_misc	=  22
                  [000000]    41  	p23	=  23
                  [000000]    42  .endm	PAL_SHADOW_DEFS
                  [000000]    43  
                  [000000]    44  ;
                  [000000]    45  ; Machine Check Error Summary Register Defintion
                  [000000]    46  ;
                  [000000]    47  .macro	MCES_DEFS
                  [000000]    48  	MCES__MCHK__S	= 0
                  [000000]    49  	MCES__SCE__S	= 1
                  [000000]    50  	MCES__PCE__S	= 2
                  [000000]    51  	MCES__DPC__S	= 3
                  [000000]    52  	MCES__DSC__S	= 4
                  [000000]    53  .endm	MCES_DEFS
                  [000000]    54  
                  [000000]    55  ;
                  [000000]    56  ; Halt codes
                  [000000]    57  ;
                  [000000]    58  .macro	HALT_DEFS
                  [000000]    59  	HALT__RESET		= 0	; bootstrap
                  [000000]    60  	HALT__HW_HALT		= 1	; console requested halt
                  [000000]    61  	HALT__KSP_INVAL		= 2	; kernel stack not valid
                  [000000]    62  	HALT__SCBB_INVAL	= 3	; invalid SCBB	
                  [000000]    63  	HALT__PTBR_INVAL	= 4	; invalid PTBR or other page table err
                  [000000]    64  	HALT__SW_HALT		= 5	; CALL_PAL HALT executed
                  [000000]    65  	HALT__DBL_MCHK		= 6	; double error abort
                  [000000]    66  	HALT__MCHK_FROM_PAL	= 7	; machine check while in PALmode
                  [000000]    67  	HALT__DC_TAG_PERR_FROM_PAL = 8	; dc_tag_perr while in PALmode
                  [000000]    68  
                  [000000]    69  	HALT__START		= ^x20
                  [000000]    70  	HALT__CALLBACK		= ^x21
                  [000000]    71  	HALT__MPSTART		= ^x22
                  [000000]    72  	HALT__LFU_START		= ^x23
                  [000000]    73  
                  [000000]    74  	HALT__JUMP0		= ^x40	; jump through 0
                  [000000]    75  
                  [000000]    76  .endm	HALT_DEFS
                  [000000]    77  
                  [000000]    78  ;
                  [000000]    79  ; Machine Check codes
                  [000000]    80  ;
                  [000000]    81  .macro	MCHK_DEFS
                  [000000]    82  	MCHK__CORR_ECC		= 67@1		; catch-all corrected mchk/crd
                  [000000]    83  	MCHK__UNKNOWN		= 69@1
                  [000000]    84  	MCHK__BUGCHECK		= 71@1
                  [000000]    85  	MCHK__OS_BUGCHECK	= 72@1
                  [000000]    86  	MCHK__PROC_HRD_ERR	= 76@1		; catch-all uncorrected mchk
                  [000000]    87  	MCHK__DC_TAG_PERR	= 79@1		; corrected dc_tag_perr
                  [000000]    88  	MCHK__ISTREAM_CMOV	= 80@1		; cmov at pc-4 on istream mchk
                  [000000]    89  	MCHK__ISTREAM_CMOV_FAULT= 81@1		; unable to get instruction
                  [000000]    90  						;	at pc-4 on istream mchk
                  [000000]    91  
                  [000000]    92  	MCHK__SYS_HRD_ERR	= 257@1
                  [000000]    93  	MCHK__SYS_CORR_ECC	= 258@1
                  [000000]    94  	MCHK__SYS_EVENT		= 259@1
                  [000000]    95  
                  [000000]    96  .endm	MCHK_DEFS
                  [000000]    97  
                  [000000]    98  ;
                  [000000]    99  ; Memory Management sizes
                  [000000]   100  ;
                  [000000]   101  .macro	MM_DEFS
                  [000000]   102  	level_bits		= 10
                  [000000]   103  	page_offset_size_bits	= 13
                  [000000]   104  	page_size_bytes		= 8192
                  [000000]   105  	va_bits_3		= 43
                  [000000]   106  	va_bits_4		= 48
                  [000000]   107  	pa_bits			= 44
                  [000000]   108  .endm	MM_DEFS
                  [000000]   109  
                  [000000]   110  ;
                  [000000]   111  ; MM_STAT_DEFS
                  [000000]   112  ;	MM_STAT will contain munged opcodes for HW_LD and HW_ST.
                  [000000]   113  ;	These codes are unique from all other opcodes, so we
                  [000000]   114  ;	can distinguish these from any others.
                  [000000]   115  ;
                  [000000]   116  .macro	MM_STAT_DEFS
                  [000000]   117  	OPCODE__HW_LD		= ^X3
                  [000000]   118  	OPCODE__HW_ST		= ^X7
                  [000000]   119  .endm	MM_STAT_DEFS
                  [000000]   120  
                  [000000]   121  ;
                  [000000]   122  ; CBOX_IPR_DEFS
                  [000000]   123  ;
                  [000000]   124  .macro	CBOX_IPR_DEFS
                  [000000]   125  ;
                  [000000]   126  ; ERR_CODE bit definitions
                  [000000]   127  ;
                  [000000]   128  	EV6__C_STAT__TYPE__S	= 0
                  [000000]   129  	EV6__C_STAT__TYPE__M	= ^x7
                  [000000]   130  	EV6__C_STAT__ISTREAM__S	= 3
                  [000000]   131  	EV6__C_STAT__ISTREAM__M	= ^x1
                  [000000]   132  	EV6__C_STAT__DOUBLE__S 	= 4
                  [000000]   133  	EV6__C_STAT__DOUBLE__M 	= ^x1
                  [000000]   134  
                  [000000]   135  .endm	CBOX_IPR_DEFS
                  [000000]   136  
                  [000000]   137  
                  [000000]   138  
                  [000000]   139  
                  [000000]   140  
                  [000000]   141  
                  [000000]   142  
                  [000000]   143  
                  [000000]   144  
                  [000000]   145  
                  [000000]   146  
                  [000000]   147  
                  [000000]   148  
File: ev6_osf_pal_defs.mar
                  [000000]     1  ;+
                  [000000]     2  ; ev6_osf_pal_defs.mar
                  [000000]     3  ;
                  [000000]     4  ; This file is for osf definitions
                  [000000]     5  ;-
                  [000000]     6  
                  [000000]     7  ;+
                  [000000]     8  ; Last Edit:	29-Jun-98
                  [000000]     9  ;
                  [000000]    10  ; Edit History
                  [000000]    11  ; Who	When		What
                  [000000]    12  ; ---	----		----
                  [000000]    13  ; ES	25-Sep-96	Added a0 interrupt values to OSF_A0_DEFS.
                  [000000]    14  ;			Added IPL definitions
                  [000000]    15  ; ES	01-Aug-97	Added OSF_IPL__DEV5 and OSF_IPL__DEV6.
                  [000000]    16  ; ES	18-May-98	Added OSFPAL_FUNC__WTINT
                  [000000]    17  ; ES	29-Jun-98	Added SCB__SYS_EVENT
                  [000000]    18  ;-
                  [000000]    19  
                  [000000]    20  ;+
                  [000000]    21  ; CALL_PAL functions
                  [000000]    22  ;-
                  [000000]    23  .macro	OSFPAL_FUNC_DEFS
                  [000000]    24  	OSFPAL_FUNC__BPT	= ^x80
                  [000000]    25  	OSFPAL_FUNC__BUGCHK	= ^x81
                  [000000]    26  	OSFPAL_FUNC__CALLSYS	= ^x83
                  [000000]    27  	OSFPAL_FUNC__IMB	= ^x86
                  [000000]    28  	OSFPAL_FUNC__URTI	= ^x92
                  [000000]    29  	OSFPAL_FUNC__RDUNIQUE	= ^x9E
                  [000000]    30  	OSFPAL_FUNC__WRUNIQUE	= ^x9F
                  [000000]    31  	OSFPAL_FUNC__GENTRAP	= ^XAA
                  [000000]    32  	OSFPAL_FUNC__CLRFEN	= ^xAE
                  [000000]    33  
                  [000000]    34  	OSFPAL_FUNC__HALT	= ^x00
                  [000000]    35  	OSFPAL_FUNC__CFLUSH	= ^x01
                  [000000]    36  	OSFPAL_FUNC__DRAINA	= ^x02
                  [000000]    37  	OSFPAL_FUNC__CSERVE	= ^x09
                  [000000]    38  	OSFPAL_FUNC__SWPPAL	= ^x0A
                  [000000]    39  	OSFPAL_FUNC__WRIPIR	= ^x0D
                  [000000]    40  	OSFPAL_FUNC__RDMCES	= ^x10
                  [000000]    41  	OSFPAL_FUNC__WRMCES	= ^x11
                  [000000]    42  	OSFPAL_FUNC__WRFEN	= ^x2B
                  [000000]    43  	OSFPAL_FUNC__WRVPTPTR	= ^x2D
                  [000000]    44  	OSFPAL_FUNC__SWPCTX	= ^x30
                  [000000]    45  	OSFPAL_FUNC__WRVAL	= ^x31
                  [000000]    46  	OSFPAL_FUNC__RDVAL	= ^x32
                  [000000]    47  	OSFPAL_FUNC__TBI	= ^x33
                  [000000]    48  	OSFPAL_FUNC__WRENT	= ^x34
                  [000000]    49  	OSFPAL_FUNC__SWPIPL	= ^x35
                  [000000]    50  	OSFPAL_FUNC__RDPS	= ^x36
                  [000000]    51  	OSFPAL_FUNC__WRKGP	= ^x37
                  [000000]    52  	OSFPAL_FUNC__WRUSP	= ^x38
                  [000000]    53  	OSFPAL_FUNC__WRPERFMON	= ^x39
                  [000000]    54  	OSFPAL_FUNC__RDUSP	= ^x3A
                  [000000]    55  	OSFPAL_FUNC__WHAMI	= ^x3C
                  [000000]    56  	OSFPAL_FUNC__RETSYS	= ^x3D
                  [000000]    57  	OSFPAL_FUNC__WTINT	= ^x3E
                  [000000]    58  	OSFPAL_FUNC__RTI	= ^x3F
                  [000000]    59  .endm	OSFPAL_FUNC_DEFS
                  [000000]    60  
                  [000000]    61  
                  [000000]    62  ;+
                  [000000]    63  ; OSF_P_MISC definition
                  [000000]    64  ;-
                  [000000]    65  .macro	OSF_P_MISC_DEFS
                  [000000]    66  	OSF_P_MISC__IPL__S		= 0
                  [000000]    67  	OSF_P_MISC__IPL__M		= ^x7
                  [000000]    68  	OSF_P_MISC__CM__S		= 3
                  [000000]    69  	OSF_P_MISC__CM__M		= ^x1
                  [000000]    70  	OSF_P_MISC__RSV__S		= 4
                  [000000]    71  	OSF_P_MISC__RSV__M		= ^xFFF
                  [000000]    72  
                  [000000]    73  	OSF_P_MISC__PS__S		= 0
                  [000000]    74  	OSF_P_MISC__PS__M		= ^xF
                  [000000]    75  
                  [000000]    76  	OSF_P_MISC__MCES__MCHK__S	= 16
                  [000000]    77  	OSF_P_MISC__MCES__SCE__S	= 17
                  [000000]    78  	OSF_P_MISC__MCES__PCE__S	= 18
                  [000000]    79  	OSF_P_MISC__MCES__DPC__S	= 19
                  [000000]    80  	OSF_P_MISC__MCES__DSC__S	= 20
                  [000000]    81  	OSF_P_MISC__MCES__RSV__S	= 21
                  [000000]    82  	OSF_P_MISC__MCES__RSV__M	= ^x7
                  [000000]    83  
                  [000000]    84  	OSF_P_MISC__SCBV__S		= 24
                  [000000]    85  	OSF_P_MISC__SCBV__M		= ^xFFFF
                  [000000]    86  	OSF_P_MISC__MCHK_CODE__S	= 40
                  [000000]    87  	OSF_P_MISC__MCHK_CODE__M	= ^xFFFF
                  [000000]    88  
                  [000000]    89  	OSF_P_MISC__SWITCH__S		= 62
                  [000000]    90  	OSF_P_MISC__PHYS__S		= 63
                  [000000]    91  .endm	OSF_P_MISC_DEFS
                  [000000]    92  
                  [000000]    93  
                  [000000]    94  ;+
                  [000000]    95  ; OSF_PS definition
                  [000000]    96  ;-
                  [000000]    97  .macro	OSF_PS_DEFS
                  [000000]    98  	OSF_PS__IPL__S		= 0
                  [000000]    99  	OSF_PS__IPL__M		= ^x7
                  [000000]   100  	OSF_PS__CM__S		= 3
                  [000000]   101  	OSF_PS__CM__M		= ^x1
                  [000000]   102  .endm	OSF_PS_DEFS
                  [000000]   103  
                  [000000]   104  
                  [000000]   105  ;+
                  [000000]   106  ; PTE layout
                  [000000]   107  ;
                  [000000]   108  ;	Loc	Size	name 	function
                  [000000]   109  ;	------	------	------	-----------------------------------
                  [000000]   110  ;	<63:32>	32	PFN	Page Frame Number
                  [000000]   111  ;	<31:16>	16	SOFT	Bits reserved for software use
                  [000000]   112  ;	<13>	1	UWE	User write enable
                  [000000]   113  ;	<12>	1	KWE	Kernel write enable
                  [000000]   114  ;	<9>	1	URE	User read enable
                  [000000]   115  ;	<8>	1	KRE	Kernel read enable
                  [000000]   116  ;	<6:5>	2	GH	Granularity hint
                  [000000]   117  ;	<4>	1	ASM	Wild card address space number match
                  [000000]   118  ;	<3>	1	FOE	Fault On execute
                  [000000]   119  ;	<2>	1	FOW	Fault On Write
                  [000000]   120  ;	<1>	1	FOR	Fault On Read
                  [000000]   121  ; 	<0>	1	V	valid bit
                  [000000]   122  ;-
                  [000000]   123  
                  [000000]   124  .macro	OSF_PTE_DEFS
                  [000000]   125  	OSF_PTE__PFN__S	= 	32
                  [000000]   126  	OSF_PTE__PFN__M	= 	^xFFFFFFFF
                  [000000]   127  
                  [000000]   128  	OSF_PTE__SOFT__S	= 16
                  [000000]   129  	OSF_PTE__SOFT__M	= ^xFFFF
                  [000000]   130  
                  [000000]   131  	OSF_PTE__UWE__S		= 13
                  [000000]   132  	OSF_PTE__UWE__M		= ^x1
                  [000000]   133  	OSF_PTE__KWE__S		= 12
                  [000000]   134  	OSF_PTE__KWE__M		= ^x1
                  [000000]   135  
                  [000000]   136  	OSF_PTE__URE__S		= 9
                  [000000]   137  	OSF_PTE__URE__M		= ^x1
                  [000000]   138  	OSF_PTE__KRE__S		= 8
                  [000000]   139  	OSF_PTE__KRE__M		= ^x1
                  [000000]   140  
                  [000000]   141  	OSF_PTE__GH__S		= 5
                  [000000]   142  	OSF_PTE__GH__M		= ^x3
                  [000000]   143  
                  [000000]   144  	OSF_PTE__ASM__S		= 4
                  [000000]   145  	OSF_PTE__ASM__M		= ^x1
                  [000000]   146  	OSF_PTE__FOE__S		= 3
                  [000000]   147  	OSF_PTE__FOE__M		= ^x1
                  [000000]   148  	OSF_PTE__FOW__S		= 2
                  [000000]   149  	OSF_PTE__FOW__M		= ^x1
                  [000000]   150  	OSF_PTE__FOR__S		= 1
                  [000000]   151  	OSF_PTE__FOR__M		= ^x1
                  [000000]   152  
                  [000000]   153  	OSF_PTE__V__S		= 0
                  [000000]   154  	OSF_PTE__V__M		= ^x1
                  [000000]   155  
                  [000000]   156  	OSF_PTE__PROT__M	= ^x3300
                  [000000]   157  
                  [000000]   158  .endm	OSF_PTE_DEFS
                  [000000]   159  
                  [000000]   160  
                  [000000]   161  ;+
                  [000000]   162  ; SYSTEM CONTROL BLOCK (SCB)
                  [000000]   163  ;-
                  [000000]   164  .macro	OSF_SCB_DEFS
                  [000000]   165  	SCB__SYS_CORR_ERR	= ^x0620
                  [000000]   166  	SCB__PROC_CORR_ERR	= ^x0630
                  [000000]   167  	SCB__PWRFAIL		= ^x0640
                  [000000]   168  	SCB__PERFMON		= ^x0650
                  [000000]   169  	SCB__SYSMCHK		= ^x0660
                  [000000]   170  	SCB__PROCMCHK		= ^x0670
                  [000000]   171  	SCB__SYS_EVENT		= ^x0680
                  [000000]   172  	SCB__PASSIVE__REL	= ^x06F0
                  [000000]   173  .endm	OSF_SCB_DEFS
                  [000000]   174  
                  [000000]   175  
                  [000000]   176  ;+
                  [000000]   177  ; PRIVILEGED CONTEXT BLOCK (PCB)
                  [000000]   178  ;-
                  [000000]   179  .macro	OSF_PCB_DEFS
                  [000000]   180  	OSF_PCB__STACKS		=  0
                  [000000]   181  	OSF_PCB__KSP		=  0
                  [000000]   182  	OSF_PCB__USP		=  8
                  [000000]   183  	OSF_PCB__PTBR		= 16
                  [000000]   184  	OSF_PCB__CPC		= 24
                  [000000]   185  	OSF_PCB__ASN		= 28
                  [000000]   186  	OSF_PCB__UNQ		= 32
                  [000000]   187  	OSF_PCB__FEN		= 40
                  [000000]   188  	OSF_PCB__RSV		= 48
                  [000000]   189  
                  [000000]   190  	OSF_PCB__ASN__S		= 32
                  [000000]   191  	OSF_PCB__ASN__M		= ^xFF
                  [000000]   192  
                  [000000]   193  	OSF_PCB__FEN__S		= 0
                  [000000]   194  	OSF_PCB__FEN__M		= ^x1
                  [000000]   195  	OSF_PCB__PME__S		= 62
                  [000000]   196  	OSF_PCB__PME__M		= ^x1
                  [000000]   197  .endm	OSF_PCB_DEFS
                  [000000]   198  
                  [000000]   199  ;+
                  [000000]   200  ; Stack frame (FRM)
                  [000000]   201  ;-
                  [000000]   202  .macro	OSF_FRM_DEFS
                  [000000]   203  	OSF_FRM__PS		= ^x0000
                  [000000]   204  	OSF_FRM__PC		= ^x0008
                  [000000]   205  	OSF_FRM__GP		= ^x0010
                  [000000]   206  
                  [000000]   207  	OSF_FRM__A0		= ^x0018
                  [000000]   208  	OSF_FRM__R16		= ^x0018
                  [000000]   209  
                  [000000]   210  	OSF_FRM__A1		= ^x0020
                  [000000]   211  	OSF_FRM__R17		= ^x0020
                  [000000]   212  
                  [000000]   213  	OSF_FRM__A2		= ^x0028
                  [000000]   214  	OSF_FRM__R18		= ^x0028
                  [000000]   215  
                  [000000]   216  	OSF_FRM__SIZE		= ^x0030
                  [000000]   217  .endm	OSF_FRM_DEFS
                  [000000]   218  
                  [000000]   219  ;+
                  [000000]   220  ; OSF_A0_DEFS
                  [000000]   221  ;-
                  [000000]   222  .macro	OSF_A0_DEFS
                  [000000]   223  	OSF_A0__BPT		= ^x0
                  [000000]   224  	OSF_A0__BUGCHK		= ^x1
                  [000000]   225  	OSF_A0__GENTRAP		= ^x2
                  [000000]   226  	OSF_A0__FEN		= ^x3
                  [000000]   227  	OSF_A0__OPDEC		= ^x4
                  [000000]   228  	OSF_A0__ILLOP		= ^x5
                  [000000]   229  
                  [000000]   230  	OSF_A0_INT__IP		= ^x0
                  [000000]   231  	OSF_A0_INT__CLK		= ^x1
                  [000000]   232  	OSF_A0_INT__CRD		= ^x2
                  [000000]   233  	OSF_A0_INT__MCHK	= ^x2
                  [000000]   234  	OSF_A0_INT__DEV		= ^x3
                  [000000]   235  	OSF_A0_INT__PERFMON	= ^x4
                  [000000]   236  .endm	OSF_A0_DEFS
                  [000000]   237  
                  [000000]   238  ;+
                  [000000]   239  ; OSF_MMCSR_DEFS
                  [000000]   240  ;-
                  [000000]   241  .macro	OSF_MMCSR_DEFS
                  [000000]   242  	OSF_MMCSR__TNV		= ^x0
                  [000000]   243  	OSF_MMCSR__ACV		= ^x1
                  [000000]   244  	OSF_MMCSR__FOR		= ^x2
                  [000000]   245  	OSF_MMCSR__FOE		= ^x3
                  [000000]   246  	OSF_MMCSR__FOW		= ^x4
                  [000000]   247  .endm	OSF_MMCSR_DEFS
                  [000000]   248  	
                  [000000]   249  ;+
                  [000000]   250  ; OSF_IPL_DEFS
                  [000000]   251  ;-
                  [000000]   252  .macro	OSF_IPL_DEFS
                  [000000]   253  	OSF_IPL__IP		= ^x5
                  [000000]   254  	OSF_IPL__CLK		= ^x5
                  [000000]   255  	OSF_IPL__MCHK_CRD	= ^x7
                  [000000]   256  	OSF_IPL__MCHK		= ^x7
                  [000000]   257  	OSF_IPL__DEV3		= ^x3
                  [000000]   258  	OSF_IPL__DEV4		= ^x4
                  [000000]   259  	OSF_IPL__DEV5		= ^x5
                  [000000]   260  	OSF_IPL__DEV6		= ^x6
                  [000000]   261  	OSF_IPL__PERFMON	= ^x6
                  [000000]   262  .endm	OSF_IPL_DEFS
File: ev6_dbm_pal_defs.mar
                  [000000]     1  ;; Alpha assembly macro (-m) output created by DEFNR
                  [000000]     2  ;   
                  [000000]     3  ;  EV6_SYSTEM_PAL_DEFS.DNR  
                  [000000]     4  ;   
                  [000000]     5  ;   
                  [000000]     6  ;  LAST EDIT:	28-MAY-98  
                  [000000]     7  ;   
                  [000000]     8  ;  EDIT HISTORY  
                  [000000]     9  ;  WHO	WHEN		WHAT  
                  [000000]    10  ;  ---	----		----  
                  [000000]    11  ;  ES	09-JUL-97	ADD CSERVES  
                  [000000]    12  ;  ES	28-May-98	Change pal base and impure base
                  [000000]    13  ;   
                  [000000]    14  
                  [000000]    15  PAL__PAL_BASE = ^x08000	
                  [000000]    16  PAL__OSFPAL_BASE = ^x08000	
                  [000000]    17  PAL__CONSOLE_BASE = ^x10000	
                  [000000]    18  PAL__EMUL_BASE = ^xFFFFFFFF	
                  [000000]    19  PAL__IMPURE_BASE = ^x04000	
                  [000000]    20  PAL__IMPURE_COMMON_SIZE = ^x200	
                  [000000]    21  PAL__IMPURE_SPECIFIC_SIZE = ^x600	
                  [000000]    22  PAL__LOGOUT_BASE = ^x06000	
                  [000000]    23  PAL__LOGOUT_SPECIFIC_SIZE = ^x400	
                  [000000]    24  PAL__TEMPS_BASE = ^x07000	
                  [000000]    25  PAL__TEMPS_SPECIFIC_SIZE = ^x200	
                  [000000]    26  ; 
                  [000000]    27  ; DEFINE ADDRESSES OF LOCATIONS IN THE IMPURE 
                  [000000]    28  ; COMMON AREA. ASSUMES BASE AT 0XC000 AND LOCATIONS 
                  [000000]    29  ; STARTING AT 0X100. 
                  [000000]    30  ; 
                  [000000]    31  
                  [000000]    32  PAL__ENTER_OSF = ^x0c100	
                  [000000]    33  ;   
                  [000000]    34  ;  DEFINE DEVICE INTERRUPT IRQ(S) AS A MASK IN ISUM<EI> FIELD  
                  [000000]    35  ;   
                  [000000]    36  
                  [000000]    37  IRQ_DEV__M = ^x2	; IRQ1 
                  [000000]    38  ; 
                  [000000]    39  ; DEFINE CSERVE FUNCTIONS 
                  [000000]    40  ; 
                  [000000]    41  CSERVE__START = ^x1	
                  [000000]    42  CSERVE__CALLBACK = ^x2	
                  [000000]    43  ; 
                  [000000]    44  ; FOR DP264 DEBUG MONITOR 
                  [000000]    45  ; 
                  [000000]    46  CSERVE__JTOPAL = ^x9	
                  [000000]    47  CSERVE__RD_IMPURE = ^xb	
                  [000000]    48  CSERVE_K_SROM_INIT      = ^x18
                  [000000]    49  CSERVE_K_SROM_PUTC      = ^x19
                  [000000]    50  CSERVE_K_SROM_GETC      = ^x20
                  [000000]    51  
File: ev6_system_pal_impure.mar
                  [000000]     1  ;; Alpha assembly macro (-m) output created by DEFNR
                  [000000]     2  ;   
                  [000000]     3  ;  EV6_SYSTEM_PAL_IMPURE.DNR  
                  [000000]     4  ;   
                  [000000]     5  ;   
                  [000000]     6  ;  LAST EDIT:	18-MAY-98  
                  [000000]     7  ;   
                  [000000]     8  ;  EDIT HISTORY  
                  [000000]     9  ;  WHO	WHEN		WHAT  
                  [000000]    10  ;  ---	----		----  
                  [000000]    11  ;  ES	17-SEP-96	MOVED AROUND IMPURE LOCATIONS TO MATCH PREVIOUS  
                  [000000]    12  ; 				IMPLEMENTATIONS  
                  [000000]    13  ;  ES	17-OCT-96	RENAMED TO EV6_SYSTEM_PAL_IMPURE.DNR  
                  [000000]    14  ;  ES	21-NOV-96	CHANGED CBOX ERROR REGISTERS, DELETED THEM FROM CNS  
                  [000000]    15  ;  ES	08-APR-97	ELIMINATE CPU_BASE AND SYSTEM_BASE AND SIZE AS  
                  [000000]    16  ; 				AS LOCATIONS.  
                  [000000]    17  ; 				NOW NEED TO UPDATE THESE MANUALLY!  
                  [000000]    18  ;  ES	10-APR-97	CHANGED CBOX READ CHAIN NAMES.  
                  [000000]    19  ; 			ADDED PAL_BASE, I_CTL, PROCESS_CONTEXT TO MCHK.  
                  [000000]    20  ;  ES	09-APR-97	NEW LOGOUT FRAME ARRANGEMENT.  
                  [000000]    21  ;  ES	24-JUN-97	ELIMINATE VA AND VA_CTL. ADD MCHK REV'S. ADD/MOVE  
                  [000000]    22  ; 				AROUND RESERVED SPOTS.  
                  [000000]    23  ;  ES	15-AUG-97	ADDED SOME NAMES FOR DP264.  
                  [000000]    24  ;  ES	30-OCT-97	MOVE MM_STAT FROM LONG TO SHORT FRAME FOR  
                  [000000]    25  ; 				CORRECTED DC_TAG_PERR.  
                  [000000]    26  ;  ES	06-NOV-97	MOVE SROM PARAMETERS TO THE END OF THE IMPURE AREA  
                  [000000]    27  ;  ES	20-NOV-97	PUT SROM PARAMETERS BACK AT PLACEHOLDERS. ONLY DEBUG  
                  [000000]    28  ; 				MONITOR CARES. SRM PUTS IT WHERE IT WANTS  
                  [000000]    29  ; 				ANYWAY  
                  [000000]    30  ;  ES	18-MAY-98	ADD CNS__WRITE_MANY FOR SLEEP MODE.  
                  [000000]    31  ;   
                  [000000]    32  ;   
                  [000000]    33  ;  DEFINE CNS_SIZE  
                  [000000]    34  ;  THIS IS MANUALLY SET!  
                  [000000]    35  ;   
                  [000000]    36  
                  [000000]    37  CNS__SIZE = ^x3b0	
                  [000000]    38  ; 
                  [000000]    39  ; DEFINE PREFIX AS CNS 
                  [000000]    40  ; 
                  [000000]    41  ;   
                  [000000]    42  ;  DEFINE OFFSETS  
                  [000000]    43  ;   
                  [000000]    44  
                  [000000]    45  CNS__FLAG = ^x0	; DUMP FLAG 
                  [000000]    46  CNS__HALT = ^x8	; HALT CODE 
                  [000000]    47  CNS__R0 = ^x10	; INTEGER REGISTERS 
                  [000000]    48  CNS__R1 = ^x18	
                  [000000]    49  CNS__R2 = ^x20	
                  [000000]    50  CNS__R3 = ^x28	
                  [000000]    51  CNS__R4 = ^x30	
                  [000000]    52  CNS__R5 = ^x38	
                  [000000]    53  CNS__R6 = ^x40	
                  [000000]    54  CNS__R7 = ^x48	
                  [000000]    55  CNS__R8 = ^x50	
                  [000000]    56  CNS__R9 = ^x58	
                  [000000]    57  CNS__R10 = ^x60	
                  [000000]    58  CNS__R11 = ^x68	
                  [000000]    59  CNS__R12 = ^x70	
                  [000000]    60  CNS__R13 = ^x78	
                  [000000]    61  CNS__R14 = ^x80	
                  [000000]    62  CNS__R15 = ^x88	
                  [000000]    63  CNS__R16 = ^x90	
                  [000000]    64  CNS__R17 = ^x98	
                  [000000]    65  CNS__R18 = ^xa0	
                  [000000]    66  CNS__R19 = ^xa8	
                  [000000]    67  CNS__R20 = ^xb0	
                  [000000]    68  CNS__R21 = ^xb8	
                  [000000]    69  CNS__R22 = ^xc0	
                  [000000]    70  CNS__R23 = ^xc8	
                  [000000]    71  CNS__R24 = ^xd0	
                  [000000]    72  CNS__R25 = ^xd8	
                  [000000]    73  CNS__R26 = ^xe0	
                  [000000]    74  CNS__R27 = ^xe8	
                  [000000]    75  CNS__R28 = ^xf0	
                  [000000]    76  CNS__R29 = ^xf8	
                  [000000]    77  CNS__R30 = ^x100	
                  [000000]    78  CNS__R31 = ^x108	
                  [000000]    79  CNS__F0 = ^x110	; FLOATING POINT REGISTERS 
                  [000000]    80  CNS__F1 = ^x118	
                  [000000]    81  CNS__F2 = ^x120	
                  [000000]    82  CNS__F3 = ^x128	
                  [000000]    83  CNS__F4 = ^x130	
                  [000000]    84  CNS__F5 = ^x138	
                  [000000]    85  CNS__F6 = ^x140	
                  [000000]    86  CNS__F7 = ^x148	
                  [000000]    87  CNS__F8 = ^x150	
                  [000000]    88  CNS__F9 = ^x158	
                  [000000]    89  CNS__F10 = ^x160	
                  [000000]    90  CNS__F11 = ^x168	
                  [000000]    91  CNS__F12 = ^x170	
                  [000000]    92  CNS__F13 = ^x178	
                  [000000]    93  CNS__F14 = ^x180	
                  [000000]    94  CNS__F15 = ^x188	
                  [000000]    95  CNS__F16 = ^x190	
                  [000000]    96  CNS__F17 = ^x198	
                  [000000]    97  CNS__F18 = ^x1a0	
                  [000000]    98  CNS__F19 = ^x1a8	
                  [000000]    99  CNS__F20 = ^x1b0	
                  [000000]   100  CNS__F21 = ^x1b8	
                  [000000]   101  CNS__F22 = ^x1c0	
                  [000000]   102  CNS__F23 = ^x1c8	
                  [000000]   103  CNS__F24 = ^x1d0	
                  [000000]   104  CNS__F25 = ^x1d8	
                  [000000]   105  CNS__F26 = ^x1e0	
                  [000000]   106  CNS__F27 = ^x1e8	
                  [000000]   107  CNS__F28 = ^x1f0	
                  [000000]   108  CNS__F29 = ^x1f8	
                  [000000]   109  CNS__F30 = ^x200	
                  [000000]   110  CNS__F31 = ^x208	
                  [000000]   111  CNS__MCHKFLAG = ^x210	; DOES ANYONE USE THIS????? 
                  [000000]   112  CNS__IMPURE = ^x218	; IMPORTANT PALTEMPS 
                  [000000]   113  CNS__WHAMI = ^x220	
                  [000000]   114  CNS__SCC = ^x228	
                  [000000]   115  CNS__PRBR = ^x230	
                  [000000]   116  CNS__PTBR = ^x238	
                  [000000]   117  CNS__TRAP = ^x240	
                  [000000]   118  CNS__HALT_CODE = ^x248	
                  [000000]   119  CNS__KSP = ^x250	
                  [000000]   120  CNS__SCBB = ^x258	
                  [000000]   121  CNS__PCBB = ^x260	
                  [000000]   122  CNS__VPTB = ^x268	
                  [000000]   123  CNS__SROM_REV = ^x270	; DP264 DEBUG MONITOR 
                  [000000]   124  CNS__PROC_ID = ^x278	; DP264 
                  [000000]   125  CNS__MEM_SIZE = ^x280	; DP264 
                  [000000]   126  CNS__CYCLE_CNT = ^x288	; DP264 
                  [000000]   127  CNS__SIGNATURE = ^x290	; DP264 
                  [000000]   128  CNS__PROC_MASK = ^x298	; DP264 
                  [000000]   129  CNS__SYSCTX = ^x2a0	; DP264 
                  [000000]   130  CNS__PLACE_HOLDER18 = ^x2a8	
                  [000000]   131  CNS__PLACE_HOLDER19 = ^x2b0	
                  [000000]   132  CNS__PLACE_HOLDER20 = ^x2b8	
                  [000000]   133  CNS__PLACE_HOLDER21 = ^x2c0	
                  [000000]   134  CNS__PLACE_HOLDER22 = ^x2c8	
                  [000000]   135  CNS__PLACE_HOLDER23 = ^x2d0	
                  [000000]   136  CNS__P4 = ^x2d8	; SHADOW REGISTERS 
                  [000000]   137  CNS__P5 = ^x2e0	
                  [000000]   138  CNS__P6 = ^x2e8	
                  [000000]   139  CNS__P7 = ^x2f0	
                  [000000]   140  CNS__P20 = ^x2f8	
                  [000000]   141  CNS__P_TEMP = ^x300	
                  [000000]   142  CNS__P_MISC = ^x308	
                  [000000]   143  CNS__P23 = ^x310	
                  [000000]   144  CNS__FPCR = ^x318	; IPRS 
                  [000000]   145  CNS__VA = ^x320	
                  [000000]   146  CNS__VA_CTL = ^x328	
                  [000000]   147  CNS__EXC_ADDR = ^x330	
                  [000000]   148  CNS__IER_CM = ^x338	
                  [000000]   149  CNS__SIRR = ^x340	
                  [000000]   150  CNS__ISUM = ^x348	
                  [000000]   151  CNS__EXC_SUM = ^x350	
                  [000000]   152  CNS__PAL_BASE = ^x358	
                  [000000]   153  CNS__I_CTL = ^x360	
                  [000000]   154  CNS__PCTR_CTL = ^x368	
                  [000000]   155  CNS__PROCESS_CONTEXT = ^x370	
                  [000000]   156  CNS__I_STAT = ^x378	
                  [000000]   157  CNS__DTB_ALT_MODE = ^x380	
                  [000000]   158  CNS__MM_STAT = ^x388	
                  [000000]   159  CNS__M_CTL = ^x390	
                  [000000]   160  CNS__DC_CTL = ^x398	
                  [000000]   161  CNS__DC_STAT = ^x3a0	
                  [000000]   162  CNS__WRITE_MANY = ^x3a8	
                  [000000]   163  ;   
                  [000000]   164  ;  DEFINE MCHK_CRD__BASE, MCHK_CRD_CPU_BASE,  
                  [000000]   165  ;  		MCHK_CRD__SYSTEM_BASE, AND MCHK_CRD__SIZE  
                  [000000]   166  ;  THESE ARE MANUALLY SET!  
                  [000000]   167  ;  ALSO HAVE REVISION NUMBER.  
                  [000000]   168  ;   
                  [000000]   169  
                  [000000]   170  MCHK_CRD__REV = ^x1	
                  [000000]   171  MCHK_CRD__BASE = ^x0	
                  [000000]   172  MCHK_CRD__CPU_BASE = ^x18	
                  [000000]   173  MCHK_CRD__SYSTEM_BASE = ^x58	
                  [000000]   174  MCHK_CRD__SIZE = ^x58	
                  [000000]   175  ; 
                  [000000]   176  ; DEFINE PREFIX AS MCHK_CRD 
                  [000000]   177  ; 
                  [000000]   178  ;   
                  [000000]   179  ;  DEFINE MCHK_CRD OFFSETS  
                  [000000]   180  ;   
                  [000000]   181  
                  [000000]   182  MCHK_CRD__FLAG_FRAME = ^x0	
                  [000000]   183  MCHK_CRD__OFFSETS = ^x8	
                  [000000]   184  MCHK_CRD__MCHK_CODE = ^x10	; START OF PAL SPECIFIC 
                  [000000]   185  MCHK_CRD__I_STAT = ^x18	; START OF CPU SPECIFIC 
                  [000000]   186  MCHK_CRD__DC_STAT = ^x20	
                  [000000]   187  MCHK_CRD__C_ADDR = ^x28	
                  [000000]   188  MCHK_CRD__DC1_SYNDROME = ^x30	
                  [000000]   189  MCHK_CRD__DC0_SYNDROME = ^x38	
                  [000000]   190  MCHK_CRD__C_STAT = ^x40	
                  [000000]   191  MCHK_CRD__C_STS = ^x48	
                  [000000]   192  MCHK_CRD__MM_STAT = ^x50	
                  [000000]   193  ;   
                  [000000]   194  ;  DEFINE MCHK__BASE, MCHK__CPU_BASE, MCHK__SYSTEM_BASE, MCHK__SIZE  
                  [000000]   195  ;  THESE ARE MANUALLY SET!  
                  [000000]   196  ;  ALSO HAVE REVISION NUMBER.  
                  [000000]   197  ;   
                  [000000]   198  
                  [000000]   199  MCHK__REV = ^x1	
                  [000000]   200  MCHK__BASE = ^x100	
                  [000000]   201  MCHK__CPU_BASE = ^x18	
                  [000000]   202  MCHK__SYSTEM_BASE = ^xa0	
                  [000000]   203  MCHK__SIZE = ^xa0	
                  [000000]   204  ; 
                  [000000]   205  ; DEFINE PREFIX AS MCHK 
                  [000000]   206  ; 
                  [000000]   207  ;   
                  [000000]   208  ;  DEFINE MCHK OFFSETS  
                  [000000]   209  ;   
                  [000000]   210  
                  [000000]   211  MCHK__FLAG_FRAME = ^x0	
                  [000000]   212  MCHK__OFFSETS = ^x8	
                  [000000]   213  MCHK__MCHK_CODE = ^x10	; START OF PAL SPECIFIC 
                  [000000]   214  MCHK__I_STAT = ^x18	; START OF CPU SPECIFIC COMMON 
                  [000000]   215  MCHK__DC_STAT = ^x20	
                  [000000]   216  MCHK__C_ADDR = ^x28	
                  [000000]   217  MCHK__DC1_SYNDROME = ^x30	
                  [000000]   218  MCHK__DC0_SYNDROME = ^x38	
                  [000000]   219  MCHK__C_STAT = ^x40	
                  [000000]   220  MCHK__C_STS = ^x48	
                  [000000]   221  MCHK__MM_STAT = ^x50	
                  [000000]   222  MCHK__EXC_ADDR = ^x58	; START OF CPU SPECIFIC, MCHK ONLY 
                  [000000]   223  MCHK__IER_CM = ^x60	
                  [000000]   224  MCHK__ISUM = ^x68	
                  [000000]   225  MCHK__RESERVED_0 = ^x70	
                  [000000]   226  MCHK__PAL_BASE = ^x78	
                  [000000]   227  MCHK__I_CTL = ^x80	
                  [000000]   228  MCHK__PROCESS_CONTEXT = ^x88	
                  [000000]   229  MCHK__RESERVED_1 = ^x90	
                  [000000]   230  MCHK__RESERVED_2 = ^x98	
                  [000000]   231  
File: ev6_pal_macros.mar
                  [000000]     1  ;+
                  [000000]     2  ; ev6_pal_macros.mar
                  [000000]     3  ;-
                  [000000]     4  
                  [000000]     5  ;+
                  [000000]     6  ; Last Edit:	12-Jan-99
                  [000000]     7  ;
                  [000000]     8  ; Edit History
                  [000000]     9  ; Who	When		What
                  [000000]    10  ; ---	----		----
                  [000000]    11  ; ES	17-Sep-96	Fixed PVC_VIOLATE macro.
                  [000000]    12  ; ES	18-Dec-96	Added optional pad to align macros.
                  [000000]    13  ;			Added ASSUME_FETCH_BLOCK.
                  [000000]    14  ;			Added MAP_SHADOW_REGISTERS
                  [000000]    15  ; ES	06-Mar-97	Add unaligned LOAD macros (for pass1 fp emulation)
                  [000000]    16  ; ES	01-Aug-97	Add optional 'verify' parameter to GET_32CONS
                  [000000]    17  ;				(suggested by Dave Mayo)
                  [000000]    18  ; ES	29-Sep-97	Eliminate MAP_SHADOW_REGISTERS. You can find it
                  [000000]    19  ;				in srom_macros.mar.
                  [000000]    20  ; ES	11-Jan-99	Add add_extra_ret conditional in CALL_PAL macro,
                  [000000]    21  ;				in case we ever want to use it.
                  [000000]    22  ;-
                  [000000]    23  
                  [000000]    24  ;
                  [000000]    25  ; On p2.3 (and maybe later), call_pal pushes the prediction stack
                  [000000]    26  ; twice, so we might want to pop it an extra time. This causes a
                  [000000]    27  ; mispredict, but the stack is back in synch. If the stack never
                  [000000]    28  ; gets deep, the mispredict hit is not worth it. So right
                  [000000]    29  ; now, we leave it around but turned off. It appears that it
                  [000000]    30  ; the right choice.
                  [000000]    31  ;
                  [000000]    32  .iif ndf add_extra_ret, add_extra_ret = 0
                  [000000]    32I  add_extra_ret = 0
                  [000000]    33  
                  [000000]    34  .macro	START_HW_VECTOR func
                  [000000]    35      .iif ndf _pal_func_in_prog, _pal_func_in_prog = 0
                  [000000]    36      ASSUME <_pal_func_in_prog> eq 0
                  [000000]    37      _pal_func_in_prog = 1
                  [000000]    38      .if ndf _new_code_space
                  [000000]    39          _new_code_space = ^x4000
                  [000000]    40      .iff
                  [000000]    41          _new_code_space = .
                  [000000]    42      .endc
                  [000000]    43      _pal_vec_cont = 0
                  [000000]    44      .if ndf osfpal
                  [000000]    45          . = <TRAP__START + EV6__'func'_ENTRY>
                  [000000]    46  TRAP__'func':
                  [000000]    47      .iff
                  [000000]    48          . = <TRAP__START + EV6__'func'_ENTRY>
                  [000000]    49  TRAP__'func':
                  [000000]    50      .endc
                  [000000]    51      _start_of_last_vec = .
                  [000000]    52  .endm	START_HW_VECTOR
                  [000000]    53  
                  [000000]    54  .macro	END_HW_VECTOR size=^x80
                  [000000]    55      _pal_func_in_prog = 0
                  [000000]    56      .if eq _pal_vec_cont
                  [000000]    57          ASSUME <.-_start_of_last_vec> le <size>
                  [000000]    58      .iff
                  [000000]    59          _new_code_space = .
                  [000000]    60      .endc
                  [000000]    61      GOTO_FREE_CODE
                  [000000]    62  .endm	END_HW_VECTOR
                  [000000]    63  
                  [000000]    64  .macro	GOTO_FREE_CODE
                  [000000]    65      .iif ndf _new_code_space, _new_code_space = ^x4000
                  [000000]    66      . = _new_code_space
                  [000000]    67      .align 6
                  [000000]    68  .endm	GOTO_FREE_CODE
                  [000000]    69  
                  [000000]    70  .macro	END_FREE_CODE
                  [000000]    71      .iif ndf _new_code_space, _new_code_space = ^x4000
                  [000000]    72      _new_code_space = .
                  [000000]    73  .endm	END_FREE_CODE
                  [000000]    74  
                  [000000]    75  .macro	CONT_HW_VECTOR func
                  [000000]    76      ASSUME <_pal_vec_cont> eq 0
                  [000000]    77      .if nb func
                  [000000]    78          .if ndf osfpal
                  [000000]    79  	br	r31, TRAP__'func'_CONT
                  [000000]    80          .iff
                  [000000]    81  	br	r31, TRAP__'func'_CONT
                  [000000]    82          .endc
                  [000000]    83      .endc
                  [000000]    84      ASSUME <.-_start_of_last_vec> le <^x80>
                  [000000]    85      _pal_vec_cont = 1
                  [000000]    86      GOTO_FREE_CODE
                  [000000]    87      .if nb func
                  [000000]    88          .if ndf osfpal
                  [000000]    89  TRAP__'func'_CONT:
                  [000000]    90          .iff
                  [000000]    91  TRAP__'func'_CONT:
                  [000000]    92          .endc
                  [000000]    93      .endc
                  [000000]    94  .endm	CONT_HW_VECTOR
                  [000000]    95  
                  [000000]    96  .if eq add_extra_ret				; add_extra_ret
                  [000000]    97  .macro	START_CALL_PAL func
                  [000000]    98      .if ndf osfpal
                  [000000]    99          ASSUME <<PAL_FUNC__'func'> & <^x40>> eq 0
                  [000000]   100          new_func_code = -
                  [000000]   101              <PAL_FUNC__'func' & ^x3F> -
                  [000000]   102  	        ! <<PAL_FUNC__'func'@-1>& ^x40>
                  [000000]   103      .iff
                  [000000]   104          ASSUME <<OSFPAL_FUNC__'func'> & <^x40>> eq 0
                  [000000]   105          new_func_code = -
                  [000000]   106              <OSFPAL_FUNC__'func' & ^x3F> -
                  [000000]   107                  ! <<OSFPAL_FUNC__'func'@-1>& ^x40>
                  [000000]   108      .endc
                  [000000]   109  
                  [000000]   110      .iif ndf _pal_func_in_prog, _pal_func_in_prog = 0
                  [000000]   111      ASSUME <_pal_func_in_prog> eq 0
                  [000000]   112      _pal_func_in_prog = 1
                  [000000]   113      _new_code_space = .
                  [000000]   114      _pal_func_cont = 0
                  [000000]   115      .if ndf osfpal
                  [000000]   116          . = <<CALL_PAL__START> + <new_func_code * <^x40>>>
                  [000000]   117  CALL_PAL__'func'::
                  [000000]   118      .iff
                  [000000]   119          . = <<CALL_PAL__START> + <new_func_code * <^x40>>>
                  [000000]   120  CALL_PAL__'func'::
                  [000000]   121      .endc
                  [000000]   122      _start_of_last_pal_func = .
                  [000000]   123  .endm	START_CALL_PAL
                  [000000]   124  .iff						; add_extra_ret
                  [000000]   125  ;
                  [000000]   126  ; Add 2 fetch blocks worth of hw_ret stuff, and then put in the
                  [000000]   127  ; equivalent of CONT_CALL_PAL.
                  [000000]   128  ;
                  [000000]   129  .macro	START_CALL_PAL func
                  [000000]   130      .if ndf osfpal
                  [000000]   131          ASSUME <<PAL_FUNC__'func'> & <^x40>> eq 0
                  [000000]   132          new_func_code = -
                  [000000]   133              <PAL_FUNC__'func' & ^x3F> -
                  [000000]   134  	        ! <<PAL_FUNC__'func'@-1>& ^x40>
                  [000000]   135      .iff
                  [000000]   136          ASSUME <<OSFPAL_FUNC__'func'> & <^x40>> eq 0
                  [000000]   137          new_func_code = -
                  [000000]   138              <OSFPAL_FUNC__'func' & ^x3F> -
                  [000000]   139                  ! <<OSFPAL_FUNC__'func'@-1>& ^x40>
                  [000000]   140      .endc
                  [000000]   141  
                  [000000]   142      .iif ndf _pal_func_in_prog, _pal_func_in_prog = 0
                  [000000]   143      ASSUME <_pal_func_in_prog> eq 0
                  [000000]   144      _pal_func_in_prog = 1
                  [000000]   145      _new_code_space = .
                  [000000]   146      _pal_func_cont = 0
                  [000000]   147          . = <<CALL_PAL__START> + <new_func_code * <^x40>>>
                  [000000]   148  CALL_PAL__'func'::
                  [000000]   149  	_start_of_last_pal_func = .
                  [000000]   150  	bis	r31, r31, r31
                  [000000]   151  	bis	r31, r31, r31
                  [000000]   152  	br	p4, s_'func'
                  [000000]   153  s_'func':
                  [000000]   154  	addq	p4, #<<e_'func' - s_'func'>+1>, p4
                  [000000]   155  	PVC_JSR	p_'func'
                  [000000]   156  	hw_ret	(p4)
                  [000000]   157  	PVC_JSR p_'func', dest=1
                  [000000]   158  e_'func':
                  [000000]   159  	bis	r31, r31, r31
                  [000000]   160  	bis	r31, r31, r31
                  [000000]   161  	br	r31, CALL_PAL__'func'_CONT_EXTRA
                  [000000]   162  
                  [000000]   163      _pal_func_cont = 1
                  [000000]   164      GOTO_FREE_CODE
                  [000000]   165  CALL_PAL__'func'_CONT_EXTRA:
                  [000000]   166  .endm	START_CALL_PAL
                  [000000]   167  .endc						; add_extra_ret
                  [000000]    97I .macro	START_CALL_PAL func
                  [000000]    98I     .if ndf osfpal
                  [000000]    99I         ASSUME <<PAL_FUNC__'func'> & <^x40>> eq 0
                  [000000]   100I         new_func_code = -
                  [000000]   101I             <PAL_FUNC__'func' & ^x3F> -
                  [000000]   102I 	        ! <<PAL_FUNC__'func'@-1>& ^x40>
                  [000000]   103I     .iff
                  [000000]   104I         ASSUME <<OSFPAL_FUNC__'func'> & <^x40>> eq 0
                  [000000]   105I         new_func_code = -
                  [000000]   106I             <OSFPAL_FUNC__'func' & ^x3F> -
                  [000000]   107I                 ! <<OSFPAL_FUNC__'func'@-1>& ^x40>
                  [000000]   108I     .endc
                  [000000]   109I 
                  [000000]   110I     .iif ndf _pal_func_in_prog, _pal_func_in_prog = 0
                  [000000]   111I     ASSUME <_pal_func_in_prog> eq 0
                  [000000]   112I     _pal_func_in_prog = 1
                  [000000]   113I     _new_code_space = .
                  [000000]   114I     _pal_func_cont = 0
                  [000000]   115I     .if ndf osfpal
                  [000000]   116I         . = <<CALL_PAL__START> + <new_func_code * <^x40>>>
                  [000000]   117I CALL_PAL__'func'::
                  [000000]   118I     .iff
                  [000000]   119I         . = <<CALL_PAL__START> + <new_func_code * <^x40>>>
                  [000000]   120I CALL_PAL__'func'::
                  [000000]   121I     .endc
                  [000000]   122I     _start_of_last_pal_func = .
                  [000000]   123I .endm	START_CALL_PAL
                  [000000]   168  
                  [000000]   169  .macro	END_CALL_PAL
                  [000000]   170      _pal_func_in_prog = 0
                  [000000]   171      .if eq _pal_func_cont
                  [000000]   172          ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [000000]   173      .iff
                  [000000]   174  	_new_code_space = .
                  [000000]   175      .endc
                  [000000]   176      GOTO_FREE_CODE
                  [000000]   177  .endm	END_CALL_PAL
                  [000000]   178  
                  [000000]   179  .if eq add_extra_ret				; add_extra_ret
                  [000000]   180  .macro	CONT_CALL_PAL func
                  [000000]   181      ASSUME <_pal_func_cont> eq 0
                  [000000]   182      .if nb func
                  [000000]   183          .if ndf osfpal
                  [000000]   184  	br	r31, CALL_PAL__'func'_CONT
                  [000000]   185          .iff
                  [000000]   186  	br	r31, CALL_PAL__'func'_CONT
                  [000000]   187          .endc
                  [000000]   188      .endc
                  [000000]   189      ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [000000]   190      _pal_func_cont = 1
                  [000000]   191      GOTO_FREE_CODE
                  [000000]   192      .if nb func
                  [000000]   193          .if ndf osfpal
                  [000000]   194  CALL_PAL__'func'_CONT:
                  [000000]   195          .iff
                  [000000]   196  CALL_PAL__'func'_CONT:
                  [000000]   197          .endc
                  [000000]   198      .endc
                  [000000]   199  .endm	CONT_CALL_PAL
                  [000000]   200  .iff						; add_extra_ret
                  [000000]   201  ;
                  [000000]   202  ; Basically just turn this into a branch to the next fetch block
                  [000000]   203  ;
                  [000000]   204  .macro	CONT_CALL_PAL func
                  [000000]   205      .if nb func
                  [000000]   206  	br	r31, CALL_PAL__'func'_CONT
                  [000000]   207      .endc
                  [000000]   208      .if nb func
                  [000000]   209      .align 4, <^x47FF041F>
                  [000000]   210  CALL_PAL__'func'_CONT:
                  [000000]   211      .endc
                  [000000]   212  .endm	CONT_CALL_PAL
                  [000000]   213  .endc						; add_extra_ret
                  [000000]   180I .macro	CONT_CALL_PAL func
                  [000000]   181I     ASSUME <_pal_func_cont> eq 0
                  [000000]   182I     .if nb func
                  [000000]   183I         .if ndf osfpal
                  [000000]   184I 	br	r31, CALL_PAL__'func'_CONT
                  [000000]   185I         .iff
                  [000000]   186I 	br	r31, CALL_PAL__'func'_CONT
                  [000000]   187I         .endc
                  [000000]   188I     .endc
                  [000000]   189I     ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [000000]   190I     _pal_func_cont = 1
                  [000000]   191I     GOTO_FREE_CODE
                  [000000]   192I     .if nb func
                  [000000]   193I         .if ndf osfpal
                  [000000]   194I CALL_PAL__'func'_CONT:
                  [000000]   195I         .iff
                  [000000]   196I CALL_PAL__'func'_CONT:
                  [000000]   197I         .endc
                  [000000]   198I     .endc
                  [000000]   199I .endm	CONT_CALL_PAL
                  [000000]   214  
                  [000000]   215  ;
                  [000000]   216  ; GET_32ADDR	load register 'dest' with 'offset(base)' where
                  [000000]   217  ;		offset can be a 32 bit literal
                  [000000]   218  ;
                  [000000]   219  .macro	GET_32ADDR dest,offset,base
                  [000000]   220  	ASSUME <offset> le  <^x7FFFFFFF>
                  [000000]   221  	ldah	'dest',<<'offset'>+32768>@-16('base'); + xxx<31:16>
                  [000000]   222  	lda	'dest',<<'offset'> & ^xFFFF>('dest') ; base+xxx<15:0>
                  [000000]   223  .endm	GET_32ADDR
                  [000000]   224  
                  [000000]   225  ;
                  [000000]   226  ; GET_16ADDR	load register 'dest' with 'offset(base)' where
                  [000000]   227  ;		offset can be a 16 bit literal
                  [000000]   228  ;
                  [000000]   229  .macro	GET_16ADDR dest,offset,base
                  [000000]   230  	ASSUME <<offset>> le  <^x7FFF>
                  [000000]   231  	lda	'dest',<'offset'>('base') ; base+xxx<15:0>
                  [000000]   232  .endm	GET_16ADDR
                  [000000]   233  
                  [000000]   234  ;
                  [000000]   235  ; GET_32CONS	load register 'dest' with 'offset(base)' where
                  [000000]   236  ;		offset can be a 32 bit literal
                  [000000]   237  ;
                  [000000]   238  .macro	GET_32CONS dest,offset,base,verify=1
                  [000000]   239  	.iif ne verify, ASSUME <offset> le  <^x7FFFFFFF>
                  [000000]   240  	ldah	'dest',<<'offset'>+32768>@-16('base'); + xxx<31:16>
                  [000000]   241  	lda	'dest',<<'offset'> & ^XFFFF>('dest') ; base+xxx<15:0>
                  [000000]   242  .endm	GET_32CONS
                  [000000]   243  
                  [000000]   244  ;
                  [000000]   245  ; GET_16CONS	load register 'dest' with 'offset(base)' where
                  [000000]   246  ;		offset can be a 16 bit literal
                  [000000]   247  ;
                  [000000]   248  .macro	GET_16CONS dest,offset,base
                  [000000]   249  	ASSUME <<offset>> le  <^x7FFF>
                  [000000]   250  	lda	'dest',<'offset'>('base') ; base+xxx<15:0>
                  [000000]   251  .endm	GET_16CONS
                  [000000]   252  
                  [000000]   253  ;
                  [000000]   254  ; ASSUME	test that a relation is true
                  [000000]   255  ;
                  [000000]   256  .macro	ASSUME exp1, relation, exp2
                  [000000]   257      .if	relation <<exp1>-<exp2>>
                  [000000]   258      .iff
                  [000000]   259          .error	; ** exp1 must be relation exp2 **
                  [000000]   260      .endc
                  [000000]   261  .endm	ASSUME
                  [000000]   262  
                  [000000]   263  .macro	ALIGN_FETCH_BLOCK pad
                  [000000]   264      .if nb <pad>
                  [000000]   265  	.align 4, <pad>
                  [000000]   266      .iff
                  [000000]   267  	.align 4
                  [000000]   268      .endc
                  [000000]   269  .endm	ALIGN_FETCH_BLOCK
                  [000000]   270  
                  [000000]   271  .macro	ALIGN_CACHE_BLOCK pad
                  [000000]   272      .if nb <pad>
                  [000000]   273  	.align 6, <pad>
                  [000000]   274      .iff
                  [000000]   275  	.align 6
                  [000000]   276      .endc
                  [000000]   277  .endm	ALIGN_CACHE_BLOCK
                  [000000]   278  
                  [000000]   279  ;
                  [000000]   280  ; NOP
                  [000000]   281  ;
                  [000000]   282  .macro	NOP
                  [000000]   283  	bis	r31, r31, r31
                  [000000]   284  .endm
                  [000000]   285  
                  [000000]   286  ;+
                  [000000]   287  ; ASSUME_FETCH_BLOCK
                  [000000]   288  ;-
                  [000000]   289  
                  [000000]   290  .macro	ASSUME_FETCH_BLOCK
                  [000000]   291  
                  [000000]   292      .if ne <.  & ^xF>
                  [000000]   293  	.error	; ** not aligned on fetch block **
                  [000000]   294      .endc
                  [000000]   295  .endm	ASSUME_FETCH_BLOCK
                  [000000]   296  
                  [000000]   297  .macro	LOAD_UNALIGNED_LONG reg, addr, scr1, scr2
                  [000000]   298  	lda	scr2, (addr)
                  [000000]   299  
                  [000000]   300  	ldq_u	reg, (scr2)
                  [000000]   301  	ldq_u	scr1, 3(scr2)
                  [000000]   302  	extll	reg, scr2, reg
                  [000000]   303  	extlh	scr1, scr2, scr1
                  [000000]   304  	or	scr1, reg, reg
                  [000000]   305  	addl	reg, r31, reg
                  [000000]   306  .endm
                  [000000]   307  
                  [000000]   308  .macro	LOAD_UNALIGNED_QUAD reg, addr, scr1, scr2
                  [000000]   309  	lda	scr2, (addr)
                  [000000]   310  	ldq_u	reg, (scr2)
                  [000000]   311  	ldq_u	scr1, 7(scr2)
                  [000000]   312  	extql	reg, scr2, reg
                  [000000]   313  	extqh	scr1, scr2, scr1
                  [000000]   314  	or	scr1, reg, reg
                  [000000]   315  .endm
                  [000000]   316  
                  [000000]   317  .macro	STORE_UNALIGNED_WORD reg, addr, scr1, scr2, scr3, lock=0, err,err1
                  [000000]   318      .if eq lock
                  [000000]   319  	lda	scr3, (addr)
                  [000000]   320  
                  [000000]   321  	ldq_u	scr1, (scr3)
                  [000000]   322  	inswl	reg, scr3, scr2
                  [000000]   323  	mskwl	scr1, scr3, scr1
                  [000000]   324  	bis	scr1, scr2, scr1
                  [000000]   325  	stq_u	scr1, (scr3)
                  [000000]   326  
                  [000000]   327  	ldq_u	scr1, 1(scr3)
                  [000000]   328  	inswh	reg, scr3, scr2
                  [000000]   329  	mskwh	scr1, scr3, scr1
                  [000000]   330  	bis	scr1, scr2, scr1
                  [000000]   331  	stq_u	scr1, 1(scr3)
                  [000000]   332  
                  [000000]   333      .iff
                  [000000]   334  
                  [000000]   335  	bic	addr, #7, scr3
                  [000000]   336  	ldq_l	scr1, (scr3)
                  [000000]   337  	inswl	reg, addr, scr2
                  [000000]   338  	mskwl	scr1, addr, scr1
                  [000000]   339  	bis	scr1, scr2, scr1
                  [000000]   340  	stq_c	scr1, (scr3)
                  [000000]   341  
                  [000000]   342  	.iif nb <err>, blbc scr1, err
                  [000000]   343  
                  [000000]   344  	lda	scr3, 1(addr)
                  [000000]   345  
                  [000000]   346  	bic	scr3, #7, scr3
                  [000000]   347  	ldq_l	scr1, (scr3)
                  [000000]   348  	inswh	reg, addr, scr2
                  [000000]   349  	mskwh	scr1, addr, scr1
                  [000000]   350  	bis	scr1, scr2, scr1
                  [000000]   351  	stq_c	scr1, (scr3)
                  [000000]   352  
                  [000000]   353  	.iif nb <err>, blbc scr1, err1
                  [000000]   354  
                  [000000]   355      .endc
                  [000000]   356  .endm
                  [000000]   357  
                  [000000]   358  .macro	STORE_UNALIGNED_LONG reg, addr, scr1, scr2, scr3, lock=0, err,err1
                  [000000]   359       .if eq lock
                  [000000]   360  	lda	scr3, (addr)
                  [000000]   361  
                  [000000]   362  	ldq_u	scr1, (scr3)
                  [000000]   363  	insll	reg, scr3, scr2
                  [000000]   364  	mskll	scr1, scr3, scr1
                  [000000]   365  	bis	scr1, scr2, scr1
                  [000000]   366  	stq_u	scr1, (scr3)
                  [000000]   367  
                  [000000]   368  	ldq_u	scr1, 3(scr3)
                  [000000]   369  	inslh	reg, scr3, scr2
                  [000000]   370  	msklh	scr1, scr3, scr1
                  [000000]   371  	bis	scr1, scr2, scr1
                  [000000]   372  	stq_u	scr1, 3(scr3)
                  [000000]   373  
                  [000000]   374      .iff
                  [000000]   375  
                  [000000]   376  	bic	addr, #7, scr3
                  [000000]   377  	ldq_l	scr1, (scr3)
                  [000000]   378  	insll	reg, addr, scr2
                  [000000]   379  	mskll	scr1, addr, scr1
                  [000000]   380  	bis	scr1, scr2, scr1
                  [000000]   381  	stq_c	scr1, (scr3)
                  [000000]   382  
                  [000000]   383  	.iif nb <err>, blbc scr1, err
                  [000000]   384  
                  [000000]   385  	lda	scr3, 3(addr)
                  [000000]   386  
                  [000000]   387  	bic	scr3, #7, scr3
                  [000000]   388  	ldq_l	scr1, (scr3)
                  [000000]   389  	inslh	reg, addr, scr2
                  [000000]   390  	msklh	scr1, addr, scr1
                  [000000]   391  	bis	scr1, scr2, scr1
                  [000000]   392  	stq_c	scr1, (scr3)
                  [000000]   393  
                  [000000]   394  	.iif nb <err>, blbc scr1, err1
                  [000000]   395      .endc
                  [000000]   396  .endm
                  [000000]   397  
                  [000000]   398  .macro	STORE_UNALIGNED_QUAD reg, addr, scr1, scr2, scr3, lock=0, err,err1
                  [000000]   399      .if eq lock
                  [000000]   400  	lda	scr3, (addr)
                  [000000]   401  
                  [000000]   402  	ldq_u	scr1, (scr3)
                  [000000]   403  	insql	reg, scr3, scr2
                  [000000]   404  	mskql	scr1, scr3, scr1
                  [000000]   405  	bis	scr1, scr2, scr1
                  [000000]   406  	stq_u	scr1, (scr3)
                  [000000]   407  
                  [000000]   408  	ldq_u	scr1, 7(scr3)
                  [000000]   409  	insqh	reg, scr3, scr2
                  [000000]   410  	mskqh	scr1, scr3, scr1
                  [000000]   411  	bis	scr1, scr2, scr1
                  [000000]   412  	stq_u	scr1, 7(scr3)
                  [000000]   413  
                  [000000]   414      .iff
                  [000000]   415  
                  [000000]   416  	bic	addr, #7, scr3
                  [000000]   417  	ldq_l	scr1, (scr3)
                  [000000]   418  	insql	reg, addr, scr2
                  [000000]   419  	mskql	scr1, addr, scr1
                  [000000]   420  	bis	scr1, scr2, scr1
                  [000000]   421  	stq_c	scr1, (scr3)
                  [000000]   422  
                  [000000]   423  	.iif nb <err>, blbc scr1, err
                  [000000]   424  
                  [000000]   425  	lda	scr3, 7(addr)
                  [000000]   426  
                  [000000]   427  	bic	scr3, #7, scr3
                  [000000]   428  	ldq_l	scr1, (scr3)
                  [000000]   429  	insqh	reg, addr, scr2
                  [000000]   430  	mskqh	scr1, addr, scr1
                  [000000]   431  	bis	scr1, scr2, scr1
                  [000000]   432  	stq_c	scr1, (scr3)
                  [000000]   433  
                  [000000]   434  	.iif nb <err>, blbc scr1, err1
                  [000000]   435      .endc
                  [000000]   436  .endm
                  [000000]   437  
                  [000000]   438  ;
                  [000000]   439  ; For longword queue operations
                  [000000]   440  ;
                  [000000]   441  .macro	QSTORE_UNALIGNED_LONG reg, disp, addr, scr1, scr2, scr3
                  [000000]   442  	lda	scr3, disp(addr)
                  [000000]   443  
                  [000000]   444  	ldq_u	scr1, disp(addr)
                  [000000]   445  	insll	reg, scr3, scr2
                  [000000]   446  	mskll	scr1, scr3, scr1
                  [000000]   447  	bis	scr1, scr2, scr1
                  [000000]   448  	stq_u	scr1, disp(addr)
                  [000000]   449  
                  [000000]   450  	ldq_u	scr1,<disp+3>(addr)
                  [000000]   451  	inslh	reg, scr3, scr2
                  [000000]   452  	msklh	scr1, scr3, scr1
                  [000000]   453  	bis	scr1, scr2, scr1
                  [000000]   454  	stq_u	scr1, <disp+3>(addr)
                  [000000]   455  .endm
                  [000000]   456  
                  [000000]   457  .macro	STORE_REG n, srn, irn, fpu=0, pal=0, ipr=0
                  [000000]   458  ;
                  [000000]   459  ; n = register number
                  [000000]   460  ; srn = scratch register
                  [000000]   461  ; irn = impure base register
                  [000000]   462  ; 
                  [000000]   463      ASSUME <fpu+pal+ipr> lt 2
                  [000000]   464  
                  [000000]   465      .if eq fpu+pal+ipr
                  [000000]   466  	hw_stq/p r'n', CNS__R'n'(irn)
                  [000000]   467      .endc
                  [000000]   468  
                  [000000]   469      .if ne fpu
                  [000000]   470  	ftoit	f'n', srn
                  [000000]   471  	hw_stq/p srn, CNS__F'n'(irn)
                  [000000]   472      .endc
                  [000000]   473  
                  [000000]   474      .if ne pal
                  [000000]   475  	hw_ldq/p srn, PT__'n'(p_temp)
                  [000000]   476  	hw_stq/p srn, CNS__'n'(irn)
                  [000000]   477      .endc
                  [000000]   478  
                  [000000]   479      .if ne ipr
                  [000000]   480  	hw_mfpr	srn, EV6__'n'
                  [000000]   481  	hw_stq/p srn, CNS__'n'(irn)
                  [000000]   482      .endc
                  [000000]   483  .endm
                  [000000]   484  
                  [000000]   485  .macro	RESTORE_REG n, srn, irn, fpu=0, pal=0, ipr=0
                  [000000]   486  ;
                  [000000]   487  ; n = register number
                  [000000]   488  ; srn = scratch register
                  [000000]   489  ; irn = impure base register
                  [000000]   490  ; 
                  [000000]   491      ASSUME <fpu+pal+ipr> lt 2
                  [000000]   492  
                  [000000]   493      .if eq fpu+pal+ipr
                  [000000]   494  	hw_ldq/p r'n', CNS__R'n'(irn)
                  [000000]   495      .endc
                  [000000]   496  
                  [000000]   497      .if ne fpu
                  [000000]   498  	hw_ldq/p srn, CNS__F'n'(irn)
                  [000000]   499  	itoft	srn, f'n'
                  [000000]   500      .endc
                  [000000]   501  
                  [000000]   502      .if ne pal
                  [000000]   503  	hw_ldq/p srn, CNS__'n'(irn)
                  [000000]   504  	hw_stq/p srn, PT__'n'(p_temp)
                  [000000]   505      .endc
                  [000000]   506  
                  [000000]   507      .if ne ipr
                  [000000]   508  	hw_ldq/p srn, CNS__'n'(irn)
                  [000000]   509  	hw_mtpr	srn, EV6__'n'
                  [000000]   510      .endc
                  [000000]   511  .endm
                  [000000]   512  
                  [000000]   513  ;+
                  [000000]   514  ; PVC macros
                  [000000]   515  ;-
                  [000000]   516  .macro	PVC_JSR token, dest=0, bonus=0, bsr=0
                  [000000]   517      .iif gt bsr-1, pcv__'token' == bsr
                  [000000]   518      .if ndf osfpal
                  [000000]   519  	.iif ndf pcv_jsr_index, pcv_jsr_index = 2100
                  [000000]   520      .iff
                  [000000]   521  	.iif ndf pcv_jsr_index, pcv_jsr_index = 3100
                  [000000]   522      .endc
                  [000000]   523      .iif ndf pcv_index, pcv_index = 100
                  [000000]   524      tpcv_jsr_index = pcv_jsr_index
                  [000000]   525      .iif ne bsr, pcv_jsr_index = pcv_jsr_index + 2000
                  [000000]   526      .iif gt bsr-1, pcv_jsr_index = bsr
                  [000000]   527      .iif ndf pcv_jsr_'token''bonus', pcv_jsr_'token''bonus' == pcv_jsr_index
                  [000000]   528      .iif ndf pcv_jsr_'token''bonus'_inst, pcv_jsr_'token''bonus'_inst = 1
                  [000000]   529  
                  [000000]   530      .if eq dest
                  [000000]   531  	.iif df osfpal, pvc_lbl \pcv_index, \pcv_jsr_'token''bonus', osf
                  [000000]   532  	.iif ndf osfpal, pvc_lbl \pcv_index, \pcv_jsr_'token''bonus', vms
                  [000000]   533      .iff
                  [000000]   534  	.iif df osfpal, pvc_lbl \pcv_index, \pcv_jsr_'token''bonus', -
                  [000000]   535  			osf, \pcv_jsr_'token''bonus'_inst
                  [000000]   536  	.iif ndf osfpal, pvc_lbl \pcv_index, \pcv_jsr_'token''bonus', -
                  [000000]   537  			vms, \pcv_jsr_'token''bonus'_inst
                  [000000]   538  	pcv_jsr_'token''bonus'_inst = pcv_jsr_'token''bonus'_inst +1
                  [000000]   539      .endc
                  [000000]   540      pcv_jsr_index = tpcv_jsr_index
                  [000000]   541      pcv_jsr_index = pcv_jsr_index + 1
                  [000000]   542      pcv_index = pcv_index + 1
                  [000000]   543  .endm
                  [000000]   544  
                  [000000]   545  .macro	PVC_VIOLATE rule
                  [000000]   546      .iif ndf pcv_index, pcv_index = 0
                  [000000]   547      .iif nb <rule>, pcv_rule = rule
                  [000000]   548      .iif df osfpal, pvc_lbl \pcv_index, \pcv_rule, osf
                  [000000]   549      .iif ndf osfpal, pvc_lbl \pcv_index,\pcv_rule, vms
                  [000000]   550      pcv_index = pcv_index +1
                  [000000]   551  .endm
                  [000000]   552  
                  [000000]   553  .macro	PVC_LBL indx, rule, os, inst=0, value
                  [000000]   554      .if nb <value>
                  [000000]   555  	.iif eq inst, pvc$'os''indx'$'rule' == value
                  [000000]   556  	.iif ne inst, pvc$'os''indx'$'rule'.'inst' == value
                  [000000]   557      .iff
                  [000000]   558  	.iif eq inst, pvc$'os''indx'$'rule' == .
                  [000000]   559  	.iif ne inst, pvc$'os''indx'$'rule'.'inst' == .
                  [000000]   560      .endc
                  [000000]   561  .endm
File: ev6_osf_pal.mar
                  [000000]     1  ;+
                  [000000]     2  ; ev6_osf_pal.mar
                  [000000]     3  ;-
                  [000000]     4  	.title	"EV6_OSF_PAL"		; informational only
                  [000000]     5  	.ident	"V1.50"			; informational only
                  [000000]     6  ;+
                  [000000]     7  ; Last Edit:	09-Apr-1999
                  [000000]     8  ;
                  [000000]     9  ; Edit History
                  [000000]    10  ;
                  [000000]    11  ; Who	Rev	When		What
                  [000000]    12  ; ---	---	----		----
                  [000000]    13  ; ES		04-Sep-96	Basic code. Passes Egore.
                  [000000]    14  ; ES		11-Sep-96	In trap__switch and trap__switch, form
                  [000000]    15  ;					PAL base more safely.
                  [000000]    16  ;				Put in pal__save_state and pal__restore_state
                  [000000]    17  ;				Put in pal__update_pcb_and_halt
                  [000000]    18  ; ES		13-Sep-96	Don't need console conditional. Default to it.
                  [000000]    19  ;					The important conditionl is srm_console.
                  [000000]    20  ;				Rearranged non-srm console powerup. Put powerup
                  [000000]    21  ;					totally in system_pal. Have powerup
                  [000000]    22  ;					do signature and swap checking.
                  [000000]    23  ;				Take redundant DTB flush out of switch.
                  [000000]    24  ;				Put in sys__enter_console, and sys__exit_console.
                  [000000]    25  ; ES		17-Sep-96	In save and restore, add vptb.
                  [000000]    26  ; ES		18-Sep-96	Added trap__cserve and sys__cserve, putting in
                  [000000]    27  ;					cserve__start and cserve__callback.
                  [000000]    28  ;				Added reference platform conditional.
                  [000000]    29  ;				In pal__restore_state, fix typo, so that
                  [000000]    30  ;					pal mode is or'ed in when turning
                  [000000]    31  ;					off shadow mode.
                  [000000]    32  ; ES		24-Sep-96	In pal__restore_state, when setting up
                  [000000]    33  ;					DTB_ASNx, don't trash r1.
                  [000000]    34  ;				Eliminate PT__M_CTL and PT__DC_CTL. Work
                  [000000]    35  ;					only from CNS__M_CTL and CNS__DC_CTL.
                  [000000]    36  ;					It's simpler and fixes save/restore bugs.
                  [000000]    37  ;				Add some PVC_VIOLATEs for hw_jmp_stalls.
                  [000000]    38  ; ES		25-Sep-96	Add mchk and crd.
                  [000000]    39  ;				In sys__switch_unknown, turn into HALT__JUMP0.
                  [000000]    40  ;				Add OSF_IPL_DEFS.
                  [000000]    41  ;				In trap__unalign_cm, had wrong reg in jmp_stall!
                  [000000]    42  ;				Add basic interrupt handling.
                  [000000]    43  ;				In cserve, add srm_console conditional.
                  [000000]    44  ; ES		27-Sep-96	In trap__interrupt, avoid cbr in 1st fetch block.
                  [000000]    45  ;				In trap__mt_fpcr, make 1st fetch block clean.
                  [000000]    46  ; ES		30-Sep-96	In trap__itb_miss, avoid trappable instructions
                  [000000]    47  ;					out of 1st fetc block.
                  [000000]    48  ; ES		24-Oct-96	In trap__arith, need to check for fpcr update
                  [000000]    49  ;					for integer overflow.
                  [000000]    50  ; ES		01-Nov-96	In switch, tbi functions, and imb, add
                  [000000]    51  ;					a write to ic_flush or ic_flush_asm.
                  [000000]    52  ;					Writes to itb_ia, itb_iap no longer
                  [000000]    53  ;					flush the icache.
                  [000000]    54  ;				In sys__crd, use current register to or
                  [000000]    55  ;					mchk code into p_misc. And use
                  [000000]    56  ;					MCES__PCE__S to test second error.
                  [000000]    57  ;				Rearrange order in ev6_osf_system_pal.mar.
                  [000000]    58  ; ES		06-Nov-96	In trap__unalign, fix bug where register
                  [000000]    59  ;					number was not being saved on stores.
                  [000000]    60  ; ES		12-Nov-96	In non-srm powerup, clear the fpcr to make the
                  [000000]    61  ;					simulator happy.
                  [000000]    62  ;				Add cflush call_pal.
                  [000000]    63  ; ES		13-Nov-96	In call_pal tbi, use r17 (not r16) for va.
                  [000000]    64  ; ES		27-Nov-96	Re-worked machine check handling in
                  [000000]    65  ;					ev6_osf_pal.mar, ev6_osf_system_pal.mar.
                  [000000]    66  ;				Added trap__pal_bugcheck code.
                  [000000]    67  ; ES		02-Dec-96	Added perfmon call_pal.
                  [000000]    68  ; ES		04-Dec-96	Don't trash r17 in call_pal__perfmon_wr_1.
                  [000000]    69  ; ES		06-Dec-96	Don't trash r17 in call_pal__perfmon_wr_1.
                  [000000]    70  ;					Really fix it this time.
                  [000000]    71  ; ES		09-Dec-96	Add ev6_p1, ev6_p2.
                  [000000]    72  ; ES		12-Dec-96	In ev6_osf_pal.mar and ev6_osf_system_pal.mar,
                  [000000]    73  ;					IMPORTANT CHANGE!!!
                  [000000]    74  ;					ev6__i_ctl<single_issue_l>
                  [000000]    75  ;						is really
                  [000000]    76  ;					ev6__i_ctl<single_issue_h>.
                  [000000]    77  ;				To avoid ISP/Behavorial mismatch on
                  [000000]    78  ;					hw_mfpr EV6__VA
                  [000000]    79  ;					when synching for asnx and isx, do a
                  [000000]    80  ;					hw_mfpr <EV6__PAL_BASE ! ^xF0>,
                  [000000]    81  ;					which scoreboards 4-7.
                  [000000]    82  ; ES		09-Jan-97	Re-worked reset. Moved more to the system
                  [000000]    83  ;					palcode. Need to do exact mapping
                  [000000]    84  ;					sequence with source map enable.
                  [000000]    85  ;					See SROM for retirator macro.
                  [000000]    86  ; ES		23-Jan-97	Still working on reset. Re-did switch entry
                  [000000]    87  ;					point a  little as well.
                  [000000]    88  ;					IMPORTANT: We assume that
                  [000000]    89  ;					INITIALIZE_RETIRATOR_AND_MAPPER and
                  [000000]    90  ;					MAP_SHADOW_REGISTERS
                  [000000]    91  ;					are both done in SROM; otherwise, we
                  [000000]    92  ;					we have to hack swppal support.
                  [000000]    93  ; ES		30-Jan-97	Set both spe modes so we can access i/o and
                  [000000]    94  ;					have normal unix superpage mode.
                  [000000]    95  ;				On pass1, set dc_ctl__dcdat_err_en to 0, since
                  [000000]    96  ;					there are ecc checking problems.
                  [000000]    97  ; ES		06-Feb-97	Fixed PVC violations found while checking vms.
                  [000000]    98  ;				(1) In powerup, separate mt_fpcr from mxpr.
                  [000000]    99  ;				(2) In powerup, pvc_violate 21 on asn clear.
                  [000000]   100  ;				(3) In sys__cbox, 1006. Also use hw_ret.
                  [000000]   101  ;				(4) In sys__mchk_scrub, pvc_violate 1006.
                  [000000]   102  ;				(5) In pal__save_state, pvc_violate 12.
                  [000000]   103  ;				(6) In pal__save_state, use hw_ret.
                  [000000]   104  ;				(7) In pal__restore_state, use hw_ret.
                  [000000]   105  ;				(8) In illegal call_pal, use hw_jmp.
                  [000000]   106  ;				(9) In swppal, use hw_jmp.
                  [000000]   107  ;				(10)In sys__int_post, use hw_ret_stall.
                  [000000]   108  ;				(11)In tbi, use hw_jmp.
                  [000000]   109  ;				(12)In wrent, use hw_jmp.
                  [000000]   110  ; ES		11-Feb-97	In wrperfmon, zap low nibbles of counts for p1.
                  [000000]   111  ; ES	1.1	24-Feb-97	(1) Start version numbers.
                  [000000]   112  ; ES		24-Feb-97	(2) In restore state, restore the vptb portion
                  [000000]   113  ;					of I_CTL and VA_CTL from CNS__VPTB.
                  [000000]   114  ;					Also restore PT__VA_CTL.
                  [000000]   115  ;				(3) Interrupt processing code jumped to
                  [000000]   116  ;					post_int without checking for swap
                  [000000]   117  ;					stack. Add that code to sys__int_post.
                  [000000]   118  ;					Also can eliminate that code from
                  [000000]   119  ;					machine check.
                  [000000]   120  ;				(3) In sys__enter_console, Go to 48-bit mode
                  [000000]   121  ;					in VA_CTL so that 1-1 console can
                  [000000]   122  ;					access I/O.
                  [000000]   123  ;				(4) Add dtbm_double_4.
                  [000000]   124  ;				(5) In pal__restore_state, write i_ctl
                  [000000]   125  ;					twice to cause a stall in case
                  [000000]   126  ;					we are toggling 48-bit mode bit.
                  [000000]   127  ; ES	1.2	10-Apr-97	Changes.
                  [000000]   128  ;				(1) Put IPL table at ^x0D00
                  [000000]   129  ;				(2) On p1, don't set DC_CTL<DCDAT_ERR_EN>.
                  [000000]   130  ;				(3) Do ldq on unlock in sys__reset and 
                  [000000]   131  ;					sys__exit_console. In sys__reset, put
                  [000000]   132  ;					an mb before ldq (pvc #28)
                  [000000]   133  ;				(4) Implement new palcode restriction, separating
                  [000000]   134  ;					retires of flush and hw_ret_stall.
                  [000000]   135  ;				(5) Bug in tbiap -- need ic_flush_asm,
                  [000000]   136  ;					not ic_flush.
                  [000000]   137  ;				(6) In switch, reset, exit console palcode,
                  [000000]   138  ;					redo some jmp_stall, scoreboard bit
                  [000000]   139  ;					synchronization.
                  [000000]   140  ;				(7) In hw_jmp_stall, use 1 instruction to
                  [000000]   141  ;					create offset instead of loading
                  [000000]   142  ;					offset and do a bis #1.
                  [000000]   143  ;				(8) In enter_console, write i_ctl twice
                  [000000]   144  ;					to wait until write completes
                  [000000]   145  ;					(pvc #31).
                  [000000]   146  ;				(9) In pass1, dc_ctl<dctag_par_en> must be 0.
                  [000000]   147  ;				(10)Change cbox read chain names to match spec.
                  [000000]   148  ;				(11)Add PAL_BASE, I_CTL, PROCESS_CONTEXT to
                  [000000]   149  ;					mchk logout frame.
                  [000000]   150  ;				(12)Add check_interrupt_pending conditional
                  [000000]   151  ;					for deasserting interrupts.
                  [000000]   152  ;				(13)In sys__cbox, add mb, eliminate mb's of
                  [000000]   153  ;					calling routines. Add clearing of
                  [000000]   154  ;					i_ctl<sbe> bits and ic_flush to
                  [000000]   155  ;					quiet the stream.
                  [000000]   156  ;				(14)In sys__reset, don't set spe<2>. Unix
                  [000000]   157  ;					just uses spe<1>, and works around
                  [000000]   158  ;					sign extension issues for i/o.
                  [000000]   159  ; ES	1.3	16-Apr-97	FP emulation support added.
                  [000000]   160  ;					Changes in fen, opcdec, arith,
                  [000000]   161  ;					wrfen, clrfen, swpctx, reset, fault
                  [000000]   162  ;					unalign, and tnv handling. Also added
                  [000000]   163  ;					CALL_PAL__003B to return to pal mode
                  [000000]   164  ;					after call to emulator.
                  [000000]   165  ;				In trap__switch, and sys_switch,
                  [000000]   166  ;					'bis' not 'and' asn and fpe!
                  [000000]   167  ;				Fix various pvc violations.
                  [000000]   168  ; ES	1.4	09-Jun-97	(1) Because of cbox triplicate tags, can
                  [000000]   169  ;					not do dc_ctl<flush> in reset. 
                  [000000]   170  ;					BIST cleans it anyway.
                  [000000]   171  ;				(2) In check_interrupt_pending code, hold
                  [000000]   172  ;					off writing IER until we have read
                  [000000]   173  ;					ISUM. Not good practice the other way.
                  [000000]   174  ;				(3) Ensure the ordering of ISUM and IER.
                  [000000]   175  ;				(4) Reorder mchk logout frame. Add VA_CTL.
                  [000000]   176  ; ES	1.5	26-Jun-97	(1) BUG FIX:
                  [000000]   177  ;					In sys__crd_second and
                  [000000]   178  ;					sys__crd_skip_frame, recover
                  [000000]   179  ;					exc_addr from PT__STACK_PC
                  [000000]   180  ;					because p23 has been trashed.
                  [000000]   181  ;				(2) Turn icache fill mchks into crd mchks.
                  [000000]   182  ;				(3) Turn recoverable dc_tag_perr into crd mchk.
                  [000000]   183  ;				(4) Eliminate VA and VA_CTL from mchk frame.
                  [000000]   184  ;				(5) Add mchk and mchk_crd revision.
                  [000000]   185  ; ES	1.6	01-Aug-97	(1) Add cserve code for DP264 debug monitor.
                  [000000]   186  ;				(2) Add clock interrupt clear for DP264.
                  [000000]   187  ;				(3) Add ev6_p2 conditional to C_ADDR_SHIFT
                  [000000]   188  ;					definition.
                  [000000]   189  ;				(4) On DFAULT for DC_TAG_PERR, need to turn
                  [000000]   190  ;					off DCTAG_PAR_EN to avoid a mchk on
                  [000000]   191  ;					the ECB.
                  [000000]   192  ;				(5) Add sample tsunami/DP264 clear interrupt
                  [000000]   193  ;					pending code.
                  [000000]   194  ;				(6) For p1, in restore_state, restore
                  [000000]   195  ;					CNS__FPE_STATE from CNS__PCTX to
                  [000000]   196  ;					keep it coherent with CNS__PCTX.
                  [000000]   197  ;				(7) In save_state, eliminate double mm_stat save.
                  [000000]   198  ;				(8) Go back to having PT__M_CTL as well as
                  [000000]   199  ;					CNS__M_CTL so we have a live and
                  [000000]   200  ;					saved version.
                  [000000]   201  ;				(9) Add va_48 conditional for xx_CTL__INIT
                  [000000]   202  ;					values.
                  [000000]   203  ;				(10)Added tb_mb_en conditional.
                  [000000]   204  ;				(11)Added mchk_en conditional.
                  [000000]   205  ;				(12)Dismiss missing/faulting WH64/ECB.
                  [000000]   206  ;				(13)On swppal with srm_console, get VA_48
                  [000000]   207  ;					status and set SPE accordingly.
                  [000000]   208  ;				(14)Handle I_CTL<SDE> with 5 fetch blocks
                  [000000]   209  ;					instead of jmp_stall to avoid
                  [000000]   210  ;					a conjectured race condition.
                  [000000]   211  ;				(15)In ev6_p1 initialization, corrected
                  [000000]   212  ;					zap of CNS__x31_EMUL.
                  [000000]   213  ;				(16)Eliminate unnecessary jmp_stalls in
                  [000000]   214  ;					switch pal code and power up.
                  [000000]   215  ;				(17)In emulator code, map 4MB region
                  [000000]   216  ;					depending on location of emulator.
                  [000000]   217  ;					Make stack space = ^x400.
                  [000000]   218  ;				(18)On IMB, do an MB.
                  [000000]   219  ;				(19)In CSERVE jtopal, add mb and 
                  [000000]   220  ;					or in 1 to r16 to form pal address.
                  [000000]   221  ;				(20)Handle FPE with 5 fetch blocks.
                  [000000]   222  ;				(21)In emulator, load PT_WHAMI off of
                  [000000]   223  ;					p_temp, NOT p4.
                  [000000]   224  ; ES	1.7	25-Aug-97	(1)Add dcache_set_en conditional. In p1,
                  [000000]   225  ;					default to 1. In p2, default to 3.
                  [000000]   226  ;					Use in dc_tag_perr processing and
                  [000000]   227  ;					reset. Also add an MB in dc_tag_perr.
                  [000000]   228  ; ES	1.8	12-Sep-97	(1)Changes to DTBM_SINGLE, DTBM_DOUBLE_3
                  [000000]   229  ;					and DTBM_DOUBLE_4. Get VA
                  [000000]   230  ;					before read of VPTE. Use p7<0>
                  [000000]   231  ;					as a double miss flag. On double
                  [000000]   232  ;					miss, put mm_stat from p5 into
                  [000000]   233  ;					<31:15> of p7, which contains
                  [000000]   234  ;					exc_sum and double miss flag.
                  [000000]   235  ;					Use p5 for exc_addr of double miss.
                  [000000]   236  ;					Restore mm_stat into p5 on
                  [000000]   237  ;					invalid_dpte when double miss.
                  [000000]   238  ;				(2)In ITB_MISS, don't use p5 until
                  [000000]   239  ;					after the VPTE fetch.
                  [000000]   240  ;				(3)Need CONT_HW_VECTOR in double_4 flow. 
                  [000000]   241  ; ES	1.9	18-Sep-97	(1)Emulator called in kseg. Need matching
                  [000000]   242  ;					emulator built for kseg.
                  [000000]   243  ;				(2)Xor in dtb miss before load virtual.
                  [000000]   244  ;					Ensures va is in hand.
                  [000000]   245  ; ES	1.10	24-Sep-97	(1)Add counter for fp emulates. Modifications
                  [000000]   246  ;					in swppal, fen, new call_pal ^xAD, to
                  [000000]   247  ;					get count.
                  [000000]   248  ;				(2)Pass serial line interrupts off to
                  [000000]   249  ;					platform specific call.
                  [000000]   250  ;				(3)Add a hw_ret after sys__int_err for pvc.
                  [000000]   251  ; ES	1.11	08-Oct-97	(1)Add clrmap symbol and clrmap call_pal.
                  [000000]   252  ;				   	Note: clrmap=1 is required to get
                  [000000]   253  ;					clrmap!
                  [000000]   254  ;				(2)In sys__enter_console, update PT__VA_CTL
                  [000000]   255  ;				   	to reflect change to VA_CTL, so that
                  [000000]   256  ;				   	PALcode running while console is
                  [000000]   257  ;					running doesn't have problems
                  [000000]   258  ;					flipping modes.
                  [000000]   259  ;				(3)In trap__switch_base, have conditional
                  [000000]   260  ;					code which turns on multi-issue.
                  [000000]   261  ;					Requested by DP264 debug team.
                  [000000]   262  ; ES	1.12	24-Oct-97	(1)In trap__reset, use r26 when branching to
                  [000000]   263  ;					sys__reset, as dp264 srom passes
                  [000000]   264  ;					up parameter in r1.
                  [000000]   265  ;				(2)Eliminate use of SROM conditional in
                  [000000]   266  ;					WAKEUP. Not testing that way
                  [000000]   267  ;					anymore.
                  [000000]   268  ;				(3)Add SROM parameter passing for DP264 debug
                  [000000]   269  ;					monitor	in the system code.
                  [000000]   270  ;				(4)Change beh_model default to 0.
                  [000000]   271  ;				(5)Add dbm_serial_io conditional for debug
                  [000000]   272  ;					monitor	serial line i/o.
                  [000000]   273  ; ES	1.13	31-Oct-97	(1)Fix typo in system code. Change _INIT to
                  [000000]   274  ;					__INIT in EV6__DC_CTL__INIT.
                  [000000]   275  ;				(2)On dc_tag_perr, only halt on dc_tag_perr
                  [000000]   276  ;					while in pal_mode. Add a new halt
                  [000000]   277  ;					code HALT__DC_TAG_PERR_FROM_PAL.
                  [000000]   278  ;					On mchk in progress, just dismiss
                  [000000]   279  ;					after fixing.
                  [000000]   280  ;				(3)Save mm_stat in short frame. Before
                  [000000]   281  ;					merge to sys__crd_merge, each
                  [000000]   282  ;					flow must write MCHK_CRD__MM_STAT.
                  [000000]   283  ;					The dc_tag_perr error writes a
                  [000000]   284  ;					useful mm_stat, showing the error.
                  [000000]   285  ;				(4)In system pal, in sys__crd, correct typo
                  [000000]   286  ;					in building p_misc: use p6, not p4.
                  [000000]   287  ;				(5)In swppal, use a quadword for PAL__ENTER_OSF.
                  [000000]   288  ; ES	1.14	04-Nov-97	(1)In exit_console, on load/unlock, set
                  [000000]   289  ;					protection to all RWE in case we
                  [000000]   290  ;					are exiting into user mode (we
                  [000000]   291  ;					have already changed mode at
                  [000000]   292  ;					this point).
                  [000000]   293  ;				(2)Add CSERVE__START to non-srm console cserve.
                  [000000]   294  ;				(3)Add pvc labels for bsr emul_restore
                  [000000]   295  ;					so that pvc doesn't terminate
                  [000000]   296  ;					permutation on subroutine return.
                  [000000]   297  ; ES	1.15	17-Dec-97	(1)Change DC_STAT field names.
                  [000000]   298  ; ES	1.16	18-Dec-97	(1)Don't zap low nibble of counters on writing
                  [000000]   299  ;					performance counters.
                  [000000]   300  ;				(2)In machine flow, move read and store of isum
                  [000000]   301  ;					earlier so we only read isum for system
                  [000000]   302  ;					machine interrupt once.
                  [000000]   303  ;				(3)Put MB in double flow in ev6_p1 conditional.
                  [000000]   304  ;				(4)Put CLRMAP in ev6_p1 conditional, and make
                  [000000]   305  ;					default CLRMAP = 1.
                  [000000]   306  ;				(5)Add some PVC_VIOLATE <35>'s. (HW_INT_CLR)
                  [000000]   307  ;					Re-arrange sys__crd_skip_frame a bit.
                  [000000]   308  ; ES	1.17	12-Jan-98	(1)In arithmetic exception, ignore SWC bit
                  [000000]   309  ;					when checking whether to take an
                  [000000]   310  ;					exception.
                  [000000]   311  ; ES	1.18	21-Jan-98	(1)Another PVC_VIOLATE <35>, this one in switch
                  [000000]   312  ;					palcode.
                  [000000]   313  ;				(2)Change <ev6_p1 ! ev6_p2> conditional to
                  [000000]   314  ;					just ev6_p1 in cbox read chain code.
                  [000000]   315  ; ES	1.19	04-Feb-98	(1)Read ISUM twice in interrupt to minimize the
                  [000000]   316  ;					possibility of a read/write conflict
                  [000000]   317  ;					causing a read of 0.
                  [000000]   318  ;				(2)In perfmon, zap counter on disable for
                  [000000]   319  ;					both pass1 AND pass2.
                  [000000]   320  ;				(3)Add check for double bit error before
                  [000000]   321  ;					istream error in mchk.
                  [000000]   322  ;				(4)Add check for istream mchk in crd flow.
                  [000000]   323  ;				(5)In reset, read the cbox error read chain
                  [000000]   324  ;					to clear it out.
                  [000000]   325  ;				(6)In reset, comment out clearing fpcr. It's
                  [000000]   326  ;					unpredictable anyway, and it's possibly
                  [000000]   327  ;					set up by the srom.
                  [000000]   328  ;				(7)In sys__mchk and sys__mchk_clear_crd,
                  [000000]   329  ;					change r5 to p5 (just a name change).
                  [000000]   330  ; ES	1.20	09-Feb-98	(1)In perfmon, fix typo in conditional
                  [000000]   331  ;					that turns on zapping counter
                  [000000]   332  ;					for both pass1 and pass2.
                  [000000]   333  ; ES	1.21	13-Mar-98	(A)Large rewrite of error handling.
                  [000000]   334  ;				(1)sys__int_err -- does more logging and then
                  [000000]   335  ;					branches to sys__mchk_header.
                  [000000]   336  ;				(2)sys__crd
                  [000000]   337  ;					(a)Now scrubs under certain conditions.
                  [000000]   338  ;						Does it before merge point from
                  [000000]   339  ;						630's.
                  [000000]   340  ;					(b)Now logs i_stat, dc_stat before merge
                  [000000]   341  ;						from 630's. Only clear crd-type
                  [000000]   342  ;						errors in dc_stat in case there
                  [000000]   343  ;						is a delayed mchk in the wings.
                  [000000]   344  ;					(c)Crd from speculative mchk now handled
                  [000000]   345  ;						directly in this code.
                  [000000]   346  ;					(d)New merge point is sys__crd_header.
                  [000000]   347  ;					(e)Dpc and pce flows also scrub
                  [000000]   348  ;						as necessary.
                  [000000]   349  ;				(3)sys_crd_scrub -- new routine to scrub. Also
                  [000000]   350  ;					includes a store to make block dirty.
                  [000000]   351  ;				(4)sys__mchk_dc_tag_perr
                  [000000]   352  ;					(a)Does more logging before merging at
                  [000000]   353  ;						sys__crd_header.
                  [000000]   354  ;					(b)Has its own dpc and pce flows.
                  [000000]   355  ;				(5)sys__mchk
                  [000000]   356  ;					(a)Now logs i_stat, dc_stat before merge
                  [000000]   357  ;						from 660's.
                  [000000]   358  ;					(b)New merge point is sys__mchk_header.
                  [000000]   359  ;					(c)Istream mchk to crd now does more
                  [000000]   360  ;						logging before branching to
                  [000000]   361  ;						sys__crd_header.
                  [000000]   362  ;				(6)sys__mchk_scrub -- includes a store to make
                  [000000]   363  ;					block dirty.
                  [000000]   364  ;				(7)trap__pal_bugcheck -- does more logging
                  [000000]   365  ;					before branching to sys__mchk_header.
                  [000000]   366  ;				(8)perfmon -- minor change to an ASSUME.
                  [000000]   367  ;
                  [000000]   368  ;				(B)Turn hw_jmp's, jmp's into hw_ret, ret's to
                  [000000]   369  ;				avoid issuing instructions in PALmode on random
                  [000000]   370  ;				cache line predictions.
                  [000000]   371  ; ES	1.22	31-Mar-98	In sys__crd_scrub, need to save off p7
                  [000000]   372  ;					before calling sys__cbox, and then
                  [000000]   373  ;					restore on return.	
                  [000000]   374  ; ES	1.23	29-Apr-98	(1)In trap__save_state and trap__restore_state,
                  [000000]   375  ;					don't save and restore pctr_ctl
                  [000000]   376  ;					(which causes the counter
                  [000000]   377  ;					to increment since we get a
                  [000000]   378  ;					post-incremented copy from the chip
                  [000000]   379  ;					even if counting is disabled).
                  [000000]   380  ;				(2)Add comments and definitions relating to
                  [000000]   381  ;					ev6_p3 changes of I_STAT.
                  [000000]   382  ; ES	1.24	15-May-98	(1)In double flows, force a stall until
                  [000000]   383  ;					the pte writes retire to avoid
                  [000000]   384  ;					issue of tag write in single flow
                  [000000]   385  ;					before retire of pte write in double
                  [000000]   386  ;					flow.
                  [000000]   387  ; ES	1.25	18-May-98	(1)In sys__reset, just check for 'DEC', not
                  [000000]   388  ;					'DECB'.
                  [000000]   389  ;				(2)Add reference platform support for use
                  [000000]   390  ;					of write_many_chain.
                  [000000]   391  ; ES	1.26	29-Jun-98	(1)Add sleep support (First cut).
                  [000000]   392  ;				(2)On save_state, just zero exc_sum value.
                  [000000]   393  ;					Not useful and can be misleading.
                  [000000]   394  ;				(2)In arith exception, zap the upper portion
                  [000000]   395  ;					of exc_sum so we don't step on
                  [000000]   396  ;					fpcr.
                  [000000]   397  ; ES	1.27	09-Jul-98	(0)Stick reference_platform conditionals
                  [000000]   398  ;					around wtint and wakeup.
                  [000000]   399  ;				(1)In sys__mchk_scrub, map
                  [000000]   400  ;					address and then scrub using
                  [000000]   401  ;					ldq_l, stq_c. Also move mb.
                  [000000]   402  ;				(2)In sys__mchk_clear_crd, also clear
                  [000000]   403  ;					dc_stat, and force ipr writes
                  [000000]   404  ;					to finish.
                  [000000]   405  ;				(3)In sys__crd, look for a double
                  [000000]   406  ;					bit error that may have
                  [000000]   407  ;					occurred just after the single
                  [000000]   408  ;					bit error.
                  [000000]   409  ;				(4)In sys__crd, don't scrub for
                  [000000]   410  ;					dstream_dc_err.
                  [000000]   411  ;				(5)In sys__crd_merge, also
                  [000000]   412  ;					clear dc_stat and force
                  [000000]   413  ;					ipr writes to finish.
                  [000000]   414  ;				(6)In sys__crd_skip_frame, don't
                  [000000]   415  ;					scrub for dstream_dc_err.
                  [000000]   416  ;				(7)In sys__crd_skip_frame_merge, also
                  [000000]   417  ;					clear dc_stat and force
                  [000000]   418  ;					ipr writes to finish.
                  [000000]   419  ;				(8)In sys__crd_scrub, map
                  [000000]   420  ;					address and then scrub using
                  [000000]   421  ;					ldq_l, stq_c. Also move mb.
                  [000000]   422  ;				(9)Put in pte eco.
                  [000000]   423  ;				(10)Add call_pal for debug monitor. Add
                  [000000]   424  ;					force_ecc, and set clrmap default
                  [000000]   425  ;					to 0.
                  [000000]   426  ; ES	1.28	21-Jul-98	(1)Clean up comments on force_ecc.
                  [000000]   427  ;				(2)Fix scoreboard bit on sleep stuff.
                  [000000]   428  ;				(3)Add check_mem call_pal.
                  [000000]   429  ;				(4)Work around for rdblkmodify nxm bug.
                  [000000]   430  ; ES	1.29	27-Jul-98	Do some more tweaking on nxm bug.
                  [000000]   431  ; ES	1.30	27-Jul-98	More tweaking
                  [000000]   432  ; ES	1.31	28-Jul-98	More tweaking
                  [000000]   433  ; ES	1.32	30-Jul-98	Optimize kseg miss to do GH=3 and ASM=1.
                  [000000]   434  ;				Fix comments on dc_tag_perr.
                  [000000]   435  ;				Fix bug in i/o space checking in kseg hack.
                  [000000]   436  ;					Check bit 40, which is sign
                  [000000]   437  ;					extended into 43 on 43 bit kseg.
                  [000000]   438  ; ES	1.33	03-Aug-98	Undo istream kseg hack.
                  [000000]   439  ; ES	1.34	05-Aug-98	In RTI/RETSYS remove unnecessary stl to clear
                  [000000]   440  ;				locks.
                  [000000]   441  ; ES	1.35	06-Aug-98	(1)Put kseg hack in conditionals.
                  [000000]   442  ;				(2)Take out check_mem call_pal.
                  [000000]   443  ;				(3)In enter console, add mm_stat stall at the
                  [000000]   444  ;					end to interlock everything.
                  [000000]   445  ; ES	1.36	25-Aug-98	Avoid speculative tag overwrite by holding it
                  [000000]   446  ;					up until previous PTE write retires.
                  [000000]   447  ;					Keeping the tag and PTE write in a
                  [000000]   448  ;					fetch block holds up speculative
                  [000000]   449  ;					set in the mapper, but add insurance
                  [000000]   450  ;					with scoreboard bits. The ALIGN
                  [000000]   451  ;					macro is marked with 1.36.
                  [000000]   452  ;				Also take cycle counts out of miss flows.
                  [000000]   453  ; ES	1.37	27-Aug-98	Urti -- take pc from stack_pc on illop because
                  [000000]   454  ;					a miss to the stack steps on p23.
                  [000000]   455  ;					Also take out stq to clear lock because
                  [000000]   456  ;					the loads will take care of it.
                  [000000]   457  ; ES	1.38	08-Sep-98	(1)Wrperfmon -- add subfunctions fo
                  [000000]   458  ;					profileme.
                  [000000]   459  ;					Eliminate return status in r0<0>.
                  [000000]   460  ;					Add some waits for retires (though it
                  [000000]   461  ;					probably doesn't really matter).
                  [000000]   462  ;					Change how nibbles are zapped on
                  [000000]   463  ;					disable.
                  [000000]   464  ;				(2)Explicitly define i_stat tpe and dpe 2.3
                  [000000]   465  ;					bits since they are no longer in
                  [000000]   466  ;					ev6_defs.
                  [000000]   467  ; ES	1.39	16-Sep-98	On a sequence of virtual operations, allow for
                  [000000]   468  ;				misses on each reference even if they are to
                  [000000]   469  ;				the same page. The virtual references can start
                  [000000]   470  ;				after the issue of an unrelated MTPR PTE/TAG
                  [000000]   471  ;				set, and have its tb entry kicked out when
                  [000000]   472  ;				the MTPR PTE/TAG retires. Marked with 1.39.
                  [000000]   473  ;				Affects in ev6_osf_pal:	fen, unalign,
                  [000000]   474  ;				  invalid_dpte, dfault, opcdec, iacv,
                  [000000]   475  ;				  invalid_ipte, arith, bpt, call_sys, urti, rti
                  [000000]   476  ;				Affects in ev6_osf_system_pal: int_post
                  [000000]   477  ; ES	1.40	22-Sep-98	On an mp system, the other cpu can mark PTEs
                  [000000]   478  ;				with fault bits to indicate they are LRU
                  [000000]   479  ;				candidates in the VM handler. So we have
                  [000000]   480  ;				to ensure that we see the same PTE throughout
                  [000000]   481  ;				the entire urti operation by doing a
                  [000000]   482  ;				scoreboard stall at the beginning. This
                  [000000]   483  ;				shouldn't be a problem with the kernel stack
                  [000000]   484  ;				operations.
                  [000000]   485  ; ES	1.41	21-Oct-98	(1)In trap__mchk, add some code that helps
                  [000000]   486  ;				eliminate double mchk's.
                  [000000]   487  ;				(2)In trap__mchk, fix flow in internally
                  [000000]   488  ;				detected bugchecks. Had a couple bugs
                  [000000]   489  ;				from rework of mchk a while back.
                  [000000]   490  ;				(3)On istream mchk, check on cmov at pc-4 and
                  [000000]   491  ;				punt if so. Bug in EV6 -- the cmov may or
                  [000000]   492  ;				may not have been executed.
                  [000000]   493  ;				(4)STx_C erroneous succeed problem -- A
                  [000000]   494  ;				ldx_l/stx_c sequence with an exception
                  [000000]   495  ;				in the middle that doesn't do a virtual
                  [000000]   496  ;				operation (which breaks the lock) and that
                  [000000]   497  ;				can have unknown bad path code that pulls back
                  [000000]   498  ;				in the locked block after it has been
                  [000000]   499  ;				pulled away from another processor. Fixed
                  [000000]   500  ;				as I100 in ev67, where a hw_ret mispredict
                  [000000]   501  ;				will cause the lock to be cleared. Handled here
                  [000000]   502  ;				with FORCE_PATH conditional in the
                  [000000]   503  ;				following locations:
                  [000000]   504  ;					dtb single miss
                  [000000]   505  ;					itb single miss
                  [000000]   506  ;					dtb double miss
                  [000000]   507  ;					interrupt passive release
                  [000000]   508  ;					crd passive relesae
                  [000000]   509  ;				Fixed with a hw_jmp followed by a
                  [000000]   510  ;					infinite loop branch in the
                  [000000]   511  ;					same fetch block. None of the
                  [000000]   512  ;					various type of predictors will
                  [000000]   513  ;					predict other than back to the jmp,
                  [000000]   514  ;					allowing no bad path code.
                  [000000]   515  ;				(4)In sys__reset and sys__enter_console, get
                  [000000]   516  ;					ipl31 from ipl table.
                  [000000]   517  ;				(5)In sys__enter_console, add some NOPs.
                  [000000]   518  ;				(6)In sys__reset, add write to hw_int_clr
                  [000000]   519  ;					for perf counter restriction.
                  [000000]   520  ; ES	1.42	04-Nov-98	(1)In ev6_vms_system_pal, change
                  [000000]   521  ;					assume_fetch_block <...> to
                  [000000]   522  ;					align_fetch_block <...>.
                  [000000]   523  ;				(3)In force_path hack, use pvc_violate <1008>
                  [000000]   524  ;					on all but 1 of each branch to
                  [000000]   525  ;					sys__cbox and sys__crd_scrub. The
                  [000000]   526  ;					pvc label skips the branch on goes
                  [000000]   527  ;					on to the next instruction. This will
                  [000000]   528  ;					speed up pvc considerably.
                  [000000]   529  ; ES	1.43	09-Nov-98	Make the new pvc happy with pvc_violate <1008>
                  [000000]   530  ;					sections by enforcing ipr operations
                  [000000]   531  ;					in different fetch blocks.
                  [000000]   532  ; ES	1.44	24-Nov-98	New force_path2 hack. Leave force_path=0.
                  [000000]   533  ;				ITB_MISS -- do a new hack
                  [000000]   534  ;					to force mispredict before a load
                  [000000]   535  ;					can fire off
                  [000000]   536  ;				DTB_MISS -- do a ldbu hack
                  [000000]   537  ;				DOUBLE -- do the new hack
                  [000000]   538  ;				1to1 mapping cases -- ignore
                  [000000]   539  ;				interrupt dismiss -- do the new hack
                  [000000]   540  ;
                  [000000]   541  ;				Also, minor fix in trap__ldvpte_dfault
                  [000000]   542  ; ES	1.45	16-Dec-98	Only do ldbu on force_path2 hack if
                  [000000]   543  ;				gh !=0. If gh !=0, we DON'T HIT OFF
                  [000000]   544  ;				the holding latch EVEN THOUGH WE HAVE
                  [000000]   545  ;				BEEN ALLOWED TO ISSUE -- thus the ldbu
                  [000000]   546  ;				takes a corrupting tb miss.
                  [000000]   547  ; ES	1.46	11-Jan-99	Development version.
                  [000000]   548  ; ES	1.47	12-Jan-99	(1)On call_pals, ev6 erroneously pushes
                  [000000]   549  ;				the prediction stack twice.
                  [000000]   550  ;				Add add_extra_ret conditional that
                  [000000]   551  ;				adds extra ret to call_pal macro, but
                  [000000]   552  ;				leave it turned off. If the stack is not
                  [000000]   553  ;				deep, the mispredict that it causes
                  [000000]   554  ;				is more harmful. We leave it around for
                  [000000]   555  ;				documentation of the problem.
                  [000000]   556  ;				(2)Fix comments on 2.3 perfmon.
                  [000000]   557  ;				Retired branch mispredicts are not
                  [000000]   558  ;				counted.
                  [000000]   559  ; ES	1.48	08-Mar-99	New PALcode restriction. On writing any
                  [000000]   560  ;				ebox ipr (va_ctl,cc,cc_ctl), it is necessary
                  [000000]   561  ;				to force its retire before any close-in-
                  [000000]   562  ;				program-order mispredict from a branch,
                  [000000]   563  ;				hw_ret_stall, or dtb miss.
                  [000000]   564  ;				The younger mispredict can actually stop the
                  [000000]   565  ;				ipr write even though the instruction is older
                  [000000]   566  ;				and retires.
                  [000000]   567  ; ES	1.49	12-Mar-99	Add double branch to ldbu hack in order
                  [000000]   568  ;				to avoid speculative issue of ldbu, which
                  [000000]   569  ;				causes the exact problem we are trying
                  [000000]   570  ;				to fix. As long are we are there,
                  [000000]   571  ;				conditionalize the d1to1 check to
                  [000000]   572  ;				compact the code.
                  [000000]   573  ; ES	1.50	09-Apr-99	(1)Ldbu hack enhanced once last time.
                  [000000]   574  ;				(2)Eliminate hw_jmp in sys__cbox.
                  [000000]   575  ;-
                  [000000]   576  	vmaj = 1
                  [000000]   577  	vmin = 50
                  [000000]   578  	vms_pal = 1
                  [000000]   579  	osf_pal = 2
                  [000000]   580  	pal_type = osf_pal
                  [000000]   581  	osfpal_version_l = <<pal_type@16> ! <vmaj@8> ! <vmin@0>>
                  [000000]   582  ;
                  [000000]   583  ; EV6 hardware definitions
                  [000000]   584  ;
                  [000000]   585  	PAL_SHADOW_DEFS
                  [000000]   586  	MCES_DEFS
                  [000000]   587  	MM_DEFS
                  [000000]   588  	MM_STAT_DEFS
                  [000000]   589  	HALT_DEFS
                  [000000]   590  	MCHK_DEFS
                  [000000]   591  	CBOX_IPR_DEFS
                  [000000]   592  ;
                  [000000]   593  ; OSF definitions
                  [000000]   594  ;
                  [000000]   595  	OSFPAL_FUNC_DEFS
                  [000000]   596  	OSF_PTE_DEFS
                  [000000]   597  	OSF_P_MISC_DEFS
                  [000000]   598  	OSF_PS_DEFS
                  [000000]   599  	OSF_SCB_DEFS
                  [000000]   600  	OSF_PCB_DEFS
                  [000000]   601  	OSF_FRM_DEFS
                  [000000]   602  	OSF_A0_DEFS
                  [000000]   603  	OSF_MMCSR_DEFS
                  [000000]   604  	OSF_IPL_DEFS
                  [000000]   605  
                  [000000]   606  ; Configuration options
                  [000000]   607  ;
                  [000000]   608  .iif ndf ev6_p1, ev6_p1 = 0
                  [000000]   608I  ev6_p1 = 0
                  [000000]   609  .iif ndf ev6_p2, ev6_p2 = 1
                  [000000]   609I  ev6_p2 = 1
                  [000000]   610  ;
                  [000000]   611  ; Pass 3 chips will work with ev6_p2. The ev6_p3 definition just changes
                  [000000]   612  ; some I_STAT definitions, but it will not affect functionality.
                  [000000]   613  ;
                  [000000]   614  .iif ndf ev6_p3, ev6_p3 = 0
                  [000000]   614I  ev6_p3 = 0
                  [000000]   615  
                  [000000]   616  ASSUME <ev6_p1+ev6_p2+ev6_p3> eq 1
                  [000000]   617  
                  [000000]   618  .iif ndf osfpal, osfpal = 1
                  [000000]   619  .iif ndf beh_model, beh_model = 0
                  [000000]   620  .iif ndf focus, focus = 0
                  [000000]   621  .iif ndf srom, srom = 1
                  [000000]   622  .iif ndf srm_console, srm_console = 1
                  [000000]   623  .iif ndf reference_platform, reference_platform = 0
                  [000000]   624  .iif ndf pte_eco, pte_eco = 1
                  [000000]   624I  pte_eco = 1
                  [000000]   625  .iif ndf check_interrupt_pending, check_interrupt_pending = 0
                  [000000]   626  .iif ndf dbm_serial_io, dbm_serial_io = 0
                  [000000]   627  
                  [000000]   628  .iif ndf va_48, va_48 = 0
                  [000000]   629  .iif ndf tb_mb_en, tb_mb_en = 0
                  [000000]   629I  tb_mb_en = 0
                  [000000]   630  .iif ndf mchk_en, mchk_en = 1
                  [000000]   631  .iif ndf fp_count, fp_count = 0
                  [000000]   631I  fp_count = 0
                  [000000]   632  .iif ndf clrmap, clrmap = 0
                  [000000]   633  .iif ndf force_ecc, force_ecc = 0
                  [000000]   634  .iif ndf force_multi_issue, force_multi_issue = 0
                  [000000]   634I  force_multi_issue = 0
                  [000000]   635  .iif ndf kseg_hack, kseg_hack = 0
                  [000000]   636  .iif ndf spinlock_hack, spinlock_hack = 0		; 1.41
                  [000000]   636I  spinlock_hack = 0		; 1.41
                  [000000]   637  ;
                  [000000]   638  ; Turn off force_path. Use force_path2 conditionally.		; 1.44
                  [000000]   639  ;
                  [000000]   640  force_path = 0							; 1.44
                  [000000]   641  .iif ndf force_path2, force_path2 = 0				; 1.44
                  [000000]   641I  force_path2 = 0				; 1.44
                  [000000]   642  
                  [000000]   643  
                  [000000]   644  .if ne ev6_p1
                  [000000]   645  	.iif ndf dcache_set_en, dcache_set_en = 1
                  [000000]   646  .iff
                  [000000]   647  	.iif ndf dcache_set_en, dcache_set_en = 3
                  [000000]   648  .endc
                  [000000]   647I 	.iif ndf dcache_set_en, dcache_set_en = 3
                  [000000]   647I  dcache_set_en = 3
                  [000000]   649  
                  [000000]   650  .if ndf	max_cpuid
                  [000000]   651  	max_cpuid = 2
                  [000000]   652  .endc
                  [000000]   651I 	max_cpuid = 2
                  [000000]   653  .if ndf	osf_svmin		; platform specific palcode version number
                  [000000]   654  	osf_svmin = 0
                  [000000]   655  .endc
                  [000000]   654I 	osf_svmin = 0
                  [000000]   656  
                  [000000]   657  osfpal_version_h = <<max_cpuid@16> ! <osf_svmin@0>>
                  [000000]   658  
                  [000000]   659  ;
                  [000000]   660  ; EV6 shadow register usage 
                  [000000]   661  ;
                  [000000]   662  ;	p4	= p4	reserved for itb/dtb miss
                  [000000]   663  ;	p5	= p5	reserved for itb/dtb miss
                  [000000]   664  ;	p6	= p6	reserved for itb/dtb miss
                  [000000]   665  ;	p7	= p7	reserved for itb/dtb miss
                  [000000]   666  ;
                  [000000]   667  ;	p20	= r20	reserved for call_pal and non-miss handling routines
                  [000000]   668  ;	p21	= r21	address of pal temps in memory (p_temp)
                  [000000]   669  ;	p22	= r22	p_misc (phys_mode in <63> and ps in <15:0>)
                  [000000]   670  ;	p23	= r23	call_pal linkage register
                  [000000]   671  ;
                  [000000]   672  
                  [000000]   673  ;
                  [000000]   674  ; Notes on speculative execution, non-renamed hardware registers, and
                  [000000]   675  ; branch prediction.
                  [000000]   676  ;
                  [000000]   677  ; EXC_ADDR, IVA_FORM, EXC_SUM, VA_FORM, VA, MM_STAT are sourced by
                  [000000]   678  ; non-renamed hardware registers that need to be available for subsequent traps.
                  [000000]   679  ; Hardware protects the values from overwrite for the first fetch block
                  [000000]   680  ; (4 instructions) of a pal flow. During this fetch block, the PALcode should
                  [000000]   681  ; save whatever registers it will need.
                  [000000]   682  ;
                  [000000]   683  ; In addition, VA, VA_FORM, DC_CTL and MM_STAT can have issue order problems
                  [000000]   684  ; with subsequent loads that issue out of order in respect to the mxfr from/to
                  [000000]   685  ; these registers. A MB before the load can be used to enforce the issue order.
                  [000000]   686  ; 
                  [000000]   687  ; Note that branch prediction is turned off in PALmode. The fall-through
                  [000000]   688  ; path should be the common path. Also note that in the exception flows,
                  [000000]   689  ; it takes a fetch block to turn off branch prediction, so therefore
                  [000000]   690  ; there should be no conditional branches in the first fetch block.
                  [000000]   691  ;
                  [000000]   692  ; We can also use this fact to help us avoid the overwrite problems
                  [000000]   693  ; For example, a dismiss ofa dtb miss is down a branch path, and thus is not
                  [000000]   694  ; speculatively issued. If the taken branch depends on these registers, we
                  [000000]   695  ; have enforced issue order.
                  [000000]   696  ;
                  [000000]   697  
                  [000000]   698  
                  [000000]   699  ;+
                  [000000]   700  ; SWITCH - offset 0
                  [000000]   701  ;
                  [000000]   702  ; Entry:
                  [000000]   703  ;	This entry is conditionalized for swap from vms palcode.
                  [000000]   704  
                  [000000]   705  ;	This entry could also be reached erroneously on a jump through 0.
                  [000000]   706  ;
                  [000000]   707  ; Entry on SWPPAL from VMS PALcode:
                  [000000]   708  ;	r17(a1)		new PC
                  [000000]   709  ;	r18(a2)		new PCBB
                  [000000]   710  ;	r19(a3)		new VPTB
                  [000000]   711  ;	p_misc		switch bit should be set
                  [000000]   712  ;	p_temp		valid
                  [000000]   713  ;
                  [000000]   714  ; Exit conditions on SWPPAL from VMS PALcode:
                  [000000]   715  ;	ASN		from PCB
                  [000000]   716  ;	FEN		from PCB
                  [000000]   717  ;	IPL		7
                  [000000]   718  ;	MCES		0 (should it be 8??)
                  [000000]   719  ;	PCBB		passed to SWPPAL
                  [000000]   720  ;	PC		passed to SWPPAL
                  [000000]   721  ;	PS		IPL=7, CM=K
                  [000000]   722  ;	PTBR		from PCB
                  [000000]   723  ;	Unique		from PCB
                  [000000]   724  ;	WHAMI		unchanged
                  [000000]   725  ;	Sysvalue	unchanged
                  [000000]   726  ;	KSP		from PCB
                  [000000]   727  ;	r0		0
                  [000000]   728  ;	other IPRs	UNPREDICTABLE
                  [000000]   729  ;	other rx,fx	UNPREDICTABLE except r0 and r30
                  [000000]   730  ;-
                  [000000]   731  .if ne srm_console
                  [000000]   732  
                  [000000]   733  	EV6__SWITCH_ENTRY = ^x0
                  [000000]   734  
                  [000000]   735  TRAP__START:					; used by vector macros
                  [000000]   736  trap__pal_base:
                  [000000]   737  
                  [000000]   738  	START_HW_VECTOR <SWITCH>
                  [000000]   739  
                  [000000]   740  	srl	p_misc, #OSF_P_MISC__SWITCH__S, r1	; check the switch bit
                  [000000]   741  	br	r31, trap__check_switch
                  [000000]   742  
                  [000000]   743  	.long	osfpal_version_l			; location 0x8
                  [000000]   744  	.long	osfpal_version_h			; location 0xC
                  [000000]   745  
                  [000000]   746  trap__check_switch:
                  [000000]   747  	blbc	r1, sys__switch_unknown			; jumped through 0
                  [000000]   748  	br	r31, trap__switch_base			; been switched
                  [000000]   749  
                  [000000]   750  	.align	quad
                  [000000]   751  trap__lock_cell:
                  [000000]   752  	.quad	0
                  [000000]   753  
                  [000000]   754  	CONT_HW_VECTOR				; continue in free space
                  [000000]   755  
                  [000000]   756  ;
                  [000000]   757  ; Init and w1c values
                  [000000]   758  ;
                  [000000]   759  	EV6__I_STAT__TPE__S = ^x1d
                  [000000]   760  	EV6__I_STAT__DPE__S = ^x1e
                  [000000]   761  
                  [000000]   762  	EV6__I_STAT__W1C = -
                  [000000]   763  		<<1@EV6__I_STAT__TPE__S> ! -
                  [000000]   764  		<1@EV6__I_STAT__DPE__S>>
                  [000000]   765  
                  [000000]   766  	EV6__DC_STAT__W1C = -
                  [000000]   767  		<<1@EV6__DC_STAT__TPERR_P0__S> ! -
                  [000000]   768  		<1@EV6__DC_STAT__TPERR_P1__S> ! -
                  [000000]   769  		<1@EV6__DC_STAT__ECC_ERR_ST__S> ! -
                  [000000]   770  		<1@EV6__DC_STAT__ECC_ERR_LD__S> ! -
                  [000000]   771  		<1@EV6__DC_STAT__SEO__S>>
                  [000000]   772  
                  [000000]   773  	ASSUME EV6__HW_INT_CLR__MCHK_D__S lt EV6__HW_INT_CLR__PC__S 
                  [000000]   774  	ASSUME EV6__HW_INT_CLR__MCHK_D__S lt EV6__HW_INT_CLR__CR__S 
                  [000000]   775  	ASSUME EV6__HW_INT_CLR__MCHK_D__S lt EV6__HW_INT_CLR__SL__S 
                  [000000]   776  
                  [000000]   777  	EV6__HW_INT_CLR__INIT = -
                  [000000]   778  	    <<1@<EV6__HW_INT_CLR__MCHK_D__S - EV6__HW_INT_CLR__MCHK_D__S>> ! -
                  [000000]   779  	     <3@<EV6__HW_INT_CLR__PC__S - EV6__HW_INT_CLR__MCHK_D__S>> ! -
                  [000000]   780  	     <1@<EV6__HW_INT_CLR__CR__S - EV6__HW_INT_CLR__MCHK_D__S>> ! -
                  [000000]   781  	     <1@<EV6__HW_INT_CLR__SL__S - EV6__HW_INT_CLR__MCHK_D__S>>>
                  [000000]   782  
                  [000000]   783  	EV6__IER__INIT = 0
                  [000000]   784  
                  [000000]   785  ;
                  [000000]   786  ; Do the intialization. We rely on fetch blocks to separate scoreboard bits!!!
                  [000000]   787  ;
                  [000000]   788  	ALIGN_FETCH_BLOCK
                  [000000]   789  
                  [000000]   790  trap__switch_base:
                  [000000]   791  	br	r1, trap__switch_get_pal_base
                  [000000]   792  trap__switch_get_pal_base:
                  [000000]   793  	GET_32ADDR r1, <trap__pal_base - trap__switch_get_pal_base>, r1
                  [000000]   794  	hw_mtpr	r1, EV6__PAL_BASE			; (4,0L) pal base
                  [000000]   795  
                  [000000]   796  	hw_mtpr	r31, EV6__ITB_IA			; (4,0L) flush ITB
                  [000000]   797  	hw_mtpr	r31, EV6__DTB_IA			; (7,0L) flush DTB
                  [000000]   798  	GET_32CONS 	r1, EV6__I_STAT__W1C, r31	; get i_stat clr value
                  [000000]   799  
                  [000000]   800  	GET_16CONS	R3, EV6__DC_STAT__W1C, R31	; get dc_stat clr value
                  [000000]   801  	hw_mtpr	r1, EV6__I_STAT				; (4,0L) w1c I_STAT
                  [000000]   802  	hw_mtpr r3, EV6__DC_STAT			; (6,0L) w1c DC_STAT
                  [000000]   803  	rc	r31					; clear intr_flag
                  [000000]   804  
                  [000000]   805  	GET_32CONS	r1, EV6__IER__INIT, r31 
                  [000000]   806  	hw_mtpr	r1, EV6__IER_CM				; (4,0L) clear ier_cm
                  [000000]   807  	hw_mtpr	r31, EV6__DTB_ALT_MODE			; (6,0L) clear alt_mode
                  [000000]   808  
                  [000000]   809  	hw_stq/p r31, PT__DTB_ALT_MODE(p_temp)		; clear alt_mode temp
                  [000000]   810  	zapnot	p_misc, #4, p_misc			; zap all but mces
                  [000000]   811  	bis	p_misc, #7, p_misc			; cm=0,ipl=7
                  [000000]   812  	hw_mtpr	r31, EV6__SIRR				; (4,0L) Clear int req
                  [000000]   813  	
                  [000000]   814  	GET_16CONS	r1, EV6__HW_INT_CLR__INIT, r31
                  [000000]   815  	sll	r1, #EV6__HW_INT_CLR__MCHK_D__S, r1	; move into position
                  [000000]   816  	PVC_VIOLATE <35>				;
                  [000000]   817  	hw_mtpr	r1, EV6__HW_INT_CLR			; (4,0L) Clear int req
                  [000000]   818  	NOP						; pad fetch block
                  [000000]   819  ;
                  [000000]   820  ; Current state:
                  [000000]   821  ;	r17 (a1)	new PC
                  [000000]   822  ;	r18 (a2)	new PCBB
                  [000000]   823  ;	r19 (a3)	new VPTB
                  [000000]   824  ;
                  [000000]   825  	hw_ldq/p p4, OSF_PCB__FEN(r18)		; get new fen/pme
                  [000000]   826  	hw_ldl/p p5, OSF_PCB__CPC(r18)		; get charged cycle counter
                  [000000]   827  	hw_ldl/p p6, OSF_PCB__ASN(r18)		; get new asn
                  [000000]   828  	hw_ldq/p p7, OSF_PCB__PTBR(r18)		; get new ptbr
                  [000000]   829  
                  [000000]   830  	sll	p7, #page_offset_size_bits, p7	; convert pfn to pa
                  [000000]   831  	hw_stq/p p7, PT__PTBR(p_temp)		; store PTBR
                  [000000]   832  	hw_stq/p r18, PT__PCBB(p_temp)		; store PCBB
                  [000000]   833  	bic	r17, #3, p23			; clean PC to p23
                  [000000]   834  ;
                  [000000]   835  ; Initialize VA_CTL with new VPTB value and saved control value.
                  [000000]   836  ; Store VPTB in PT__VPTB in pal temps area.
                  [000000]   837  ; Initialize M_CTL based on VA_48, and save it away.
                  [000000]   838  ; Set up initialization of I_CTL, with VPTB, old control value, and
                  [000000]   839  ;		SPE based on VA_48.
                  [000000]   840  ;
                  [000000]   841  	hw_ldq/p r1, PT__VA_CTL(p_temp)		; get control part
                  [000000]   842  	hw_stq/p r19, PT__VPTB(p_temp)		; store vptb base part
                  [000000]   843  	bis	r1, r19, r1			; or in vptb part
                  [000000]   844  	hw_mtpr	r1, EV6__VA_CTL			; (5,1L)
                  [000000]   845  
                  [000000]   846  	hw_mfpr	r1, EV6__I_CTL			; (4,0L) read I_CTL
                  [000000]   847  	lda	p4, 2(r31)			; get SPE<1> bit
                  [000000]   848  	srl	r1, #EV6__I_CTL__VA_48__S, r3	; get VA_48 bit
                  [000000]   849  	and	r3, #1, r3			; r3=1 -> VA_48
                  [000000]   850  
                  [000000]   851  	sll	p4, r3, p4			; shift to SPE<2> if VA_48
                  [000000]   852  	sll	p4, #EV6__M_CTL__SPE__S, r3	; shift into M_CTL position
                  [000000]   853  .if ne kseg_hack				; kseg hack
                  [000000]   854  	hw_mtpr	r31, EV6__M_CTL			; kseg hack
                  [000000]   855  	hw_stq/p r31, PT__M_CTL(p_temp)		; kseg hack
                  [000000]   856  .iff
                  [000000]   857  	hw_mtpr	r3, EV6__M_CTL			; (6,0L) write M_CTL
                  [000000]   858  	hw_stq/p r3, PT__M_CTL(p_temp)		; save away
                  [000000]   859  .endc
                  [000000]   860  
                  [000000]   861  	sll	p4, #EV6__I_CTL__SPE__S, r3	; shift into I_CTL position
                  [000000]   862  	bis	r1, r3, r1			; or into I_CTL
                  [000000]   863  	sll	r1, #<64 - EV6__I_CTL__VPTB__S>, r1	; clean VPTB
                  [000000]   864  	srl	r1, #<64 - EV6__I_CTL__VPTB__S>, r1	; clean VPTB
                  [000000]   865  
                  [000000]   866  	bis	r1, r19, r1			; or in new VPTB
                  [000000]   867  
                  [000000]   868  .if ne force_multi_issue
                  [000000]   869  	lda	p7, 1(r31)				; get a 1
                  [000000]   870  	sll	p7, #EV6__I_CTL__SINGLE_ISSUE__S, p7	; into position
                  [000000]   871  	bic	r1, p7, r1				; clear single issue
                  [000000]   872  .endc
                  [000000]   873  
                  [000000]   874  ;
                  [000000]   875  ; Initialize I_CTL. Write it twice (pvc #31).
                  [000000]   876  ;
                  [000000]   877  
                  [000000]   878  	hw_mtpr	r1, EV6__I_CTL				; (4,0L) write I_CTL
                  [000000]   879  	bis	r31, r31, r31
                  [000000]   880  	bis	r31, r31, r31
                  [000000]   881  	bis	r31, r31, r31
                  [000000]   882  
                  [000000]   883  	hw_mtpr	r1, EV6__I_CTL				; (4,0L) write I_CTL
                  [000000]   884  ;
                  [000000]   885  ; Do USP and KSP
                  [000000]   886  ;
                  [000000]   887  	hw_ldq/p r30, OSF_PCB__USP(r18)		; get new USP
                  [000000]   888  	hw_stq/p r30, PT__USP(p_temp)		; save it away
                  [000000]   889  	hw_ldq/p r30, OSF_PCB__KSP(r18)		; get KSP
                  [000000]   890  ;
                  [000000]   891  ; Now do DTB_ASNx.
                  [000000]   892  ;
                  [000000]   893  ; There must be a scoreboard bit -> register dependency chain to prevent
                  [000000]   894  ; hw_mtpr DTB_ASx from issuing while ANY of scoreboard bits <7:4> are set.
                  [000000]   895  ;
                  [000000]   896  ; Current state:
                  [000000]   897  ;	p6	ASN
                  [000000]   898  ;
                  [000000]   899  ASSUME OSF_PCB__ASN__M eq ^xFF
                  [000000]   900  
                  [000000]   901  	and	p6, #OSF_PCB__ASN__M, p6	; clean ASN quadword
                  [000000]   902  	sll	p6, #EV6__DTB_ASN0__ASN__S, p20	; ASN into mbox spot
                  [000000]   903  
                  [000000]   904  	hw_mfpr	p7, <EV6__PAL_BASE ! ^xF0>	; (4-7, 0L)
                  [000000]   905  	xor	p7, p7, p7			; zap p7
                  [000000]   906  	bis	p7, p20, p20			; force register dependency
                  [000000]   907  	bis	r31, r31, r31
                  [000000]   908  	hw_mtpr	p20, EV6__DTB_ASN0		; (4,0L)
                  [000000]   909  	hw_mtpr	p20, EV6__DTB_ASN1		; (7,1L)
                  [000000]   910  ;
                  [000000]   911  ; Create Ibox Process Context IPR.
                  [000000]   912  ; Fill in ASN, FPE, clearing ASTEN, ASTRR, PPCE.
                  [000000]   913  ;
                  [000000]   914  ; Current state:
                  [000000]   915  ;	p4	fen/pme quadword
                  [000000]   916  ;	p5	cpc
                  [000000]   917  ;	p6	asn
                  [000000]   918  ;	p23	new pc
                  [000000]   919  ;
                  [000000]   920  	sll	p6, #EV6__PROCESS_CONTEXT__ASN__S, p6	; shift asn into place
                  [000000]   921  	and	p4, #1, p4				; get just the fen bit
                  [000000]   922  	sll	p4, #EV6__PROCESS_CONTEXT__FPE__S, p7	; shift fpe into place
                  [000000]   923  	bis	p7, p6, p7				; or together
                  [000000]   924  	hw_mtpr	p7, EV6__PROCESS_CONTEXT		; (4,0L) write them
                  [000000]   925  
                  [000000]   926  .if ne ev6_p1
                  [000000]   927  	hw_ldq/p p7, PT__IMPURE(p_temp)			; get impure pointer
                  [000000]   928  	hw_stq/p p4, CNS__FPE_STATE(p7)			; write FPE_STATE
                  [000000]   929      .if ne fp_count
                  [000000]   930  	hw_stq/p r31, PT__RSV_FOR_PAL(p_temp)		; clear counter
                  [000000]   931      .endc
                  [000000]   932  .endc
                  [000000]   933  
                  [000000]   934  ;
                  [000000]   935  ; Do the cycle counter
                  [000000]   936  ; Not sure we need this, but ensure 4-7 clear before any dtb writes.
                  [000000]   937  ; Current state:
                  [000000]   938  ;	p5		CPC from PCB
                  [000000]   939  
                  [000000]   940  	rpcc	r1				; get cycle counter
                  [000000]   941  	subl	p5, r1, r1			; gen new offset
                  [000000]   942  	insll	r1, #4, r1			; shift left 32
                  [000000]   943  	hw_mtpr r1, <EV6__CC ! ^xF0>		; (4-7,1L) write it
                  [000000]   944  	bis	r31, r31, r31
                  [000000]   945  	bis	r31, r31, r31
                  [000000]   946  	bis	r31, r31, r31
                  [000000]   947  ;
                  [000000]   948  ; Now we need to clear the lock flag, which must be done with a LDQ
                  [000000]   949  ; So we need to set up the DTB, do the write, and re-clear the DTB.
                  [000000]   950  ;
                  [000000]   951  ; Write the dtb, do the reference, and then clear the dtb.
                  [000000]   952  ;
                  [000000]   953  	hw_mfpr	r1, EV6__PAL_BASE		; (4,0L) get pal base back
                  [000000]   954  	sll	r1, #<32-13>, r2		; shift into position
                  [000000]   955  	lda	r3, ^x1101(r31)			; set KWE, KRE
                  [000000]   956  	or	r2, r3, r2			; produce pte
                  [000000]   957  
                  [000000]   958  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
                  [000000]   959  
                  [000000]   960  	PVC_VIOLATE <2>				; ignore scoreboard violation
                  [000000]   961  	hw_mtpr	r1, EV6__DTB_TAG0		; (2&6,0L) write tag0
                  [000000]   962  	hw_mtpr r1, EV6__DTB_TAG1		; (1&5,1L) write tag1
                  [000000]   963  	hw_mtpr	r2, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
                  [000000]   964  	hw_mtpr	r2, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [000000]   965  ;
                  [000000]   966  ; Do the unlock.
                  [000000]   967  ;
                  [000000]   968  	ALIGN_FETCH_BLOCK <^x47FF041F>
                  [000000]   969  	ldq	r31, <trap__lock_cell - trap__pal_base>(r1)
                  [000000]   970  ;
                  [000000]   971  ; Now clear the dtb again. The stall at the end will do the
                  [000000]   972  ; necessary synchronization.
                  [000000]   973  ;
                  [000000]   974  	hw_mtpr	r31, EV6__DTB_IA		; (7,0L)
                  [000000]   975  ;
                  [000000]   976  ; Mark success, flush icache, and hw_ret_stall to pc.
                  [000000]   977  ;
                  [000000]   978  	or	r31, r31, r0			; success
                  [000000]   979  	hw_mtpr	r31, EV6__IC_FLUSH		; (4,0L) flush icache
                  [000000]   980  	bne	r31, .				; pvc #24
                  [000000]   981  	hw_ret_stall (p23)			; switch complete
                  [000000]   982  
                  [000000]   983  	END_HW_VECTOR
                  [000000]   984  
                  [000000]   985  .endc ; if ne srm_console
                  [000000]   986  
                  [000000]   987  
                  [000000]   988  ;+
                  [000000]   989  ; POWERUP - offset 0
                  [000000]   990  ;
                  [000000]   991  ; Entry:
                  [000000]   992  ;	This entry is conditionalized for jump from SROM code
                  [000000]   993  ;	on non-SRM console systems.
                  [000000]   994  ;
                  [000000]   995  ;	Jumped to by the SROM code on reset. Vector 780 will be used for
                  [000000]   996  ;	wakeup. It is assumed that the retirator, the integer/floating
                  [000000]   997  ;	map, and the shadow registers have been initialized.
                  [000000]   998  ;
                  [000000]   999  ; Reference platform standard:
                  [000000]  1000  ;	r0 - r5		chip specific srom parameters
                  [000000]  1001  ;	r15 - r21 	standard srom parameters (even though
                  [000000]  1002  ;			it steps on shadow set)
                  [000000]  1003  ;-
                  [000000]  1004  .if eq srm_console
                  [000000]  1005  
                  [000000]  1006  	EV6__POWERUP_ENTRY = ^x0
                  [000000]  1007  TRAP__START:					; used by vector macros
                  [000000]  1008  trap__pal_base:
                  [000000]  1009  	START_HW_VECTOR <POWERUP>
                  [000000]  1010  
                  [000000]  1011  	br	r26, sys__reset			; off to sys__reset
                  [000000]  1012  
                  [000000]  1013  	.long	0
                  [000000]  1014  	.long	osfpal_version_l			; location 0x8
                  [000000]  1015  	.long	osfpal_version_h			; location 0xC
                  [000000]  1016  
                  [000000]  1017  	.align	quad
                  [000000]  1018  trap__lock_cell:
                  [000000]  1019  	.quad	0
                  [000000]  1020  
                  [000000]  1021  	END_HW_VECTOR
                  [000000]  1022  
                  [000000]  1023  .endc ; if eq srm_console
                  [000000]  1005I 
                  [000000]  1006I 	EV6__POWERUP_ENTRY = ^x0
                  [000000]  1007I TRAP__START:					; used by vector macros
                  [000000]  1008I trap__pal_base:
                  [000000]  1009I 	START_HW_VECTOR <POWERUP>
File: ev6_pal_macros.mar
                  [000000]    36i     ASSUME <_pal_func_in_prog> eq 0
                  [000000]    49i TRAP__POWERUP:
File: ev6_osf_pal.mar
                  [000000]  1010I 
         C34019BF [000000]  1011I 	br	r26, sys__reset			; off to sys__reset
                  [000004]  1012I 
         00000000 [000004]  1013I 	.long	0
         00020132 [000008]  1014I 	.long	osfpal_version_l			; location 0x8
         00020000 [00000C]  1015I 	.long	osfpal_version_h			; location 0xC
                  [000010]  1016I 
                  [000010]  1017I 	.align	quad
                  [000010]  1018I trap__lock_cell:
00000000 00000000 [000010]  1019I 	.quad	0
                  [000018]  1020I 
                  [000018]  1021I 	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [000018]    57i         ASSUME <.-_start_of_last_vec> le <^x80>
                  [000018]    61i         GOTO_FREE_CODE
                  [004000]    67i     .align 6
File: ev6_osf_pal.mar
                  [004000]  1022I 
                  [004000]  1024  
                  [004000]  1025  
                  [004000]  1026  ;+
                  [004000]  1027  ; DTBM_DOUBLE_3 - offset 100
                  [004000]  1028  ;
                  [004000]  1029  ; Entry:
                  [004000]  1030  ;	Vectored into via hardware trap on TB miss on level 3
                  [004000]  1031  ;	page table entry.
                  [004000]  1032  ;
                  [004000]  1033  ; Function:
                  [004000]  1034  ;	Translate level 3 PTE va.
                  [004000]  1035  ;	If valid, load TB and return to redo the ld_vpte, which will now hit.
                  [004000]  1036  ;	If not valid, then take TNV/ACV exception.
                  [004000]  1037  ;
                  [004000]  1038  ; Current state:
                  [004000]  1039  ;	p4	va of level 3 page table entry
                  [004000]  1040  ;	p5	mm_stat (from dtbm_single)
                  [004000]  1041  ;	p6	original va
                  [004000]  1042  ;	p7	exc_sum (from dtbm_single)
                  [004000]  1043  ;	p23	pc of instruction causing the TB miss
                  [004000]  1044  ;
                  [004000]  1045  ;	VA	original va for dstream TB miss
                  [004000]  1046  ;
                  [004000]  1047  ; Register Use:
                  [004000]  1048  ;	p5	exc_addr, pc of ld_vpte in TB miss flows
                  [004000]  1049  ;	p7	<31:16>=mm_stat<15:0>,<15:1>=exc_sum<15:1>,<0>=1
                  [004000]  1050  ;
                  [004000]  1051  ;	r25	saved, used as scratch, restored on hw_ret
                  [004000]  1052  ;	r26	saved, used as scratch, restored on hw_ret
                  [004000]  1053  ;
                  [004000]  1054  ; Exit state:
                  [004000]  1055  ;	On exit to trap__double3_pte_inv
                  [004000]  1056  ;	p5	scratch
                  [004000]  1057  ;	p6	original va
                  [004000]  1058  ;	p7	<31:16>=mm_stat<15:0>,<15:1>=exc_sum<15:1>,<0>=1
                  [004000]  1059  ;	p23	pc of instruction causing TB miss
                  [004000]  1060  ;	r25	pte
                  [004000]  1061  ;-
                  [004000]  1062  	START_HW_VECTOR <DTBM_DOUBLE_3>
File: ev6_pal_macros.mar
                  [004000]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000100]    49i TRAP__DTBM_DOUBLE_3:
File: ev6_osf_pal.mar
                  [000100]  1063  
                  [000100]  1064  ; Entered on a miss on va of level 3 page table entry
                  [000100]  1065  ; 	level 1 = vptb
                  [000100]  1066  ; 	level 2 = level 1 of original va
                  [000100]  1067  ; 	level 3 = level 2 of original va
                  [000100]  1068  ; byte_within_page = level 3 of original va as offset into level 3 page table
                  [000100]  1069  ;
                  [000100]  1070  ; Optimize by starting with the fetch of level 2 pte
                  [000100]  1071  ;
         48E07627 [000100]  1072  	zapnot	p7, #3, p7			; clean exc_sum to 16 bits
         48A21725 [000104]  1073  	sll	p5, #16, p5			; shift mm_stat into place
         44E50407 [000108]  1074  	bis	p7, p5, p7			; combine 
         64BF0600 [00010C]  1075  	hw_mfpr	p5, EV6__EXC_ADDR		; (0L) save exc_addr
                  [000110]  1076  
         44E03407 [000110]  1077  	bis	p7, #1, p7			; double miss flag
                  [000114]  1078  
         7F351118 [000114]  1079  	hw_stq/p r25, PT__R25(p_temp)		; get a scratch register
         7F551120 [000118]  1080  	hw_stq/p r26, PT__R26(p_temp)		; get a scratch register
         6F351008 [00011C]  1081  	hw_ldq/p r25, PT__PTBR(p_temp)		; get phys page table addr
                  [000120]  1082  
         EAC00FC4 [000120]  1083  	blt	p_misc, trap__double3_1to1	; 1-to-1 => branch
                  [000124]  1084  
         4883F73A [000124]  1085  	sll	p4, #<64-<<2*level_bits>+13>>, r26
         4B46769A [000128]  1086  	srl	r26, #<61-level_bits>, r26	; get level 2 into offset
         433A0419 [00012C]  1087  	addq	r25, r26, r25			; pa for level 2 pte
         6F391000 [000130]  1088  	hw_ldq/p r25, 0(r25)			; get level 2 pte
         4885373A [000134]  1089  	sll	p4, #<64-<<1*level_bits>+13>>, r26
         4B46769A [000138]  1090  	srl	r26, #<61-level_bits>, r26	; get level 3 into offset
         E3200FB6 [00013C]  1091  	blbc	r25, trap__double3_pte_inv	; branch => invalid pte
         4B241699 [000140]  1092  	srl	r25, #32, r25			; extract pfn from pte
         4B21B739 [000144]  1093  	sll	r25, #13, r25			; get into position
         433A0419 [000148]  1094  	addq	r25, r26, r25			; pa for level 3 pte
         6F391000 [00014C]  1095  	hw_ldq/p	r25, 0(r25)		; get level 3 pte
         E3200FB1 [000150]  1096  	blbc	r25, trap__double3_pte_inv	; branch => invalid pte
         4B20F69A [000154]  1097  	srl	r25, #7, r26			; get mb bit
                  [000158]  1098  
                  [000158]  1099  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
47FF041F 47FF041F [000158]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
                  [000160]  1100  
                  [000160]  1101  	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [000160]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         77E42044 [000160]  1102  	hw_mtpr	p4, EV6__DTB_TAG0		; (2&6,0L) write tag0
         77E4A022 [000164]  1103  	hw_mtpr p4, EV6__DTB_TAG1		; (1&5,1L) write tag1
         77F92155 [000168]  1104  	hw_mtpr	r25, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
         77F9A1AA [00016C]  1105  	hw_mtpr	r25, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [000170]  1106  
         6F351118 [000170]  1107  	hw_ldq/p r25, PT__R25(p_temp)		; restore register
                  [000174]  1108  ;
                  [000174]  1109  ; We need to wait until the pte writes retire. We need to avoid the
                  [000174]  1110  ; case where the tag writes in the single flow issue before the
                  [000174]  1111  ; pte writes in this flow issue and retire. With changes in 1.36, we
                  [000174]  1112  ; can probably remove this stall, but at this point in the project,
                  [000174]  1113  ; let's just leave it in.
                  [000174]  1114  ;
         77FF2780 [000174]  1115  	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; wait for pte write
                  [000178]  1116  
                  [000178]  1117  	CONT_HW_VECTOR <DTBM_DOUBLE_3>
File: ev6_pal_macros.mar
                  [000178]    76M     ASSUME <_pal_vec_cont> eq 0
         C3E00FA1 [000178]    81i 	br	r31, TRAP__DTBM_DOUBLE_3_CONT
                  [00017C]    84M                 ASSUME <.-_start_of_last_vec> le <^x80>
                  [00017C]    86M     GOTO_FREE_CODE
                  [004000]    67M     .align 6
                  [004000]    91i TRAP__DTBM_DOUBLE_3_CONT:
File: ev6_osf_pal.mar
                  [004000]  1118  
                  [004000]  1119  ASSUME <tb_mb_en + pte_eco> ne 2
                  [004000]  1120  
                  [004000]  1121  .if eq force_path2				; 1.44 force_path2 = 0
                  [004000]  1122  
                  [004000]  1123    .if ne pte_eco
                  [004000]  1124  	blbc	r26, trap__dtbm_double3_mb	; branch for mb
                  [004000]  1125  	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004000]  1126  	hw_ret	(p5)				; (0L) return
                  [004000]  1127  
                  [004000]  1128  trap__dtbm_double3_mb:
                  [004000]  1129  	mb
                  [004000]  1130  	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004000]  1131  	hw_ret	(p5)				; (0L) return
                  [004000]  1132    .iff
                  [004000]  1133  	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004000]  1134  	hw_ret	(p5)				; (0L) return
                  [004000]  1135    .endc						; pte_eco
                  [004000]  1136  
                  [004000]  1137  .iff						; force_path2 = 1
                  [004000]  1138  ;
                  [004000]  1139  ; We need to avoid the situation where a ldx_l has acquired a lock,
                  [004000]  1140  ; another processor has taken it, and a bad path before a stx_c has
                  [004000]  1141  ; a load which pulls the data back in and makes it look like the
                  [004000]  1142  ; lock has succeeded. Hold up loads by writing to MM_STAT with
                  [004000]  1143  ; scoreboard bit 2 (and 6 -- 6 is required or we hang).
                  [004000]  1144  ;
                  [004000]  1145  	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004000]  1146  	mb					; allow hw_ret to fire
                  [004000]  1147  
                  [004000]  1148  	ALIGN_FETCH_BLOCK <^x47FF041F>
                  [004000]  1149  	mulq	p6, #1, p6			; hold up loads
                  [004000]  1150  	mulq	p6, #1, p6			; hols up loads
                  [004000]  1151  	hw_mtpr p6, <EV6__MM_STAT ! ^x44>	; hold up loads
                  [004000]  1152  	hw_ret	(p5)				; return
                  [004000]  1153  .endc						; 1.44 force_path2
                  [004000]  1122I 
                  [004000]  1123I   .if ne pte_eco
                  [004000]  1124I 	blbc	r26, trap__dtbm_double3_mb	; branch for mb
                  [004000]  1125I 	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004000]  1126I 	hw_ret	(p5)				; (0L) return
                  [004000]  1127I 
                  [004000]  1128I trap__dtbm_double3_mb:
                  [004000]  1129I 	mb
                  [004000]  1130I 	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004000]  1131I 	hw_ret	(p5)				; (0L) return
                  [004000]  1132I   .iff
                  [004000]  1133I 	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004000]  1134I 	hw_ret	(p5)				; (0L) return
                  [004000]  1135I   .endc						; pte_eco
         E3400002 [004000]  1124I 	blbc	r26, trap__dtbm_double3_mb	; branch for mb
         6F551120 [004004]  1125I 	hw_ldq/p r26, PT__R26(p_temp)		; restore register
         7BE58000 [004008]  1126I 	hw_ret	(p5)				; (0L) return
                  [00400C]  1127I 
                  [00400C]  1128I trap__dtbm_double3_mb:
         63FF4000 [00400C]  1129I 	mb
         6F551120 [004010]  1130I 	hw_ldq/p r26, PT__R26(p_temp)		; restore register
         7BE58000 [004014]  1131I 	hw_ret	(p5)				; (0L) return
                  [004018]  1136I   
                  [004018]  1154  
                  [004018]  1155  
                  [004018]  1156  ;+
                  [004018]  1157  ; trap__double3_pte_inv
                  [004018]  1158  ;
                  [004018]  1159  ; Entry:
                  [004018]  1160  ; 	Double TB miss flow found an invalid level 2/3 page table entry,
                  [004018]  1161  ;	which is equivalent to invalid level 1/2 PTE of original va.
                  [004018]  1162  ;
                  [004018]  1163  ; Function:
                  [004018]  1164  ;	Prepare to take a TNV or ACV exception. Access violation takes
                  [004018]  1165  ;	priority over translation not valid. Return to single miss with
                  [004018]  1166  ;	fake PTE, and the invalid single miss flow will report the error.
                  [004018]  1167  ;
                  [004018]  1168  ; Current state:
                  [004018]  1169  ;	p4	available
                  [004018]  1170  ;	p5	pc of ld_vpte instruction in TB miss flow
                  [004018]  1171  ;	p6	original va
                  [004018]  1172  ;	p7	<31:16>=mm_stat<15:0>,<15:1>=exc_sum<15:1>,<0>=1
                  [004018]  1173  ;	p23	pc of instruction causing TB miss
                  [004018]  1174  ;
                  [004018]  1175  ;	r25	pte
                  [004018]  1176  ;	r26	scratch
                  [004018]  1177  ;
                  [004018]  1178  ;	PT__R25	saved r25
                  [004018]  1179  ;	PT__R26	saved r26
                  [004018]  1180  ;
                  [004018]  1181  ; Register use:
                  [004018]  1182  ;	p20	available if original exception not from pal
                  [004018]  1183  ;
                  [004018]  1184  ; Exit state:
                  [004018]  1185  ;	On exit back to single miss flow
                  [004018]  1186  ;	p4	PTE
                  [004018]  1187  ;	p5	scratch
                  [004018]  1188  ;	p7	<31:16>=mm_stat<15:0>,<15:1>=exc_sum<15:1>,<0>=1
                  [004018]  1189  ;	p23	pc of instruction taking TB miss
                  [004018]  1190  ;-
                  [004018]  1191  trap__double3_pte_inv:
         4B211699 [004018]  1192  	srl	r25, #OSF_PTE__KRE__S, r25	; get kre bit to <0>
         40A09405 [00401C]  1193  	addq	p5, #4, p5			; inc pc for return to single
         209F3300 [004020]  1194  	lda	p4, OSF_PTE__PROT__M(r31)	; UWE,KWE,URE,KRE set
         473F02C4 [004024]  1195  	cmovlbc	r25, r31, p4			; if <kre>=0 => ACV
                  [004028]  1196  
         6F351118 [004028]  1197  	hw_ldq/p r25, PT__R25(p_temp)		; restore r25
         6F551120 [00402C]  1198  	hw_ldq/p r26, PT__R26(p_temp)		; restore r26
                  [004030]  1199  
         7BE58000 [004030]  1200  	hw_ret	(p5)				; (0L) return
                  [004034]  1201  ;+
                  [004034]  1202  ; Do a 1-to-1 mapping
                  [004034]  1203  ; Current state:
                  [004034]  1204  ;	p5	exc_addr of ld_vpte
                  [004034]  1205  ;	r25	saved, needs to be restored
                  [004034]  1206  ;	r26	saved, needs to be restored
                  [004034]  1207  ;-
                  [004034]  1208  trap__double3_1to1:
         6F351118 [004034]  1209  	hw_ldq/p r25, PT__R25(p_temp)		; restore r25
         6F551120 [004038]  1210  	hw_ldq/p r26, PT__R26(p_temp)		; restore r26
         40A09405 [00403C]  1211  	addq	p5, #4, p5			; return past the ld_vpte
                  [004040]  1212  
                  [004040]  1213      .if eq force_path				; 1.41
                  [004040]  1214  	hw_ret	(p5)				; do the ret
                  [004040]  1215      .iff
                  [004040]  1216  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align
                  [004040]  1217  	PVC_VIOLATE <1007>
                  [004040]  1218  	PVC_VIOLATE <1020>			; stop permutation
                  [004040]  1219  	hw_jmp	(p5)				; return with jmp
                  [004040]  1220  	br	r31, .-4			; stop predictor
                  [004040]  1221      .endc					; 1.41
         7BE58000 [004040]  1214I 	hw_ret	(p5)				; do the ret
                  [004044]  1222      
                  [004044]  1223  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [004044]    61M         GOTO_FREE_CODE
00000000 00000000 [004044]    67M     .align 6
00000000 00000000 [00404C]
00000000 00000000 [004054]
00000000 00000000 [00405C]
00000000 00000000 [004064]
00000000 00000000 [00406C]
00000000 00000000 [004074]
         00000000 [00407C]
File: ev6_osf_pal.mar
                  [004080]  1224  
                  [004080]  1225  ;+
                  [004080]  1226  ; DTBM_DOUBLE_4 - offset 180
                  [004080]  1227  ;
                  [004080]  1228  ; Entry:
                  [004080]  1229  ;	Vectored into vis hardware trap on TB miss on level 3
                  [004080]  1230  ;	page table entry. Use 4-level flow.
                  [004080]  1231  ;
                  [004080]  1232  ; Function:
                  [004080]  1233  ;	Translate level 3 PTE va.
                  [004080]  1234  ;	If valid, load TB and return to redo the ld_vpte, which will now hit.
                  [004080]  1235  ;	If not valid, then take TNV/ACV exception.
                  [004080]  1236  ;
                  [004080]  1237  ; Current state:
                  [004080]  1238  ;	p4	va of level 3 page table entry
                  [004080]  1239  ;	p5	mm_stat (from dtbm_single)
                  [004080]  1240  ;	p7	exc_sum (from dtbm_single)
                  [004080]  1241  ;	p23	pc of instruction causing the TB miss
                  [004080]  1242  ;
                  [004080]  1243  ;	VA	original VA for dstream TB miss
                  [004080]  1244  ;
                  [004080]  1245  ; Register Use:
                  [004080]  1246  ;	p5	exc_addr, pc of ld_vpte in TB miss flows
                  [004080]  1247  ;	p6	original va
                  [004080]  1248  ;	p7	<31:16>=mm_stat<15:0>,<15:1>=exc_sum<15:1>,<0>=1
                  [004080]  1249  ;
                  [004080]  1250  ;	r25	saved, used as scratch, restored on hw_ret
                  [004080]  1251  ;	r26	saved, used as scratch, restored on hw_ret
                  [004080]  1252  ;
                  [004080]  1253  ; Exit state:
                  [004080]  1254  ;	On exit to trap__double3_pte_inv
                  [004080]  1255  ;	p5	scratch
                  [004080]  1256  ;	p6	original va
                  [004080]  1257  ;	p7	<31:16>=mm_stat<15:0>,<15:1>=exc_sum<15:1>,<0>=1
                  [004080]  1258  ;	p23	pc of instruction causing TB miss
                  [004080]  1259  ;	r25	pte
                  [004080]  1260  ;-
                  [004080]  1261  
                  [004080]  1262  	START_HW_VECTOR <DTBM_DOUBLE_4>
File: ev6_pal_macros.mar
                  [004080]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000180]    49i TRAP__DTBM_DOUBLE_4:
File: ev6_osf_pal.mar
                  [000180]  1263  
                  [000180]  1264  ;
                  [000180]  1265  ; Entered on a miss on va of level 3 page table entry.
                  [000180]  1266  ;	level 0 = VPTB
                  [000180]  1267  ;	level 1 = level 0 of original va
                  [000180]  1268  ;	level 2 = level 1 of original va
                  [000180]  1269  ;	level 3 = level 2 of original va
                  [000180]  1270  ; byte_within_page = level 3 or original va as offset in level 3 page table
                  [000180]  1271  ;
                  [000180]  1272  ; Optimize by starting with the fetch of level 1 pte
                  [000180]  1273  ;
                  [000180]  1274  ASSUME OSF_P_MISC__PHYS__S eq 63
         48E07627 [000180]  1275  	zapnot	p7, #3, p7			; clean exc_sum to 16 bits
         48A21725 [000184]  1276  	sll	p5, #16, p5			; shift mm_stat into place
         44E50407 [000188]  1277  	bis	p7, p5, p7			; combine 
         64BF0600 [00018C]  1278  	hw_mfpr	p5, EV6__EXC_ADDR		; (0L) save exc_addr
                  [000190]  1279  
         44E03407 [000190]  1280  	bis	p7, #1, p7			; double miss flag
                  [000194]  1281  
         7F351118 [000194]  1282  	hw_stq/p r25, PT__R25(p_temp)		; get a scratch register
         7F551120 [000198]  1283  	hw_stq/p r26, PT__R26(p_temp)		; get a scratch register
         6F351008 [00019C]  1284  	hw_ldq/p r25, PT__PTBR(p_temp)		; get phys page table addr
                  [0001A0]  1285  
         EAC00FA4 [0001A0]  1286  	blt	p_misc, trap__double3_1to1	; 1-to-1 => branch
                  [0001A4]  1287  
         4882B73A [0001A4]  1288  	sll	p4, #<64-<<3*level_bits>+13>>, r26
         4B46769A [0001A8]  1289  	srl	r26, #<61-level_bits>, r26	; get level 1 into offset
         433A0419 [0001AC]  1290  	addq	r25, r26, r25			; pa for level 1 pte
         6F391000 [0001B0]  1291  	hw_ldq/p r25, 0(r25)			; get level 1 pte
                  [0001B4]  1292  
         4883F73A [0001B4]  1293  	sll	p4, #<64-<<2*level_bits>+13>>, r26
         4B46769A [0001B8]  1294  	srl	r26, #<61-level_bits>, r26	; get level 2 into offset
         E3200F96 [0001BC]  1295  	blbc	r25, trap__double3_pte_inv	; branch => invalid pte
         4B241699 [0001C0]  1296  	srl	r25, #32, r25			; extract pfn from pte
         4B21B739 [0001C4]  1297  	sll	r25, #13, r25			; get into position
         433A0419 [0001C8]  1298  	addq	r25, r26, r25			; pa for level 2 pte
         6F391000 [0001CC]  1299  	hw_ldq/p r25, 0(r25)			; get level 2 pte
                  [0001D0]  1300  
         4885373A [0001D0]  1301  	sll	p4, #<64-<<1*level_bits>+13>>, r26
         4B46769A [0001D4]  1302  	srl	r26, #<61-level_bits>, r26	; get level 3 into offset
         E3200F8F [0001D8]  1303  	blbc	r25, trap__double3_pte_inv	; branch => invalid pte
         4B241699 [0001DC]  1304  	srl	r25, #32, r25			; extract pfn from pte
         4B21B739 [0001E0]  1305  	sll	r25, #13, r25			; get into position
         433A0419 [0001E4]  1306  	addq	r25, r26, r25			; pa for level 3 pte
         6F391000 [0001E8]  1307  	hw_ldq/p r25, 0(r25)			; get level 3 pte
                  [0001EC]  1308  
         E3200F8A [0001EC]  1309  	blbc	r25, trap__double3_pte_inv	; branch => invalid pte
         4B20F69A [0001F0]  1310  	srl	r25, #7, r26			; get mb bit
                  [0001F4]  1311  
                  [0001F4]  1312  	CONT_HW_VECTOR <DTBM_DOUBLE_4>
File: ev6_pal_macros.mar
                  [0001F4]    76M     ASSUME <_pal_vec_cont> eq 0
         C3E00FA2 [0001F4]    81i 	br	r31, TRAP__DTBM_DOUBLE_4_CONT
                  [0001F8]    84M                 ASSUME <.-_start_of_last_vec> le <^x80>
                  [0001F8]    86M     GOTO_FREE_CODE
                  [004080]    67M     .align 6
                  [004080]    91i TRAP__DTBM_DOUBLE_4_CONT:
File: ev6_osf_pal.mar
                  [004080]  1313  
                  [004080]  1314  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
                  [004080]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
                  [004080]  1315  
                  [004080]  1316  	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [004080]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         77E42044 [004080]  1317  	hw_mtpr	p4, EV6__DTB_TAG0		; (2&6,0L) write tag0
         77E4A022 [004084]  1318  	hw_mtpr p4, EV6__DTB_TAG1		; (1&5,1L) write tag1
         77F92155 [004088]  1319  	hw_mtpr	r25, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
         77F9A1AA [00408C]  1320  	hw_mtpr	r25, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [004090]  1321  
                  [004090]  1322  	ASSUME_FETCH_BLOCK
                  [004090]  1323  
         6F351118 [004090]  1324  	hw_ldq/p r25, PT__R25(p_temp)		; restore register
                  [004094]  1325  ;
                  [004094]  1326  ; We need to wait until the pte writes retire. We need to avoid the
                  [004094]  1327  ; case where the tag writes in the single flow issue before the
                  [004094]  1328  ; pte writes in this flow issue and retire. With changes in 1.36, we
                  [004094]  1329  ; can probably remove this stall, but at this point in the project,
                  [004094]  1330  ; let's just leave it in.
                  [004094]  1331  ;
         77FF2780 [004094]  1332  	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; wait for pte write
                  [004098]  1333  
                  [004098]  1334  ASSUME <tb_mb_en + pte_eco> ne 2
                  [004098]  1335  
                  [004098]  1336  .if eq force_path2				; 1.44 force_path = 0
                  [004098]  1337  
                  [004098]  1338    .if ne pte_eco
                  [004098]  1339  	blbc	r26, trap__dtbm_double4_mb	; branch for mb
                  [004098]  1340  	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004098]  1341  	hw_ret	(p5)				; (0L) return
                  [004098]  1342  
                  [004098]  1343  trap__dtbm_double4_mb:
                  [004098]  1344  	mb
                  [004098]  1345  	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004098]  1346  	hw_ret	(p5)				; (0L) return
                  [004098]  1347    .iff
                  [004098]  1348  	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004098]  1349  	hw_ret	(p5)				; (0L) return
                  [004098]  1350    .endc						; pte eco
                  [004098]  1351  
                  [004098]  1352  .iff						; force_path2 = 1
                  [004098]  1353  ;
                  [004098]  1354  ; We need to avoid the situation where a ldx_l has acquired a lock,
                  [004098]  1355  ; another processor has taken it, and a bad path before a stx_c has
                  [004098]  1356  ; a load which pulls the data back in and makes it look like the
                  [004098]  1357  ; lock has succeeded. Hold up loads by writing to MM_STAT with
                  [004098]  1358  ; scoreboard bit 2 (and 6 -- 6 is required or we hang).
                  [004098]  1359  ;
                  [004098]  1360  	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004098]  1361  	mb					; allow hw_ret to fire
                  [004098]  1362  
                  [004098]  1363  	ALIGN_FETCH_BLOCK <^x47FF041F>
                  [004098]  1364  	mulq	p6, #1, p6			; hold up loads
                  [004098]  1365  	mulq	p6, #1, p6			; hols up loads
                  [004098]  1366  	hw_mtpr p6, <EV6__MM_STAT ! ^x44>	; hold up loads
                  [004098]  1367  	hw_ret	(p5)				; return
                  [004098]  1368  .endc						; 1.44 force_path2
                  [004098]  1337I 
                  [004098]  1338I   .if ne pte_eco
                  [004098]  1339I 	blbc	r26, trap__dtbm_double4_mb	; branch for mb
                  [004098]  1340I 	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004098]  1341I 	hw_ret	(p5)				; (0L) return
                  [004098]  1342I 
                  [004098]  1343I trap__dtbm_double4_mb:
                  [004098]  1344I 	mb
                  [004098]  1345I 	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004098]  1346I 	hw_ret	(p5)				; (0L) return
                  [004098]  1347I   .iff
                  [004098]  1348I 	hw_ldq/p r26, PT__R26(p_temp)		; restore register
                  [004098]  1349I 	hw_ret	(p5)				; (0L) return
                  [004098]  1350I   .endc						; pte eco
         E3400002 [004098]  1339I 	blbc	r26, trap__dtbm_double4_mb	; branch for mb
         6F551120 [00409C]  1340I 	hw_ldq/p r26, PT__R26(p_temp)		; restore register
         7BE58000 [0040A0]  1341I 	hw_ret	(p5)				; (0L) return
                  [0040A4]  1342I 
                  [0040A4]  1343I trap__dtbm_double4_mb:
         63FF4000 [0040A4]  1344I 	mb
         6F551120 [0040A8]  1345I 	hw_ldq/p r26, PT__R26(p_temp)		; restore register
         7BE58000 [0040AC]  1346I 	hw_ret	(p5)				; (0L) return
                  [0040B0]  1351I   
                  [0040B0]  1369  
                  [0040B0]  1370  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [0040B0]    61M         GOTO_FREE_CODE
00000000 00000000 [0040B0]    67M     .align 6
00000000 00000000 [0040B8]
File: ev6_osf_pal.mar
                  [0040C0]  1371  
                  [0040C0]  1372  ;+
                  [0040C0]  1373  ; FEN - offset 200
                  [0040C0]  1374  ;
                  [0040C0]  1375  ; Entry:
                  [0040C0]  1376  ;	Vectored into via hardware trap on floating disable fault.
                  [0040C0]  1377  ;
                  [0040C0]  1378  ; Function:
                  [0040C0]  1379  ;	Build stack frame.
                  [0040C0]  1380  ;		r16 (a0)	FEN code
                  [0040C0]  1381  ;		r17 (a1)	unpredictable
                  [0040C0]  1382  ;		r18 (a2)	unpredictable
                  [0040C0]  1383  ;	Vector via entIF.
                  [0040C0]  1384  ;
                  [0040C0]  1385  ; Note:
                  [0040C0]  1386  ;	Unlike previous processors, this entry point is *only* for
                  [0040C0]  1387  ;	floating point disabled fault, so we don't need to check fen
                  [0040C0]  1388  ;	to see if we need to generate an OPCDEC instead.
                  [0040C0]  1389  ;-
                  [0040C0]  1390  
                  [0040C0]  1391  	START_HW_VECTOR <FEN>
File: ev6_pal_macros.mar
                  [0040C0]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000200]    49i TRAP__FEN:
File: ev6_osf_pal.mar
                  [000200]  1392  
                  [000200]  1393  ASSUME OSF_P_MISC__PS__S eq 0
                  [000200]  1394  
                  [000200]  1395  .if ne ev6_p1
                  [000200]  1396  	hw_mfpr	p23, EV6__EXC_ADDR			; (0L) save exc_addr
                  [000200]  1397  	NOP						; no conditional br
                  [000200]  1398  	NOP						;	in 1st block
                  [000200]  1399  	NOP
                  [000200]  1400  
                  [000200]  1401  	hw_ldq/p p4, PT__IMPURE(p_temp)			; get base of impure area
                  [000200]  1402  	hw_ldq/p p5, CNS__FPE_STATE(p4)			; get real fpe state
                  [000200]  1403  	blbc	p5, trap__emul_fen			; if clear, take fen trap
                  [000200]  1404  
                  [000200]  1405  trap__emul_merge:				; merge from opcdec
                  [000200]  1406  
                  [000200]  1407  	hw_stq/p p23, CNS__FP_PC(p4)		; save user pc
                  [000200]  1408  
                  [000200]  1409      .if ne fp_count
                  [000200]  1410  	hw_ldq/p p6, PT__RSV_FOR_PAL(p_temp)	; get fp counter
                  [000200]  1411  	addq	p6, #1, p6			; add 1
                  [000200]  1412  	hw_stq/p p6, PT__RSV_FOR_PAL(p_temp)	; write it back
                  [000200]  1413  	br	r31, trap__fen_cont		; continue
                  [000200]  1414      .endc
                  [000200]  1415  
                  [000200]  1416  	CONT_HW_VECTOR <FEN>
                  [000200]  1417  ;
                  [000200]  1418  ; Fen with FPE_STATE set
                  [000200]  1419  ;	or
                  [000200]  1420  ; Opcdec with unknown FPE_STATE
                  [000200]  1421  ;
                  [000200]  1422  ;	Save GPRs.
                  [000200]  1423  ;	Get the instruction and parse for load/store.
                  [000200]  1424  ;	Execute locally for ld/st.
                  [000200]  1425  ;	Go to emulator for operates and branches.
                  [000200]  1426  ;	Restore GPRs.
                  [000200]  1427  ;	HW_RET to correct PC. 
                  [000200]  1428  ;
                  [000200]  1429  ASSUME EV6__I_CTL__SDE__S eq 6
                  [000200]  1430  
                  [000200]  1431  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align with nops
                  [000200]  1432  
                  [000200]  1433  	hw_stq/p r0, CNS__R0_EMUL(p4)		; save r0
                  [000200]  1434  	hw_stq/p r1, CNS__R1_EMUL(p4)		; save r1
                  [000200]  1435  	hw_stq/p r2, CNS__R2_EMUL(p4)		; save r2
                  [000200]  1436  	hw_mfpr	r2, EV6__I_CTL			; (4,0L) get i_ctl
                  [000200]  1437  
                  [000200]  1438  	bis	p4, r31, r1			; impure base into r1
                  [000200]  1439  	bic	r2, #<2@EV6__I_CTL__SDE__S>, r2	; zap sde
                  [000200]  1440  	hw_stq/p r3, CNS__R3_EMUL(p4)		; save r3
                  [000200]  1441  	hw_stq/p r8, CNS__R8_EMUL(r1)		; save gpr
                  [000200]  1442  
                  [000200]  1443  	hw_mtpr	r2, EV6__I_CTL			; (4,0L) write i_ctl
                  [000200]  1444  	hw_stq/p r9, CNS__R9_EMUL(r1)		; save gpr
                  [000200]  1445  	hw_stq/p r10, CNS__R10_EMUL(r1)		; save gpr
                  [000200]  1446  	hw_stq/p r11, CNS__R11_EMUL(r1)		; save gpr
                  [000200]  1447  
                  [000200]  1448  	hw_mtpr	r2, EV6__I_CTL			; (4,0L) stall outside IQ
                  [000200]  1449  	hw_stq/p r12, CNS__R12_EMUL(r1)		; save gpr
                  [000200]  1450  	hw_stq/p r13, CNS__R13_EMUL(r1)		; save gpr
                  [000200]  1451  	hw_stq/p r14, CNS__R14_EMUL(r1)		; save gpr
                  [000200]  1452  
                  [000200]  1453  	hw_stq/p r15, CNS__R15_EMUL(r1)		; buffer block 1 -- save gpr
                  [000200]  1454  	hw_stq/p r16, CNS__R16_EMUL(r1)		; save gpr
                  [000200]  1455  	hw_stq/p r17, CNS__R17_EMUL(r1)		; save gpr
                  [000200]  1456  	hw_stq/p r18, CNS__R18_EMUL(r1)		; save gpr
                  [000200]  1457  
                  [000200]  1458  	hw_stq/p r19, CNS__R19_EMUL(r1)		; buffer block 2 -- save gpr
                  [000200]  1459  	hw_stq/p r24, CNS__R24_EMUL(r1)		; save gpr
                  [000200]  1460  	hw_stq/p r25, CNS__R25_EMUL(r1)		; save gpr
                  [000200]  1461  	hw_stq/p r26, CNS__R26_EMUL(r1)		; save gpr
                  [000200]  1462  
                  [000200]  1463  	hw_stq/p r27, CNS__R27_EMUL(r1)		; buffer block 3 -- save gpr
                  [000200]  1464  	hw_stq/p r28, CNS__R28_EMUL(r1)		; save gpr
                  [000200]  1465  	hw_stq/p r29, CNS__R29_EMUL(r1)		; save gpr
                  [000200]  1466  	hw_stq/p r30, CNS__R30_EMUL(r1)		; save gpr
                  [000200]  1467  
                  [000200]  1468  	hw_stq/p r4, CNS__R4_EMUL(r1)		; save gpr
                  [000200]  1469  	hw_stq/p r5, CNS__R5_EMUL(r1)		; save gpr
                  [000200]  1470  	hw_stq/p r6, CNS__R6_EMUL(r1)		; save gpr
                  [000200]  1471  	hw_stq/p r7, CNS__R7_EMUL(r1)		; save gpr
                  [000200]  1472  
                  [000200]  1473  	hw_stq/p r20, CNS__R20_EMUL(r1)		; save gpr
                  [000200]  1474  	hw_stq/p r21, CNS__R21_EMUL(r1)		; save gpr
                  [000200]  1475  	hw_stq/p r22, CNS__R22_EMUL(r1)		; save gpr
                  [000200]  1476  	hw_stq/p r23, CNS__R23_EMUL(r1)		; save gpr
                  [000200]  1477  
                  [000200]  1478  	hw_stq/p r31, CNS__R31_EMUL(r1)		; save gpr
                  [000200]  1479  ;
                  [000200]  1480  ; Now turn shadow mode back on
                  [000200]  1481  ;
                  [000200]  1482  	bis	r2, #<2@EV6__I_CTL__SDE__S>, r2	; enable sde
                  [000200]  1483  	hw_mtpr	r2, EV6__I_CTL			; (4,0L) write i_ctl
                  [000200]  1484  	bis	r31, r31, r31			; finish fetch block
                  [000200]  1485  
                  [000200]  1486  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align with nops
                  [000200]  1487  
                  [000200]  1488  	hw_mtpr	r2, EV6__I_CTL			; (4,0L) stall outside IQ
                  [000200]  1489  	bis	r31, r31, r31
                  [000200]  1490  	bis	r31, r31, r31
                  [000200]  1491  	bis	r31, r31, r31
                  [000200]  1492  
                  [000200]  1493  	bis	r0, r0, r0			; buffer block 1
                  [000200]  1494  	bis	r31, r31, r31
                  [000200]  1495  	bis	r31, r31, r31
                  [000200]  1496  	bis	r31, r31, r31
                  [000200]  1497  
                  [000200]  1498  	bis	r0, r0, r0			; buffer block 2
                  [000200]  1499  	bis	r31, r31, r31
                  [000200]  1500  	bis	r31, r31, r31
                  [000200]  1501  	bis	r31, r31, r31
                  [000200]  1502  
                  [000200]  1503  	bis	r0, r0, r0			; buffer block 3
                  [000200]  1504  	bis	r31, r31, r31
                  [000200]  1505  	bis	r31, r31, r31
                  [000200]  1506  	bis	r31, r31, r31
                  [000200]  1507  ;
                  [000200]  1508  ; Now start parsing the instruction.
                  [000200]  1509  ;	r1	pointer to impure area
                  [000200]  1510  ;	p23	pc of instruction
                  [000200]  1511  ; After getting the instruction, we can no longer depend on p23, as
                  [000200]  1512  ; we could have taken a miss. So copy to r2 for the fetch.
                  [000200]  1513  ;
                  [000200]  1514  	bic	p23, #3, r2			; clean instruction to r2
                  [000200]  1515  trap__emul_get_instr:
                  [000200]  1516  	ldl	p5, 0(r2)			; fatal if faults, okay to tnv
                  [000200]  1517  	zap	p5, #^xF0, p5			; clean to 32 bits
                  [000200]  1518  	srl	p5, #26, p6			; get opcode
                  [000200]  1519  	and	p6, #^x30, p7			; just get <5:4> of opcode
                  [000200]  1520  	cmpeq	p7, #^x20, p7			; check against ^x20
                  [000200]  1521  	beq	p7, trap__emul_emul		; branch => pass to emulator
                  [000200]  1522  ;
                  [000200]  1523  ; Load/Store
                  [000200]  1524  ;	r1	pointer to impure area
                  [000200]  1525  ;	p5	instruction
                  [000200]  1526  ;	p6	opcode
                  [000200]  1527  ;
                  [000200]  1528  	sll	p5, #43, r2			; Rb.ab
                  [000200]  1529  	srl	r2, #59, r2			; Rb.ab
                  [000200]  1530  	s8addq	r2, r1, r2			; impure area + offset for RA
                  [000200]  1531  	hw_ldq/p r3, CNS__R0_EMUL(r2)		; get contents of register
                  [000200]  1532  
                  [000200]  1533  	sll	p5, #48, r8			; get bit 15 to 63
                  [000200]  1534  	sra	r8, #48, r8			; now have sign ext displacement
                  [000200]  1535  	addq	r8, r3, r8			; (reg)+disp = mem addr
                  [000200]  1536  
                  [000200]  1537  	sll	p5, #38, r9			; Fa
                  [000200]  1538  	srl	r9, #59, r9			; Fa
                  [000200]  1539  	bis	r9, r31, r10			; Fa for F31 check
                  [000200]  1540  	s8addq	r9, r1, r9			; impure area + offset for FA
                  [000200]  1541  ;
                  [000200]  1542  ; We now have the operand info.
                  [000200]  1543  ;	r1	pointer to impure area
                  [000200]  1544  ;	r8	memory address
                  [000200]  1545  ;	r9	impure area + offset to FA
                  [000200]  1546  ;	r10	FA for F31 check
                  [000200]  1547  ;
                  [000200]  1548  ;	p5	instr
                  [000200]  1549  ;	p6	opcode
                  [000200]  1550  ;
                  [000200]  1551  ; We need to save the opcode into r11 in case of alignment trap.
                  [000200]  1552  ;
                  [000200]  1553  	bis	p6, r31, r11			; save for alignment trap
                  [000200]  1554  	and	p6, #^x04, r2			; check for load or store
                  [000200]  1555  	bne	r2, trap__emul_parse		; branch for stores
                  [000200]  1556  	cmpeq	r10, #^x1F, r3			; check for load to f31
                  [000200]  1557  	bne	r3, trap__emul_ldst_done	; done if load to f31
                  [000200]  1558  
                  [000200]  1559  trap__emul_parse:
                  [000200]  1560  	cmpeq	p6, #^x20, r2
                  [000200]  1561  	bne	r2, trap__emul_ldf		; branch for ldf
                  [000200]  1562  	cmpeq	p6, #^x21, r3
                  [000200]  1563  	bne	r3, trap__emul_ldg		; branch for ldg
                  [000200]  1564  	cmpeq	p6, #^x22, r2
                  [000200]  1565  	bne	r2, trap__emul_lds		; branch for lds
                  [000200]  1566  	cmpeq	p6, #^x23, r3
                  [000200]  1567  	bne	r3, trap__emul_ldt		; branch for ldt
                  [000200]  1568  
                  [000200]  1569  	cmpeq	p6, #^x24, r2
                  [000200]  1570  	bne	r2, trap__emul_stf		; branch for stf
                  [000200]  1571  	cmpeq	p6, #^x25, r3
                  [000200]  1572  	bne	r3, trap__emul_stg		; branch for stg
                  [000200]  1573  	cmpeq	p6, #^x26, r2
                  [000200]  1574  	bne	r2, trap__emul_sts		; branch for sts
                  [000200]  1575  	cmpeq	p6, #^x27, r3
                  [000200]  1576  	beq	r3, trap__pal_exc_bugcheck	; bugcheck if not stt
                  [000200]  1577  	br	r31, trap__emul_stt		; fall through for stt
                  [000200]  1578  ;
                  [000200]  1579  ; Do load or store.
                  [000200]  1580  ;	r8	memory address
                  [000200]  1581  ;	r9	impure area + fpr offset
                  [000200]  1582  ;
                  [000200]  1583  
                  [000200]  1584  ;
                  [000200]  1585  ; LDF
                  [000200]  1586  ;
                  [000200]  1587  trap__emul_ldf:
                  [000200]  1588  	ldl	r0, 0(r8)		; load from memory (may fault)
                  [000200]  1589  	extwl   r0, #2, r1		; <31:16> -> r1
                  [000200]  1590  	inswl	r0, #2, r0		; <15:0> << 16 -> r0
                  [000200]  1591          addq	r0, r1, r0
                  [000200]  1592  	sll	r0, #41, r1		; shift out all but fraction bits
                  [000200]  1593  	srl	r1, #12, r1		; shift fraction bits inplace
                  [000200]  1594          addq	r31, #^x070, r16
                  [000200]  1595          srl	r0, #30, r19		; shift out all but sign and bias
                  [000200]  1596          sll	r19, #62, r19		; move into correct place
                  [000200]  1597          srl	r0, #23, r0
                  [000200]  1598          addq	r1, r19, r1		; insert sign and bias
                  [000200]  1599          and	r0, #255, r0		; clear all but exp
                  [000200]  1600  	cmoveq	r0, #0, r16		; clear map
                  [000200]  1601  	cmpult	r0, #^x80, r19		; test for small exp
                  [000200]  1602  	cmpeq	r0, #^xff, r17		; check for Nan and Inf
                  [000200]  1603  	bic	r19, r17, r19		; r19 and ~r17
                  [000200]  1604  	cmoveq	r19, #0, r16		; clear map
                  [000200]  1605          and	r0, #^x7f, r0		; clear all but exp
                  [000200]  1606          s8addq	r16, r0, r16
                  [000200]  1607  	sll	r16, #52, r16
                  [000200]  1608          addq	r16, r1, r0		; merge it
                  [000200]  1609  	hw_stq/p r0, CNS__F0_EMUL(r9)	; write to our register file
                  [000200]  1610  	br	r31, trap__emul_ldst_done
                  [000200]  1611  ;
                  [000200]  1612  ; LDG
                  [000200]  1613  ;
                  [000200]  1614  trap__emul_ldg:
                  [000200]  1615  	ldq	r0, 0(r8)		; load from memory (may fault)
                  [000200]  1616  	sll	r0, #48, r1		; <15:0> -> <63:48>
                  [000200]  1617  	srl	r0, #48, r16		; <63:48> -> <15:0>
                  [000200]  1618  	extwl	r0, #2,	r17		; <31:16> -> r17
                  [000200]  1619  	addq	r1, r16, r1		; <63:48> + <15:0>
                  [000200]  1620  	inswl	r17, #4, r16		; <31:16> -> <47:32>
                  [000200]  1621  	extwl	r0, #4,	r17		; <47:32> -> r17
                  [000200]  1622  	addq	r1, r16, r1		; <63:48> + <47:32> + <15:0> 
                  [000200]  1623  	inswl	r17, #2, r0		; <47:32> -> <31:16>
                  [000200]  1624  	addq	r1, r0, r0		; <63:48> + <47:32> + <31:16> + <15:0>
                  [000200]  1625  	hw_stq/p r0, CNS__F0_EMUL(r9)	; write to our register file
                  [000200]  1626  	br	r31, trap__emul_ldst_done
                  [000200]  1627  ;
                  [000200]  1628  ; LDS
                  [000200]  1629  ;
                  [000200]  1630  trap__emul_lds:
                  [000200]  1631  	ldl	r0, 0(r8)		; load from user memory
                  [000200]  1632  	sll	r0, #41, r1		; shift out all but fraction bits
                  [000200]  1633  	srl	r1, #12, r1		; shift fraction bits inplace
                  [000200]  1634  	addq	r31, #^x70, r16	
                  [000200]  1635  	srl	r0, #30, r19		; shift out all but sign and bias
                  [000200]  1636  	sll	r19, #62, r19		; move into correct place
                  [000200]  1637  	srl	r0, #23, r0
                  [000200]  1638  	addq	r1, r19, r1		; insert sign and bias
                  [000200]  1639  	and	r0, #255, r0		; clear all but exp
                  [000200]  1640  	cmoveq	r0, #0, r16		; clear map
                  [000200]  1641  	cmpult	r0, #^x80, r19		; test for small exp
                  [000200]  1642  	cmpeq	r0, #^xff, r17		; check for Nan and Inf
                  [000200]  1643  	bis	r17, r19, r19		; or result
                  [000200]  1644  	cmoveq	r19, #0, r16		; clear map
                  [000200]  1645  	and	r0, #^x7f, r0		; clear all but exp
                  [000200]  1646  	s8addq	r16, r0, r16
                  [000200]  1647  	sll	r16, #52, r16
                  [000200]  1648  	addq	r16, r1, r0		; merge it
                  [000200]  1649  	hw_stq/p r0, CNS__F0_EMUL(r9)	; write to our register file
                  [000200]  1650  	br	r31, trap__emul_ldst_done
                  [000200]  1651  ;
                  [000200]  1652  ; LDT
                  [000200]  1653  ;
                  [000200]  1654  trap__emul_ldt:
                  [000200]  1655  	ldq	r0, 0(r8)		; load from memory (may fault)
                  [000200]  1656  	hw_stq/p r0, CNS__F0_EMUL(r9)	; write to our register file
                  [000200]  1657  	br	r31, trap__emul_ldst_done
                  [000200]  1658  
                  [000200]  1659  ;
                  [000200]  1660  ; STF
                  [000200]  1661  ;
                  [000200]  1662  trap__emul_stf:
                  [000200]  1663  	hw_ldq/p r0, CNS__F0_EMUL(r9)	; read from our register file
                  [000200]  1664  	sll	r0, #5, r1		; shift out all but fraction bits
                  [000200]  1665  	srl	r1, #34, r1		; shift fraction bits inplace
                  [000200]  1666  	srl	r0, #62, r0		; shift out all but fraction bits
                  [000200]  1667  	sll	r0, #30, r0
                  [000200]  1668  	addq	r0, r1, r0
                  [000200]  1669  	extwl	r0, #2, r1		; <31:16> -> r1
                  [000200]  1670  	inswl	r0, #2, r0		; <15:0> << 16 -> r0
                  [000200]  1671  	addq	r0, r1, r0
                  [000200]  1672  trap__emul_stf_s:
                  [000200]  1673  	stl	r0, 0(r8)		; store it in to memory (may fault)
                  [000200]  1674  	br	r31, trap__emul_ldst_done
                  [000200]  1675  ;
                  [000200]  1676  ; STG
                  [000200]  1677  ;
                  [000200]  1678  trap__emul_stg:
                  [000200]  1679  	hw_ldq/p r0, CNS__F0_EMUL(r9)	; read from our register file
                  [000200]  1680  	sll	r0, #48, r1		; <15:0> -> <63:48>
                  [000200]  1681  	srl	r0, #48, r16		; <63:48> -> <15:0>
                  [000200]  1682  	extwl	r0, #2,	r17		; <31:16> -> r17
                  [000200]  1683  	addq	r1, r16, r1		; <63:48> + <15:0>
                  [000200]  1684  	inswl	r17, #4, r16		; <31:16> -> <47:32>
                  [000200]  1685  	extwl	r0, #4,	r17		; <47:32> -> r17
                  [000200]  1686  	addq	r1, r16, r1		; <63:48> + <47:32> + <15:0> 
                  [000200]  1687  	inswl	r17, #2, r0		; <47:32> -> <31:16>
                  [000200]  1688  	addq	r1, r0, r0		; <63:48> + <47:32> + <31:16> + <15:0>
                  [000200]  1689  trap__emul_stg_s:
                  [000200]  1690  	stq	r0, 0(r8)		; store it in memory (may fault)
                  [000200]  1691  	br	r31, trap__emul_ldst_done
                  [000200]  1692  ;
                  [000200]  1693  ; STS
                  [000200]  1694  ;
                  [000200]  1695  trap__emul_sts:
                  [000200]  1696  	hw_ldq/p r0, CNS__F0_EMUL(r9)	; read from our register file
                  [000200]  1697  	sll	r0, #5, r1		; shift out all but fraction bits
                  [000200]  1698  	srl	r1, #34, r1		; shift fraction bits in place
                  [000200]  1699  	srl	r0, #62, r0		; shift out all but fraction bits
                  [000200]  1700  	sll	r0, #30, r0
                  [000200]  1701  	addq	r0, r1, r0
                  [000200]  1702  trap__emul_sts_s:
                  [000200]  1703  	stl	r0, 0(r8)		; store in user memory (may fault)
                  [000200]  1704  	br	r31, trap__emul_ldst_done
                  [000200]  1705  ;
                  [000200]  1706  ; STT
                  [000200]  1707  ;
                  [000200]  1708  trap__emul_stt:
                  [000200]  1709  	hw_ldq/p r0, CNS__F0_EMUL(r9)	; read from our register file
                  [000200]  1710  trap__emul_stt_s:
                  [000200]  1711  	stq	r0, 0(r8)		; store in user memory (may fault)
                  [000200]  1712  	br	r31, trap__emul_ldst_done
                  [000200]  1713  ;
                  [000200]  1714  ; Load/Store Done.
                  [000200]  1715  ;
                  [000200]  1716  trap__emul_ldst_done:
                  [000200]  1717  	hw_ldq/p p4, PT__IMPURE(p_temp)		; get base of impure area
                  [000200]  1718  	hw_ldq/p p6, CNS__FP_PC(p4)		; get pc back
                  [000200]  1719  	addq	p6, #4, p6			; point to next instruction
                  [000200]  1720  	hw_stq/p p6, CNS__FP_PC(p4)		; write back to save location
                  [000200]  1721  	br	r31, trap__emul_done
                  [000200]  1722  
                  [000200]  1723  
                  [000200]  1724  ;+
                  [000200]  1725  ; Done emulation. Restore and go back to user.
                  [000200]  1726  ; Current state:
                  [000200]  1727  ;	p4	base of impure area
                  [000200]  1728  ;	p20	unaligned flag
                  [000200]  1729  ;
                  [000200]  1730  ;	Get out of shadow mode.
                  [000200]  1731  ;	Restore overshadowed registers.
                  [000200]  1732  ;	Get back into shadow mode.
                  [000200]  1733  ;	Restore the rest of the registers.
                  [000200]  1734  ;	Return to user.
                  [000200]  1735  ;-
                  [000200]  1736  trap__emul_done:
                  [000200]  1737  	bis	p4, r31, r1			; impure base into r1
                  [000200]  1738  	PVC_JSR	emul_restore, bsr=1
                  [000200]  1739  	bsr	r3, trap__emul_restore		; restore GPRs except r0-r3
                  [000200]  1740  ;
                  [000200]  1741  ; Now restore the rest of the GPRs.;
                  [000200]  1742  ;
                  [000200]  1743  	hw_ldq/p r0, CNS__R0_EMUL(p4)		; restore r0
                  [000200]  1744  	hw_ldq/p r1, CNS__R1_EMUL(p4)		; restore r1
                  [000200]  1745  	hw_ldq/p r2, CNS__R2_EMUL(p4)		; restore r2
                  [000200]  1746  	hw_ldq/p r3, CNS__R3_EMUL(p4)		; restore r3
                  [000200]  1747  ;
                  [000200]  1748  ; Return to user.
                  [000200]  1749  ;
                  [000200]  1750  	hw_ldq/p p23, CNS__FP_PC(p4)		; get nextpc
                  [000200]  1751  	hw_ret (p23)				; return to user
                  [000200]  1752  
                  [000200]  1753  ;+
                  [000200]  1754  ; Subroutine to restore GPRs.
                  [000200]  1755  ;	p4	pointer to impure area
                  [000200]  1756  ;	r1	pointer to impure area
                  [000200]  1757  ;	r3	return address
                  [000200]  1758  ;
                  [000200]  1759  ; Do not touch shadow registers.
                  [000200]  1760  ;-
                  [000200]  1761  	ALIGN_FETCH_BLOCK
                  [000200]  1762  
                  [000200]  1763  trap__emul_restore:
                  [000200]  1764  	hw_mfpr	r2, EV6__I_CTL			; (4,0L) get i_ctl
                  [000200]  1765  	bic	r2, #<2@EV6__I_CTL__SDE__S>, r2	; zap sde
                  [000200]  1766  	hw_ldq/p r8, CNS__R8_EMUL(r1)		; restore gpr
                  [000200]  1767  	hw_ldq/p r9, CNS__R9_EMUL(r1)		; restore gpr
                  [000200]  1768  
                  [000200]  1769  	hw_mtpr	r2, EV6__I_CTL			; (4,0L) write i_ctl
                  [000200]  1770  	hw_ldq/p r10, CNS__R10_EMUL(r1)		; restore gpr
                  [000200]  1771  	hw_ldq/p r11, CNS__R11_EMUL(r1)		; restore gpr
                  [000200]  1772  	hw_ldq/p r12, CNS__R12_EMUL(r1)		; restore gpr
                  [000200]  1773  
                  [000200]  1774  	hw_mtpr	r2, EV6__I_CTL			; stall outside IQ
                  [000200]  1775  	hw_ldq/p r13, CNS__R13_EMUL(r1)		; restore gpr
                  [000200]  1776  	hw_ldq/p r14, CNS__R14_EMUL(r1)		; restore gpr
                  [000200]  1777  	hw_ldq/p r15, CNS__R15_EMUL(r1)		; restore gpr
                  [000200]  1778  
                  [000200]  1779  	hw_ldq/p r16, CNS__R16_EMUL(r1)		; buffer block 1 -- restore gpr
                  [000200]  1780  	hw_ldq/p r17, CNS__R17_EMUL(r1)		; restore gpr
                  [000200]  1781  	hw_ldq/p r18, CNS__R18_EMUL(r1)		; restore gpr
                  [000200]  1782  	hw_ldq/p r19, CNS__R19_EMUL(r1)		; restore gpr
                  [000200]  1783  
                  [000200]  1784  	hw_ldq/p r24, CNS__R24_EMUL(r1)		; buffer block 2 -- restore gpr
                  [000200]  1785  	hw_ldq/p r25, CNS__R25_EMUL(r1)		; restore gpr
                  [000200]  1786  	hw_ldq/p r26, CNS__R26_EMUL(r1)		; restore gpr
                  [000200]  1787  	hw_ldq/p r27, CNS__R27_EMUL(r1)		; restore gpr
                  [000200]  1788  
                  [000200]  1789  	hw_ldq/p r28, CNS__R28_EMUL(r1)		; buffer block 3 -- restore gpr
                  [000200]  1790  	hw_ldq/p r29, CNS__R29_EMUL(r1)		; restore gpr
                  [000200]  1791  	hw_ldq/p r30, CNS__R30_EMUL(r1)		; restore gpr
                  [000200]  1792  	bis	r31, r31, r31
                  [000200]  1793  
                  [000200]  1794  	hw_ldq/p r4, CNS__R4_EMUL(r1)		; restore gpr
                  [000200]  1795  	hw_ldq/p r5, CNS__R5_EMUL(r1)		; restore gpr
                  [000200]  1796  	hw_ldq/p r6, CNS__R6_EMUL(r1)		; restore gpr
                  [000200]  1797  	hw_ldq/p r7, CNS__R7_EMUL(r1)		; restore gpr
                  [000200]  1798  
                  [000200]  1799  	hw_ldq/p r20, CNS__R20_EMUL(r1)		; restore gpr
                  [000200]  1800  	hw_ldq/p r21, CNS__R21_EMUL(r1)		; restore gpr
                  [000200]  1801  	hw_ldq/p r22, CNS__R22_EMUL(r1)		; restore gpr
                  [000200]  1802  	hw_ldq/p r23, CNS__R23_EMUL(r1)		; restore gpr
                  [000200]  1803  ;
                  [000200]  1804  ; Now turn shadow mode back on.
                  [000200]  1805  ;
                  [000200]  1806  	bis	r2, #<2@EV6__I_CTL__SDE__S>, r2	; enable sde
                  [000200]  1807  	hw_mtpr	r2, EV6__I_CTL			; (4,0L) write i_ctl
                  [000200]  1808  	bis	r31, r31, r31
                  [000200]  1809  	bis	r31, r31, r31
                  [000200]  1810  
                  [000200]  1811  	hw_mtpr	r2, EV6__I_CTL			; (4,0L) stall outside IQ
                  [000200]  1812  	bis	r31, r31, r31
                  [000200]  1813  	bis	r31, r31, r31
                  [000200]  1814  	bis	r31, r31, r31
                  [000200]  1815  
                  [000200]  1816  	bis	r0, r0, r0			; buffer block 1
                  [000200]  1817  	bis	r31, r31, r31
                  [000200]  1818  	bis	r31, r31, r31
                  [000200]  1819  	bis	r31, r31, r31
                  [000200]  1820  
                  [000200]  1821  	bis	r0, r0, r0			; buffer block 2
                  [000200]  1822  	bis	r31, r31, r31
                  [000200]  1823  	bis	r31, r31, r31
                  [000200]  1824  	bis	r31, r31, r31
                  [000200]  1825  
                  [000200]  1826  	bis	r0, r0, r0			; buffer block 3
                  [000200]  1827  	bis	r31, r31, r31
                  [000200]  1828  	bis	r31, r31, r31
                  [000200]  1829  	bis	r31, r31, r31
                  [000200]  1830  
                  [000200]  1831  	bis	r3, #1, r3			; return in pal mode
                  [000200]  1832  	PVC_JSR emul_restore, bsr=1, dest=1
                  [000200]  1833  	hw_ret_stall (r3)			; stall for pvc
                  [000200]  1834  
                  [000200]  1835  ;+
                  [000200]  1836  ; Load/Store operand dfault.
                  [000200]  1837  ;
                  [000200]  1838  ; We need to restore GPRs. Then we need to set up for an exception.
                  [000200]  1839  ;
                  [000200]  1840  ; Current register state:
                  [000200]  1841  ;	p5		mm_stat
                  [000200]  1842  ;	p6		pc of palcode instruction
                  [000200]  1843  ;	p7		available
                  [000200]  1844  ;
                  [000200]  1845  ;	r25		will be restored as part of gpr restore
                  [000200]  1846  ;	r26		will be restored as part of gpr restore
                  [000200]  1847  ;
                  [000200]  1848  ;	CNS__FP_PC	user pc
                  [000200]  1849  ;
                  [000200]  1850  ;	VA		faulting VA
                  [000200]  1851  ;-
                  [000200]  1852  trap__emul_ldst_dfault:
                  [000200]  1853  	hw_ldq/p p4, PT__IMPURE(p_temp)		; impure base into p4
                  [000200]  1854  	bis	p4, r31, r1			; also put it into r1
                  [000200]  1855  	PVC_JSR	emul_restore, bsr=1
                  [000200]  1856  	bsr	r3, trap__emul_restore		; restore all but r0-r3
                  [000200]  1857  ;
                  [000200]  1858  ; Now restore the rest of the GPRs.
                  [000200]  1859  ;
                  [000200]  1860  	hw_ldq/p r0, CNS__R0_EMUL(p4)		; restore r0
                  [000200]  1861  	hw_ldq/p r1, CNS__R1_EMUL(p4)		; restore r1
                  [000200]  1862  	hw_ldq/p r2, CNS__R2_EMUL(p4)		; restore r2
                  [000200]  1863  	hw_ldq/p r3, CNS__R3_EMUL(p4)		; restore r3
                  [000200]  1864  ;
                  [000200]  1865  ; Now restore restore pc to p6, and merge with dfault code
                  [000200]  1866  ;
                  [000200]  1867  	hw_ldq/p p6, CNS__FP_PC(p4)		; get back user pc
                  [000200]  1868  	br	r31, trap__dfault_no_dismiss	; merge to post
                  [000200]  1869  
                  [000200]  1870  ;+
                  [000200]  1871  ; Load/Store operand tnv.
                  [000200]  1872  ;
                  [000200]  1873  ; We need to restore GPRs. Then we need to set up for an exception.
                  [000200]  1874  ;
                  [000200]  1875  ; Current register state:
                  [000200]  1876  ;	p4		PTE
                  [000200]  1877  ;	p5		mm_stat
                  [000200]  1878  ;	p6		va
                  [000200]  1879  ;	p7		exc_sum
                  [000200]  1880  ;
                  [000200]  1881  ;	r25		will be restored as part of gpr restore
                  [000200]  1882  ;	r26		will be restored as part of gpr restore
                  [000200]  1883  ;
                  [000200]  1884  ;	CNS__FP_PC	user pc
                  [000200]  1885  ;-
                  [000200]  1886  trap__emul_ldst_tnv:
                  [000200]  1887  	hw_ldq/p p23, PT__IMPURE(p_temp)	; impure base into p23
                  [000200]  1888  	bis	p23, r31, r1			; also put it into r1
                  [000200]  1889  	PVC_JSR	emul_restore, bsr=1
                  [000200]  1890  	bsr	r3, trap__emul_restore		; restore all but r0-r3
                  [000200]  1891  ;
                  [000200]  1892  ; Now restore the rest of the GPRs.
                  [000200]  1893  ;
                  [000200]  1894  	hw_ldq/p r0, CNS__R0_EMUL(p23)		; restore r0
                  [000200]  1895  	hw_ldq/p r1, CNS__R1_EMUL(p23)		; restore r1
                  [000200]  1896  	hw_ldq/p r2, CNS__R2_EMUL(p23)		; restore r2
                  [000200]  1897  	hw_ldq/p r3, CNS__R3_EMUL(p23)		; restore r3
                  [000200]  1898  ;
                  [000200]  1899  ; Now restore restore pc to p6, and merge with dfault code
                  [000200]  1900  ;
                  [000200]  1901  	hw_ldq/p p23, CNS__FP_PC(p23)			; get back user pc
                  [000200]  1902  	br	r31, trap__invalid_dpte_no_dismiss	; merge to post
                  [000200]  1903  
                  [000200]  1904  ;+
                  [000200]  1905  ; Load/Store operand unalign
                  [000200]  1906  ;
                  [000200]  1907  ; We need to restore GPRs. Then we need to set up for an exception.
                  [000200]  1908  ;
                  [000200]  1909  ; Current register state:
                  [000200]  1910  ;	p5		va
                  [000200]  1911  ;	p6		mm_stat
                  [000200]  1912  ;	p7		exc_sum
                  [000200]  1913  ;	p23		exc_addr in PALcode
                  [000200]  1914  ;
                  [000200]  1915  ;	r10		fa -- move to p7
                  [000200]  1916  ;	r11		opcode -- move to proper spot in p6
                  [000200]  1917  ;-
                  [000200]  1918  trap__emul_ldst_unalign:
                  [000200]  1919  	bis	r10, r31, p7				; register number
                  [000200]  1920  	sll	r11, #EV6__MM_STAT__OPCODE__S, p6	; opcode
                  [000200]  1921  
                  [000200]  1922  	hw_ldq/p p4, PT__IMPURE(p_temp)		; impure base into p4
                  [000200]  1923  	bis	p4, r31, r1			; also put it into r1
                  [000200]  1924  	PVC_JSR	emul_restore, bsr=1
                  [000200]  1925  	bsr	r3, trap__emul_restore		; restore all but r0-r3
                  [000200]  1926  ;
                  [000200]  1927  ; Now restore the rest of the GPRs.
                  [000200]  1928  ;
                  [000200]  1929  	hw_ldq/p r0, CNS__R0_EMUL(p4)		; restore r0
                  [000200]  1930  	hw_ldq/p r1, CNS__R1_EMUL(p4)		; restore r1
                  [000200]  1931  	hw_ldq/p r2, CNS__R2_EMUL(p4)		; restore r2
                  [000200]  1932  	hw_ldq/p r3, CNS__R3_EMUL(p4)		; restore r3
                  [000200]  1933  ;
                  [000200]  1934  ; Now take an unalign exception.
                  [000200]  1935  ; Current state:
                  [000200]  1936  ;	p4		base of impure area
                  [000200]  1937  ;	p5		va
                  [000200]  1938  ;	p6		"mm_stat" with opcode from r11
                  [000200]  1939  ;	p7		register number from from r10
                  [000200]  1940  ;
                  [000200]  1941  	hw_ldq/p p23, CNS__FP_PC(p4)		; get pc back
                  [000200]  1942  	addq	p23, #4, p23			; bump to nextpc
                  [000200]  1943  
                  [000200]  1944  	br	r31, trap__unalign_nodismiss	; merge with unalign code
                  [000200]  1945  
                  [000200]  1946  ;+
                  [000200]  1947  ; Operates and branches are passed to emulator.
                  [000200]  1948  ; Current state:
                  [000200]  1949  ;	GPRs have been saved.
                  [000200]  1950  ;	CNS__FP_PC	pc
                  [000200]  1951  ;	p5		instruction
                  [000200]  1952  ;
                  [000200]  1953  ; Map a 4MB chunck of virtual to physical.
                  [000200]  1954  ; NOTE: The impure area has to be in the same naturally aligned 4mb chunk!!!
                  [000200]  1955  ;-
                  [000200]  1956  .if ndf PAL__EMUL_BASE
                  [000200]  1957  	PAL__EMUL_BASE = ^xE0000
                  [000200]  1958  .endc
                  [000200]  1959  
                  [000200]  1960  	ALIGN_FETCH_BLOCK
                  [000200]  1961  trap__emul_emul:
                  [000200]  1962  	subq	r31, #1, r8			; get a -1
                  [000200]  1963  	srl	r8, #42, r8			; shift off low bits of kseg addr
                  [000200]  1964  	sll	r8, #42, r8			; shift back into position
                  [000200]  1965  
                  [000200]  1966  	br	r1, trap__emul_entry
                  [000200]  1967  	.long	PAL__EMUL_BASE			; transfer address
                  [000200]  1968  trap__emul_entry:
                  [000200]  1969  	hw_ldl/p r27, 0(r1)			; get transfer address
                  [000200]  1970  	bis	r27, r8, r27			; transfer address as kseg
                  [000200]  1971  
                  [000200]  1972  	ALIGN_FETCH_BLOCK <^x47FF041F>
                  [000200]  1973  	hw_mfpr	r16, EV6__IER_CM		; (4,0L) get old IER_CM
                  [000200]  1974  	hw_ldq/p p4, PT__IMPURE(p_temp)		; get impure base
                  [000200]  1975  	hw_stq/p r16, CNS__IER_CM(p4)		; save old IER_CM
                  [000200]  1976  	bis	p4, r8, p4			; impure area as kseg
                  [000200]  1977  
                  [000200]  1978  	ASSUME_FETCH_BLOCK
                  [000200]  1979  	hw_mtpr r31, EV6__IER_CM		; (4,0L) ints off, cm=kernel
                  [000200]  1980  	bis	p5, r31, r16			; instruction
                  [000200]  1981  	bis	p4, r31, r17			; pointer to impure area
                  [000200]  1982  	bis	r31, r31, r31
                  [000200]  1983  
                  [000200]  1984  	ASSUME_FETCH_BLOCK
                  [000200]  1985  	lda	p6,^x400(r31)			; get a ^x400
                  [000200]  1986  	hw_ldq/p p4, PT__WHAMI(p_temp)		; get whami
                  [000200]  1987  	mulq	p4, p6, p6			; whami * ^x400
                  [000200]  1988  	subq	r27, p6, r30			; set top of stack to be kseg
                  [000200]  1989  						;   xfer addr - (whami * ^x400)
                  [000200]  1990  
                  [000200]  1991  kseg_offset = <trap__emul_kseg_done - trap__emul_kseg>
                  [000200]  1992  
                  [000200]  1993  	ASSUME_FETCH_BLOCK
                  [000200]  1994  	bis	r31, r31, r31
                  [000200]  1995  	bis	r31, r31, r31
                  [000200]  1996  	bis	r31, r31, r31
                  [000200]  1997  	br	r1, trap__emul_kseg
                  [000200]  1998  
                  [000200]  1999  	ASSUME_FETCH_BLOCK
                  [000200]  2000  trap__emul_kseg: 
                  [000200]  2001  	addq	r1, #<kseg_offset>, r1
                  [000200]  2002  	bis	r1, r8, r1			; ret as native mode kernel kseg
                  [000200]  2003  	bsr	r31, .				; push prediction stack
                  [000200]  2004  	PVC_JSR emul_kseg
                  [000200]  2005  	hw_ret_stall (r1)			; pop prediction stack
                  [000200]  2006  	PVC_JSR emul_kseg, dest=1
                  [000200]  2007  
                  [000200]  2008  trap__emul_kseg_done:
                  [000200]  2009  
                  [000200]  2010  ;
                  [000200]  2011  ; Now we are in native kernel kseg
                  [000200]  2012  ;
                  [000200]  2013  	ASSUME_FETCH_BLOCK
                  [000200]  2014  	PVC_VIOLATE <29>
                  [000200]  2015  	PVC_VIOLATE <1007>
                  [000200]  2016  	jsr	r26, (r27)			; jsr to emulator
                  [000200]  2017  ;
                  [000200]  2018  ; Return from emulation.
                  [000200]  2019  ; We are still in native kernel kseg mode.
                  [000200]  2020  ;	r0		return status
                  [000200]  2021  ;	CNS__FP_PC	updated pc
                  [000200]  2022  ;	CNS__FPCR	updated
                  [000200]  2023  ;	CNS__EXC_SUM	exception information
                  [000200]  2024  ;
                  [000200]  2025  trap__emul_return:				; return in non-pal mode
                  [000200]  2026  	lda	r16, ^xBAC(r31)			; flag to call_pal
                  [000200]  2027  	.long	^x3B				; pop back into pal mode
                  [000200]  2028  ;
                  [000200]  2029  ; Now restore IER_CM
                  [000200]  2030  ;
                  [000200]  2031  	hw_ldq/p p4, PT__IMPURE(p_temp)		; get base of impure area
                  [000200]  2032  	hw_ldq/p r16, CNS__IER_CM(p4)		; get old IER_CM back
                  [000200]  2033  	bis	r31, r31, p20			; zap unalign flag
                  [000200]  2034  	hw_mtpr	r16, EV6__IER_CM		; (4,0L) restore IER_CM
                  [000200]  2035  ;
                  [000200]  2036  ; Check r0 for status.
                  [000200]  2037  ;	r0	 0	success
                  [000200]  2038  ;		-1	arith trap
                  [000200]  2039  ;		-2	opcdec
                  [000200]  2040  ;		-4	fen (FEN from OPCDEC with FPE_STATE clear)
                  [000200]  2041  ;
                  [000200]  2042  	bne	r0, trap__emul_arith		; branch for arith or opcdec
                  [000200]  2043  	br	r31, trap__emul_done		; restore registers and return
                  [000200]  2044  
                  [000200]  2045  ;+
                  [000200]  2046  ; Arithmetic exception or opcdec or fen during emulation.
                  [000200]  2047  ;	Restore state. Merge with appropriate flow.
                  [000200]  2048  ;	Emulator left FP_PC as current pc.
                  [000200]  2049  ;-
                  [000200]  2050  trap__emul_arith:
                  [000200]  2051  	bis	r0, r31, p5			; save status
                  [000200]  2052  	bis	p4, r31, r1			; impure base into r1
                  [000200]  2053  	PVC_JSR	emul_restore, bsr=1
                  [000200]  2054  	bsr	r3, trap__emul_restore		; restore all but r0-r3
                  [000200]  2055  ;
                  [000200]  2056  ; Now restore the rest of the GPRs.
                  [000200]  2057  ;
                  [000200]  2058  	hw_ldq/p r0, CNS__R0_EMUL(p4)		; restore r0
                  [000200]  2059  	hw_ldq/p r1, CNS__R1_EMUL(p4)		; restore r1
                  [000200]  2060  	hw_ldq/p r2, CNS__R2_EMUL(p4)		; restore r2
                  [000200]  2061  	hw_ldq/p r3, CNS__R3_EMUL(p4)		; restore r3
                  [000200]  2062  ;
                  [000200]  2063  ; Current state:
                  [000200]  2064  ;	p4	base of impure area
                  [000200]  2065  ;	p5	status
                  [000200]  2066  ;		-1	arith trap
                  [000200]  2067  ;		-2	opcdec
                  [000200]  2068  ;		-4	fen (FPE_STATE clear)
                  [000200]  2069  ;
                  [000200]  2070  	hw_ldq/p p23, CNS__FP_PC(p4)		; get PC back
                  [000200]  2071  	blbc	p5, trap__emul_opcdec_or_fen	; branch for opcdec or fen
                  [000200]  2072  
                  [000200]  2073  	hw_ldq/p p7, CNS__EXC_SUM(p4)		; get emulated exc_sum
                  [000200]  2074  	br	r31, trap__arith_merge		; merge with arithmetic
                  [000200]  2075  ;
                  [000200]  2076  ; 
                  [000200]  2077  ; Opcdec
                  [000200]  2078  ;	or
                  [000200]  2079  ; Fen (FEN from OPCDEC with FPE_STATE clear)
                  [000200]  2080  ;	p5	-2	opcdec
                  [000200]  2081  ;		-4	fen (FEN from OPCDEC with FPE_STATE clear)
                  [000200]  2082  ;
                  [000200]  2083  ;	p23		user pc
                  [000200]  2084  ;
                  [000200]  2085  trap__emul_opcdec_or_fen:
                  [000200]  2086  	srl	p5, #1, p5			; shift to determine which
                  [000200]  2087  	blbc	p5, trap__emul_fen		; branch for fen
                  [000200]  2088  	br	r31, trap__opcdec_merge		; take opcdec
                  [000200]  2089  
                  [000200]  2090  .iff
                  [000200]  2091  	hw_mfpr	p23, EV6__EXC_ADDR			; (0L) save exc_addr
                  [000200]  2092  	NOP						; no conditional br
                  [000200]  2093  	NOP						;	in 1st block
                  [000200]  2094  	NOP
                  [000200]  2095  .endc
         66FF0600 [000200]  2091I 	hw_mfpr	p23, EV6__EXC_ADDR			; (0L) save exc_addr
                  [000204]  2092I 	NOP						; no conditional br
File: ev6_pal_macros.mar
         47FF041F [000204]   283i 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [000208]  2093I 	NOP						;	in 1st block
File: ev6_pal_macros.mar
         47FF041F [000208]   283i 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [00020C]  2094I 	NOP
File: ev6_pal_macros.mar
         47FF041F [00020C]   283i 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [000210]  2096  
                  [000210]  2097  trap__emul_fen:						; take real fen
                  [000210]  2098  
         F2E000C6 [000210]  2099  	blbs	p23, trap__pal_exc_bugcheck		; mchk if fen within pal
                  [000214]  2100  
         46C11004 [000214]  2101  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p4	; current mode
         46C1F014 [000218]  2102  	and	p_misc, #OSF_P_MISC__PS__M, p20		; save original ps
         E4800008 [00021C]  2103  	beq	p4, trap__fen_stack			; skip switch if kernel
                  [000220]  2104  ;
                  [000220]  2105  ; Switch to kernel mode. 
                  [000220]  2106  ;
                  [000220]  2107  fen_cm_offset = <trap__fen_stack - trap__fen_cm>
                  [000220]  2108  
         7FD51020 [000220]  2109  	hw_stq/p r30, PT__USP(p_temp)			; save user SP
         6FD51018 [000224]  2110  	hw_ldq/p r30, PT__KSP(p_temp)			; get kernel SP
         46C1F116 [000228]  2111  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc	; cm=0, ipl=0
                  [00022C]  2112  
         C0C00000 [00022C]  2113  	br	p6, trap__fen_cm			; change mode to kernel
                  [000230]  2114  trap__fen_cm:
         40C23406 [000230]  2115  	addq	p6, #<fen_cm_offset+1>, p6		; jump past in palmode
         77FF0910 [000234]  2116  	hw_mtpr	r31, EV6__PS				; (4,0L) switch to kern
         D3E00000 [000238]  2117  	bsr	r31, .					; push prediction stack
                  [00023C]  2118  	PVC_JSR	fen_cm					; synch up
File: ev6_pal_macros.mar
                  [00023C]   531i  pvc_lbl \pcv_index, \pcv_jsr_fen_cm0, osf
File: ev6_osf_pal.mar
         7BE6A000 [00023C]  2119  	hw_ret_stall (p6)				; pop prediction stack
                  [000240]  2120  	PVC_JSR	fen_cm, dest=1
File: ev6_pal_macros.mar
                  [000240]   534i  pvc_lbl \pcv_index, \pcv_jsr_fen_cm0, osf, \pcv_jsr_fen_cm0_inst
File: ev6_osf_pal.mar
                  [000240]  2121  ;
                  [000240]  2122  ; Take the trap. Be careful of tb miss!
                  [000240]  2123  ; Current state:
                  [000240]  2124  ;	p_misc__ps	if we were in kernel, original ps
                  [000240]  2125  ;			if we were in user, new ps = 0 (cm=0, ipl=0)
                  [000240]  2126  ;	p20		original ps
                  [000240]  2127  ;	p23		pc
                  [000240]  2128  ;
                  [000240]  2129  trap__fen_stack:
         7EF51060 [000240]  2130  	hw_stq/p p23, PT__STACK_PC(p_temp)		; store away pc
                  [000244]  2131  
         23DEFFD0 [000244]  2132  	lda	r30, <0-OSF_FRM__SIZE>(r30)		; allocate stack space
                  [000248]  2133  
         B69E0000 [000248]  2134  	stq	p20, OSF_FRM__PS(r30)			; save original ps
         B65E0028 [00024C]  2135  	stq	r18, OSF_FRM__A2(r30)			; save a2
                  [000250]  2136  
         6E951060 [000250]  2137  	hw_ldq/p p20, PT__STACK_PC(p_temp)		; 1.39 get pc back
                  [000254]  2138  
         B7BE0010 [000254]  2139  	stq	r29, OSF_FRM__GP(r30)			; save gp
         B61E0018 [000258]  2140  	stq	r16, OSF_FRM__A0(r30)			; save a0
         B63E0020 [00025C]  2141  	stq	r17, OSF_FRM__A1(r30)			; save a1
         B69E0008 [000260]  2142  	stq	p20, OSF_FRM__PC(r30)			; 1.39 save pc
                  [000264]  2143  
         6EF51038 [000264]  2144  	hw_ldq/p p23, PT__ENT_IF(p_temp)		; get entry point
         6FB51028 [000268]  2145  	hw_ldq/p r29, PT__KGP(p_temp)			; get kgp
         47E07410 [00026C]  2146  	bis	r31, #OSF_A0__FEN, r16			; set a0 
                  [000270]  2147  
         7BF78000 [000270]  2148  	hw_ret	(p23)					; to os
                  [000274]  2149  
                  [000274]  2150  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [000274]    57i         ASSUME <.-_start_of_last_vec> le <^x80>
                  [000274]    61M         GOTO_FREE_CODE
                  [0040C0]    67M     .align 6
File: ev6_osf_pal.mar
                  [0040C0]  2151  
                  [0040C0]  2152  
                  [0040C0]  2153  ;+
                  [0040C0]  2154  ; UNALIGN - offset 280
                  [0040C0]  2155  ;
                  [0040C0]  2156  ; Entry:
                  [0040C0]  2157  ;	Vectored in via hardware trap on unaligned Dstream reference.
                  [0040C0]  2158  ;
                  [0040C0]  2159  ; Function:
                  [0040C0]  2160  ;	Take a trap unless to x31.
                  [0040C0]  2161  ;	Build stack frame.
                  [0040C0]  2162  ;		r16 (a0)	VA
                  [0040C0]  2163  ;		r17 (a1)	Opcode
                  [0040C0]  2164  ;		r18 (a2)	Src/Dst register
                  [0040C0]  2165  ;	Vector via entUna.
                  [0040C0]  2166  ;-
                  [0040C0]  2167  
                  [0040C0]  2168  	START_HW_VECTOR <UNALIGN>
File: ev6_pal_macros.mar
                  [0040C0]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000280]    49i TRAP__UNALIGN:
File: ev6_osf_pal.mar
                  [000280]  2169  
                  [000280]  2170  ASSUME EV6__MM_STAT__WR__S eq 0
                  [000280]  2171  
         66FF0600 [000280]  2172  	hw_mfpr	p23, EV6__EXC_ADDR		; (0L) get exc_addr
         64FF0F00 [000284]  2173  	hw_mfpr p7, EV6__EXC_SUM		; (0L) get register field
         64DF2700 [000288]  2174  	hw_mfpr p6, EV6__MM_STAT		; (0L) opcode, r/w bit
         64BFC2F0 [00028C]  2175  	hw_mfpr	p5, EV6__VA			; (4-7,1L) get va
                  [000290]  2176  
                  [000290]  2177  .if eq ev6_p1
                  [000290]  2178  	blbs	p23, trap__pal_exc_bugcheck	; mchk if within pal
                  [000290]  2179  .iff
                  [000290]  2180  	blbs	p23, trap__unalign_check_fp	; check for fp ld/st problem
                  [000290]  2181  .endc
         F2E000A6 [000290]  2178I 	blbs	p23, trap__pal_exc_bugcheck	; mchk if within pal
                  [000294]  2182  
         42E09417 [000294]  2183  	addq	p23, #4, p23			; bump to nextpc
                  [000298]  2184  
         48E11687 [000298]  2185  	srl	p7, #EV6__EXC_SUM__REG__S, p7	; shift register number
         44E3F007 [00029C]  2186  	and	p7, #EV6__EXC_SUM__REG__M, p7	; clean register number
         F0C00F87 [0002A0]  2187  	blbs	p6, trap__unalign_nodismiss	; store => take a trap
                  [0002A4]  2188  ;
                  [0002A4]  2189  ; Check load to x31, which we dismiss.
                  [0002A4]  2190  ;
         40E3F5A4 [0002A4]  2191  	cmpeq	p7, #^x1F, p4			; check for x31
         E4800F85 [0002A8]  2192  	beq	p4, trap__unalign_nodismiss	; not x31 => nodismiss
                  [0002AC]  2193  ;
                  [0002AC]  2194  ; Dismiss the load x31
                  [0002AC]  2195  ;
         63FF4000 [0002AC]  2196  	mb					; protect mm_stat and va
         7BF78000 [0002B0]  2197  	hw_ret	(p23)				; return
                  [0002B4]  2198  
                  [0002B4]  2199  	CONT_HW_VECTOR
File: ev6_pal_macros.mar
                  [0002B4]    76M     ASSUME <_pal_vec_cont> eq 0
                  [0002B4]    84M     ASSUME <.-_start_of_last_vec> le <^x80>
                  [0002B4]    86M     GOTO_FREE_CODE
                  [0040C0]    67M     .align 6
File: ev6_osf_pal.mar
                  [0040C0]  2200  ;
                  [0040C0]  2201  ; Take a trap.
                  [0040C0]  2202  ;
                  [0040C0]  2203  trap__unalign_nodismiss:
         63FF4000 [0040C0]  2204  	mb						; protect mm_stat and va
                  [0040C4]  2205  
         46C11004 [0040C4]  2206  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p4	; current mode
         46C1F014 [0040C8]  2207  	and	p_misc, #OSF_P_MISC__PS__M, p20		; save original ps
         E4800008 [0040CC]  2208  	beq	p4, trap__unalign_stack			; skip switch if kernel
                  [0040D0]  2209  ;
                  [0040D0]  2210  ; Switch to kernel mode. 
                  [0040D0]  2211  ;
                  [0040D0]  2212  unalign_cm_offset = <trap__unalign_stack - trap__unalign_cm>
                  [0040D0]  2213  
         7FD51020 [0040D0]  2214  	hw_stq/p r30, PT__USP(p_temp)			; save user SP
         6FD51018 [0040D4]  2215  	hw_ldq/p r30, PT__KSP(p_temp)			; get kernel SP
         46C1F116 [0040D8]  2216  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc	; cm=0, ipl=0
                  [0040DC]  2217  
         C0800000 [0040DC]  2218  	br	p4, trap__unalign_cm			; change mode to kernel
                  [0040E0]  2219  trap__unalign_cm:
         40823404 [0040E0]  2220  	addq	p4, #<unalign_cm_offset+1>, p4		; jump past in palmode
         77FF0910 [0040E4]  2221  	hw_mtpr	r31, EV6__PS				; (4,0L) switch to kern
         D3E00000 [0040E8]  2222  	bsr	r31, .					; push prediction stack
                  [0040EC]  2223  	PVC_JSR	unalign_cm				; synch up
File: ev6_pal_macros.mar
                  [0040EC]   531i  pvc_lbl \pcv_index, \pcv_jsr_unalign_cm0, osf
File: ev6_osf_pal.mar
         7BE4A000 [0040EC]  2224  	hw_ret_stall (p4)				; pop prediction stack
                  [0040F0]  2225  	PVC_JSR	unalign_cm, dest=1
File: ev6_pal_macros.mar
                  [0040F0]   534i  pvc_lbl \pcv_index, \pcv_jsr_unalign_cm0, osf, \pcv_jsr_unalign_cm0_inst
File: ev6_osf_pal.mar
                  [0040F0]  2226  ;
                  [0040F0]  2227  ; Take the trap. Be careful of tb miss!
                  [0040F0]  2228  ; Current state:
                  [0040F0]  2229  ;	p5		va
                  [0040F0]  2230  ;	p6		mm_stat
                  [0040F0]  2231  ;	p7		register number
                  [0040F0]  2232  ;	p20		original ps
                  [0040F0]  2233  ;	p23		nextpc
                  [0040F0]  2234  ;	p_misc__ps	if we were in kernel, original ps
                  [0040F0]  2235  ;			if we were in user, new ps = 0 (cm=0, ipl=0)
                  [0040F0]  2236  ;
                  [0040F0]  2237  trap__unalign_stack:
         7EF51060 [0040F0]  2238  	hw_stq/p p23, PT__STACK_PC(p_temp)		; store away nextpc
         48C09686 [0040F4]  2239  	srl	p6, #EV6__MM_STAT__OPCODE__S, p6	; get opcode
         44C7F006 [0040F8]  2240  	and	p6, #EV6__MM_STAT__OPCODE__M, p6	; clean it
         7CB51068 [0040FC]  2241  	hw_stq/p p5, PT__NEW_A0(p_temp)			; save away va
         7CD51070 [004100]  2242  	hw_stq/p p6, PT__NEW_A1(p_temp)			; save away opcode
         7CF51078 [004104]  2243  	hw_stq/p p7, PT__NEW_A2(p_temp)			; save away reg number
                  [004108]  2244  
         23DEFFD0 [004108]  2245  	lda	r30, <0-OSF_FRM__SIZE>(r30)		; allocate stack space
                  [00410C]  2246  
         B69E0000 [00410C]  2247  	stq	p20, OSF_FRM__PS(r30)			; save original ps
         B65E0028 [004110]  2248  	stq	r18, OSF_FRM__A2(r30)			; save a2
                  [004114]  2249  
         6E951060 [004114]  2250  	hw_ldq/p p20, PT__STACK_PC(p_temp)		; 1.39 get nextpc back
                  [004118]  2251  
         B7BE0010 [004118]  2252  	stq	r29, OSF_FRM__GP(r30)			; save gp
         B61E0018 [00411C]  2253  	stq	r16, OSF_FRM__A0(r30)			; save a0
         B63E0020 [004120]  2254  	stq	r17, OSF_FRM__A1(r30)			; save a1
         B69E0008 [004124]  2255  	stq	p20, OSF_FRM__PC(r30)			; 1.39 save nextpc
                  [004128]  2256  
         6EF51058 [004128]  2257  	hw_ldq/p p23, PT__ENT_UNA(p_temp)		; get entry point
         6FB51028 [00412C]  2258  	hw_ldq/p r29, PT__KGP(p_temp)			; get kgp
         6E151068 [004130]  2259  	hw_ldq/p r16, PT__NEW_A0(p_temp)		; a0 <- va
         6E351070 [004134]  2260  	hw_ldq/p r17, PT__NEW_A1(p_temp)		; a1 <- opcode
         6E551078 [004138]  2261  	hw_ldq/p r18, PT__NEW_A2(p_temp)		; a2 <- register number
                  [00413C]  2262  
         7BF78000 [00413C]  2263  	hw_ret	(p23)					; to os
                  [004140]  2264  
                  [004140]  2265  ;
                  [004140]  2266  ; We turn ld/st unaligns into alignment traps.
                  [004140]  2267  ; Current state:
                  [004140]  2268  ;	p5	va
                  [004140]  2269  ;	p6	mm_stat (opcode, r/w bit)
                  [004140]  2270  ;	p7	exc_sum (register field)
                  [004140]  2271  ;	p23	exc_addr
                  [004140]  2272  ;
                  [004140]  2273  .if ne ev6_p1
                  [004140]  2274  trap__unalign_check_fp:
                  [004140]  2275  	bic	p23, #3, p4		; clean PAL pc
                  [004140]  2276  	hw_mfpr	p20, EV6__PAL_BASE	; (4,0L) get pal base
                  [004140]  2277  	subq	p20, p4, p4		; pal base - cleaned pc
                  [004140]  2278  
                  [004140]  2279  	lda	p20, <trap__emul_ldf - trap__pal_base>(p4)
                  [004140]  2280  	beq	p20, trap__emul_ldst_unalign
                  [004140]  2281  	
                  [004140]  2282  	lda	p20, <trap__emul_ldg - trap__pal_base>(p4)
                  [004140]  2283  	beq	p20, trap__emul_ldst_unalign
                  [004140]  2284  	
                  [004140]  2285  	lda	p20, <trap__emul_lds - trap__pal_base>(p4)
                  [004140]  2286  	beq	p20, trap__emul_ldst_unalign
                  [004140]  2287  	
                  [004140]  2288  	lda	p20, <trap__emul_ldt - trap__pal_base>(p4)
                  [004140]  2289  	beq	p20, trap__emul_ldst_unalign
                  [004140]  2290  	
                  [004140]  2291  	lda	p20, <trap__emul_stf_s - trap__pal_base>(p4)
                  [004140]  2292  	beq	p20, trap__emul_ldst_unalign
                  [004140]  2293  	
                  [004140]  2294  	lda	p20, <trap__emul_stg_s - trap__pal_base>(p4)
                  [004140]  2295  	beq	p20, trap__emul_ldst_unalign
                  [004140]  2296  	
                  [004140]  2297  	lda	p20, <trap__emul_sts_s - trap__pal_base>(p4)
                  [004140]  2298  	beq	p20, trap__emul_ldst_unalign
                  [004140]  2299  	
                  [004140]  2300  	lda	p20, <trap__emul_stt_s - trap__pal_base>(p4)
                  [004140]  2301  	beq	p20, trap__emul_ldst_unalign
                  [004140]  2302  
                  [004140]  2303  	br	r31, trap__pal_exc_bugcheck	; mchk otherwise
                  [004140]  2304  
                  [004140]  2305  .endc
                  [004140]  2306  
                  [004140]  2307  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [004140]    61M         GOTO_FREE_CODE
                  [004140]    67M     .align 6
File: ev6_osf_pal.mar
                  [004140]  2308  
                  [004140]  2309  ;+
                  [004140]  2310  ; DTBM_SINGLE - offset 300
                  [004140]  2311  ;
                  [004140]  2312  ; Entry:
                  [004140]  2313  ;	Vectored into via hardware trap on Dstream single
                  [004140]  2314  ;	translation buffer miss.
                  [004140]  2315  ;
                  [004140]  2316  ; Function:
                  [004140]  2317  ;	Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid.
                  [004140]  2318  ;	Can trap into double.
                  [004140]  2319  ;
                  [004140]  2320  ; Note:
                  [004140]  2321  ;	We want to keep the main flow in a single cache line
                  [004140]  2322  ;	(4 fetch blocks) to be as efficient as possible.
                  [004140]  2323  ;
                  [004140]  2324  ;	The update of the TB occurs on the when the write to PTE1 retires.
                  [004140]  2325  ;
                  [004140]  2326  ; NOTE:
                  [004140]  2327  ;	1-to-1 mapping scheme implemented with bit in p_misc shadow register.
                  [004140]  2328  ;
                  [004140]  2329  ; Register use:
                  [004140]  2330  ;	p4	shadow register reserved for itb/dtb miss
                  [004140]  2331  ;	p5	shadow register reserved for itb/dtb miss
                  [004140]  2332  ;	p6	shadow register reserved for itb/dtb miss
                  [004140]  2333  ;	p7	shadow register reserved for itb/dtb miss
                  [004140]  2334  ;	p_misc	physical mode bit in <63>
                  [004140]  2335  ;	p23	exc_addr, pc of instruction causing DTB miss
                  [004140]  2336  ;
                  [004140]  2337  ; Exit state:
                  [004140]  2338  ;	On exit to trap__invalid_dpte
                  [004140]  2339  ;	p4	PTE
                  [004140]  2340  ;	p5	no double miss: mm_stat 
                  [004140]  2341  ;		double miss: scratch
                  [004140]  2342  ;	p6	va
                  [004140]  2343  ;	p7	no double miss: exc_sum 
                  [004140]  2344  ;		double miss: <31:16>=mm_stat<15:0>,<15:1>=exc_sum<15:1>,<0>=1
                  [004140]  2345  ;	p23	pc of instruction causing DTB miss
                  [004140]  2346  ;
                  [004140]  2347  ;
                  [004140]  2348  ; Note on scoreboarding and register dependencies: Having (4-7) on the
                  [004140]  2349  ; VA/VA_FORM register reads ensures that they don't issue until all of the
                  [004140]  2350  ; previous dtb miss's tag/pte writes have retired. The register dependency
                  [004140]  2351  ; between the VA/VA_FORM read and the tag/pte writes ensures that none
                  [004140]  2352  ; of the tag/pte issue until all of the previous tag/pte writes from
                  [004140]  2353  ; a previous miss have retired.
                  [004140]  2354  ;
                  [004140]  2355  ; How to squeeze 5 pegs into 4 holes:
                  [004140]  2356  ; 	Before fetching the vpte, we clear the low bit of p7.
                  [004140]  2357  ;	If we take a double miss, we squeeze mm_stat and exc_sum into p7,
                  [004140]  2358  ;		setting the low bit to indicate we took a double miss.
                  [004140]  2359  ;	The invalid_pte code checks p7 and restores p5 if indicated.
                  [004140]  2360  ;-
                  [004140]  2361  	START_HW_VECTOR <DTBM_SINGLE>
File: ev6_pal_macros.mar
                  [004140]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000300]    49i TRAP__DTBM_SINGLE:
File: ev6_osf_pal.mar
                  [000300]  2362  
                  [000300]  2363  ASSUME OSF_P_MISC__PHYS__S eq 63
                  [000300]  2364  
         66FF0600 [000300]  2365  	hw_mfpr	p23, EV6__EXC_ADDR		; (0L) get exception address
         649FC3F0 [000304]  2366  	hw_mfpr	p4, EV6__VA_FORM		; (4-7,1L) get vpte address
         64BF2700 [000308]  2367  	hw_mfpr	p5, EV6__MM_STAT		; (0L) get miss info
         64FF0F00 [00030C]  2368  	hw_mfpr p7, EV6__EXC_SUM		; (0L) get exc_sum for ra
                  [000310]  2369  
         64DFC2F0 [000310]  2370  	hw_mfpr p6, EV6__VA			; (4-7,1L) get original va
         44E03107 [000314]  2371  	bic	p7, #1, p7			; clear double miss flag
                  [000318]  2372  
         44860804 [000318]  2373  	xor	p4, p6, p4			; interlock p4 and p6
         44860804 [00031C]  2374  	xor	p4, p6, p4			; restore p4
                  [000320]  2375  
                  [000320]  2376  .if ne kseg_hack					; kseg hack
                  [000320]  2377  	hw_stq/p p7, PT__RSV_FOR_PAL(p_temp)		; save off p7
                  [000320]  2378  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p7	; current mode
                  [000320]  2379  	beq	p7, trap__hack_kseg			; do hack for kseg
                  [000320]  2380  	hw_ldq/p p7, PT__RSV_FOR_PAL(p_temp)		; restore p7
                  [000320]  2381  	br	r31, trap__dtbm_single_vpte		; as we were
                  [000320]  2382  
                  [000320]  2383  	CONT_HW_VECTOR					; 1.41
                  [000320]  2384  .endc
                  [000320]  2385  
                  [000320]  2386  trap__dtbm_single_vpte:
         6C845000 [000320]  2387  	hw_ldq/v p4, (p4)			; (1L) get vpte
                  [000324]  2388  
                  [000324]  2389  .if eq srm_console				; 1.49
                  [000324]  2390  	blt	p_misc, trap__d1to1		; (xU) <63>=1 => 1-to-1
                  [000324]  2391  .endc						; 1.49 srm_console
         EAC00FD5 [000324]  2390I 	blt	p_misc, trap__d1to1		; (xU) <63>=1 => 1-to-1
         E0800F85 [000328]  2392  	blbc	p4, trap__invalid_dpte		; (xU) invalid => branch
                  [00032C]  2393  ;
                  [00032C]  2394  ; We need to avoid the situation where a ldx_l has acquired a lock,
                  [00032C]  2395  ; another processor has taken it, and a bad path before a stx_c has
                  [00032C]  2396  ; a load which pulls the data back in and makes it look like the
                  [00032C]  2397  ; lock has succeeded. So we either need to do a virtual load
                  [00032C]  2398  ; or hold up bad path loads by doing a sequence of mulq and
                  [00032C]  2399  ; a write to MM_STAT with bit 2 and 6 (6 is required or we hang).
                  [00032C]  2400  ;
                  [00032C]  2401  ; 1.50
                  [00032C]  2402  ; For the pte_eco case, do a ldbu down every path except the
                  [00032C]  2403  ; i/o case, where we couldn't have missed on a stx_c.
                  [00032C]  2404  ; 1.50
                  [00032C]  2405  ;
                  [00032C]  2406  .if eq force_path2				; 1.45
                  [00032C]  2407  	and	p4, #^x80, p7			; isolate mb bit
                  [00032C]  2408  	xor	p7, #^x80, p7			; flip mb bit
                  [00032C]  2409  .iff						; 1.45
                  [00032C]  2410  	srl	p4, #62, p5			; get i/o space bit
                  [00032C]  2411  	and	p5, #1, p5			; isolate i/o space bit
                  [00032C]  2412  .endc						; 1.45
         44901007 [00032C]  2407I 	and	p4, #^x80, p7			; isolate mb bit
         44F01807 [000330]  2408I 	xor	p7, #^x80, p7			; flip mb bit
                  [000334]  2413  
                  [000334]  2414  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
47FF041F 47FF041F [000334]   265i 	.align 4, <^x47FF041F>
         47FF041F [00033C]
File: ev6_osf_pal.mar
                  [000340]  2415  
                  [000340]  2416  	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [000340]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         77E62044 [000340]  2417  	hw_mtpr	p6, EV6__DTB_TAG0		; (2&6,0L) write tag0
         77E6A022 [000344]  2418  	hw_mtpr p6, EV6__DTB_TAG1		; (1&5,1L) write tag1
         77E42155 [000348]  2419  	hw_mtpr	p4, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
         77E4A1AA [00034C]  2420  	hw_mtpr	p4, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [000350]  2421  
                  [000350]  2422  .if ne force_path2				; 1.45
                  [000350]  2423  	and	p4, #^xe0, p7			; isolate mb, GH bits
                  [000350]  2424  	xor	p7, #^x80, p7			; flip mb bit
                  [000350]  2425  	bis	p7, p5, p7			; merge bits
                  [000350]  2426  .endc
                  [000350]  2427  
                  [000350]  2428  ASSUME <tb_mb_en + pte_eco> ne 2
                  [000350]  2429  
                  [000350]  2430  .if ne pte_eco
                  [000350]  2431  	bne	p7, trap__dtbm_single_gh_mb_io	; 1.45 branch for mb
                  [000350]  2432  
                  [000350]  2433    .if ne force_path2				; 1.45
                  [000350]  2434  trap__dtbm_single_hack1:
                  [000350]  2435  	ldbu	r31, (p6)			; do a virtual operation
                  [000350]  2436    .endc						; 1.45
                  [000350]  2437  
                  [000350]  2438  	hw_ret	(p23)				; return
                  [000350]  2439  
                  [000350]  2440    .if ne force_path2				; 1.41
                  [000350]  2441  	CONT_HW_VECTOR
                  [000350]  2442    .endc						; 1.41
                  [000350]  2443  
                  [000350]  2444  trap__dtbm_single_gh_mb_io:
                  [000350]  2445    .if ne force_path2
                  [000350]  2446  	and	p7, #^x81, p5			; check io,mb bits
                  [000350]  2447  	bne	p5, trap__dtbm_single_mb_io	; continue for GH case
                  [000350]  2448  	hw_mtpr p6, <EV6__VA ! ^x22>		; hold up loads
                  [000350]  2449  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
                  [000350]  2450  trap__dtbm_single_hack2:
                  [000350]  2451  	ldbu	r31, (p6)
                  [000350]  2452  	hw_ret	(p23)				; return
                  [000350]  2453  
                  [000350]  2454  trap__dtbm_single_mb_io:
                  [000350]  2455  	blbs	p7, trap__dtbm_single_io	; continue for mb case
                  [000350]  2456  	mb
                  [000350]  2457  	hw_mtpr p6, <EV6__VA ! ^x22>		; hold up loads
                  [000350]  2458  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
                  [000350]  2459  trap__dtbm_single_hack3:
                  [000350]  2460  	ldbu	r31, (p6)
                  [000350]  2461  	hw_ret	(p23)				; return
                  [000350]  2462  
                  [000350]  2463  trap__dtbm_single_io:
                  [000350]  2464    .endc						; force_path2
                  [000350]  2465  	mb
                  [000350]  2466  	hw_ret	(p23)				; return
                  [000350]  2467  
                  [000350]  2468  .iff						; 1.45 no need to be clever
                  [000350]  2469  
                  [000350]  2470    .if ne force_path2				; 1.45
                  [000350]  2471  	mb
                  [000350]  2472  	ALIGN_FETCH_BLOCK <^x47FF041F>
                  [000350]  2473  	mulq	p6, #1, p6			; hold up loads
                  [000350]  2474  	mulq	p6, #1, p6			; hols up loads
                  [000350]  2475  	hw_mtpr p6, <EV6__VA ! ^x22>		; hold up loads
                  [000350]  2476    .endc						; 1.45
                  [000350]  2477  
                  [000350]  2478  	hw_ret	(p23)				; return
                  [000350]  2479  .endc
         F4E00001 [000350]  2431I 	bne	p7, trap__dtbm_single_gh_mb_io	; 1.45 branch for mb
                  [000354]  2432I 
                  [000354]  2433I   .if ne force_path2				; 1.45
                  [000354]  2434I trap__dtbm_single_hack1:
                  [000354]  2435I 	ldbu	r31, (p6)			; do a virtual operation
                  [000354]  2436I   .endc						; 1.45
                  [000354]  2437I 
         7BF78000 [000354]  2438I 	hw_ret	(p23)				; return
                  [000358]  2439I 
                  [000358]  2440I   .if ne force_path2				; 1.41
                  [000358]  2441I 	CONT_HW_VECTOR
                  [000358]  2442I   .endc						; 1.41
                  [000358]  2443I 
                  [000358]  2444I trap__dtbm_single_gh_mb_io:
                  [000358]  2445I   .if ne force_path2
                  [000358]  2446I 	and	p7, #^x81, p5			; check io,mb bits
                  [000358]  2447I 	bne	p5, trap__dtbm_single_mb_io	; continue for GH case
                  [000358]  2448I 	hw_mtpr p6, <EV6__VA ! ^x22>		; hold up loads
                  [000358]  2449I 	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
                  [000358]  2450I trap__dtbm_single_hack2:
                  [000358]  2451I 	ldbu	r31, (p6)
                  [000358]  2452I 	hw_ret	(p23)				; return
                  [000358]  2453I 
                  [000358]  2454I trap__dtbm_single_mb_io:
                  [000358]  2455I 	blbs	p7, trap__dtbm_single_io	; continue for mb case
                  [000358]  2456I 	mb
                  [000358]  2457I 	hw_mtpr p6, <EV6__VA ! ^x22>		; hold up loads
                  [000358]  2458I 	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
                  [000358]  2459I trap__dtbm_single_hack3:
                  [000358]  2460I 	ldbu	r31, (p6)
                  [000358]  2461I 	hw_ret	(p23)				; return
                  [000358]  2462I 
                  [000358]  2463I trap__dtbm_single_io:
                  [000358]  2464I   .endc						; force_path2
         63FF4000 [000358]  2465I 	mb
         7BF78000 [00035C]  2466I 	hw_ret	(p23)				; return
                  [000360]  2467I 
                  [000360]  2480  
                  [000360]  2481  .if eq force_path2				; 1.41
                  [000360]  2482  	CONT_HW_VECTOR
                  [000360]  2483  .endc						; 1.41
                  [000360]  2482I 	CONT_HW_VECTOR
File: ev6_pal_macros.mar
                  [000360]    76i     ASSUME <_pal_vec_cont> eq 0
                  [000360]    84i     ASSUME <.-_start_of_last_vec> le <^x80>
                  [000360]    86i     GOTO_FREE_CODE
                  [004140]    67i     .align 6
File: ev6_osf_pal.mar
                  [004140]  2484  
                  [004140]  2485  
                  [004140]  2486  .if ne kseg_hack				; kseg hack
                  [004140]  2487  ;
                  [004140]  2488  ; tsunami hack
                  [004140]  2489  ; current state:
                  [004140]  2490  ;	p23	return address
                  [004140]  2491  ;	p6	va
                  [004140]  2492  ; Avoid issuing DTB write until the PALcode path is verified.
                  [004140]  2493  ; Add a scoreboard interlock to avoid speculative reads.
                  [004140]  2494  ; We won't return until we have committed the DTB write.
                  [004140]  2495  ;
                  [004140]  2496  
                  [004140]  2497  trap__hack_kseg:				; do hack for kseg
                  [004140]  2498  	srl	p6, #41, p7			; get <47:41>
                  [004140]  2499  	and	p7, #^x7F, p7			; clean <47:41>
                  [004140]  2500  	cmpeq	p7, #^x7E, p7			; kseg?
                  [004140]  2501  	beq	p7, trap__hack_kseg_not		; branch if not
                  [004140]  2502  	br	r31, trap__hack_kseg_bits	; test bits
                  [004140]  2503  
                  [004140]  2504  trap__hack_kseg_not:				; not kseg
                  [004140]  2505  	srl	p6, #46, p7			; check for <47:46>
                  [004140]  2506  	and	p7, #^x3, p7			; clean <47:46>
                  [004140]  2507  	cmpeq	p7, #^x2, p7			; 48 bit kseg?
                  [004140]  2508  	beq	p7, trap__hack_kseg_not2	; branch if not
                  [004140]  2509  	br	r31, trap__hack_kseg_bits2	; test bits
                  [004140]  2510  
                  [004140]  2511  trap__hack_kseg_not2:
                  [004140]  2512  	hw_ldq/p p7, PT__RSV_FOR_PAL(p_temp)	; restore p7
                  [004140]  2513  	br	r31, trap__dtbm_single_vpte	; as we were
                  [004140]  2514  
                  [004140]  2515  trap__hack_kseg_bits:				; kseg
                  [004140]  2516  	srl	p6, #40, p7			; check <40> (IO)
                  [004140]  2517  	blbs	p7, trap__hack_kseg_bits_io	; branch for io
                  [004140]  2518  	srl	p6, #32, p7			; check <34:32>
                  [004140]  2519  	and	p7, #^x7, p7			; any bits 1?
                  [004140]  2520  	bne	p7, trap__hack_kseg_hack	; branch if so
                  [004140]  2521  	beq	p7, trap__hack_kseg_bits_io	; branch if not
                  [004140]  2522  	PVC_VIOLATE <1006>
                  [004140]  2523  	br	r31, .-4			; infinite loop
                  [004140]  2524  trap__hack_kseg_bits_io:			; merge for io addr
                  [004140]  2525  	bis	p6, r31, p7			; 1to1 translation into p7
                  [004140]  2526  	br	r31, trap__hack_kseg_1to1	; now map 1to1
                  [004140]  2527  
                  [004140]  2528  trap__hack_kseg_hack:				; force nxm
                  [004140]  2529  	bis	r31, #1, p7			; get a 1
                  [004140]  2530  	sll	p7, #35, p7			; move into <35>
                  [004140]  2531  	bis	p6, p7, p7			; or into translation
                  [004140]  2532  
                  [004140]  2533  trap__hack_kseg_1to1:
                  [004140]  2534  	sll	p7, #23, p7			; <40> to position 63
                  [004140]  2535  	sra	p7, #23, p7			; force sign extension
                  [004140]  2536  	sll	p7, #20, p7			; <43> to position 63
                  [004140]  2537  	srl	p7, #20, p7			; translation
                  [004140]  2538  
                  [004140]  2539  	lda	p5, ^x1171(r31)				; KxE,GH=3,ASM=1,V=1
                  [004140]  2540  	srl	p7, #<13+9>, p4				; byte offset+9
                  [004140]  2541  	sll	p4, #<EV6__DTB_PTE0__PFN__S+9>, p4	; pfn into position
                  [004140]  2542  	bis	p4, p5, p4				; produce the pte
                  [004140]  2543  
                  [004140]  2544  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
                  [004140]  2545  
                  [004140]  2546  	PVC_VIOLATE <2>				; ignore scoreboard violation
                  [004140]  2547  	hw_mtpr	p6, EV6__DTB_TAG0		; (2&6,0L) write tag0
                  [004140]  2548  	hw_mtpr p6, EV6__DTB_TAG1		; (1&5,1L) write tag1
                  [004140]  2549  	hw_mtpr	p4, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
                  [004140]  2550  	hw_mtpr	p4, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [004140]  2551  
                  [004140]  2552  	hw_mtpr	r31, <EV6__MM_STAT ! ^xF0>	; (4-7,0L) stall outside IQ
                  [004140]  2553  	hw_ret	(p23)				; (0L) return
                  [004140]  2554  
                  [004140]  2555  trap__hack_kseg_bits2:				; kseg
                  [004140]  2556  	srl	p6, #43, p7			; check <43> (IO)
                  [004140]  2557  	blbs	p7, trap__hack_kseg_bits2_io	; branch if io
                  [004140]  2558  	srl	p6, #32, p7			; check <34:32>
                  [004140]  2559  	and	p7, #^x7, p7			; any bits 1?
                  [004140]  2560  	bne	p7, trap__hack_kseg_hack2	; branch if so
                  [004140]  2561  	beq	p7, trap__hack_kseg_bits2_io	; branch if not
                  [004140]  2562  	PVC_VIOLATE <1006>
                  [004140]  2563  	br	r31, .-4			; infinite loop
                  [004140]  2564  trap__hack_kseg_bits2_io:			; merge for io
                  [004140]  2565  	bis	p6, r31, p7			; 1to1 translation into p7
                  [004140]  2566  	br	r31, trap__hack_kseg_1to1_2	; now map 1to1
                  [004140]  2567  
                  [004140]  2568  trap__hack_kseg_hack2:				; force nxm
                  [004140]  2569  	bis	r31, #1, p7			; get a 1
                  [004140]  2570  	sll	p7, #35, p7			; move into <35>
                  [004140]  2571  	bis	p6, p7, p7			; or into translation
                  [004140]  2572  
                  [004140]  2573  trap__hack_kseg_1to1_2:
                  [004140]  2574  	sll	p7, #20, p7			; <43> to position 63
                  [004140]  2575  	srl	p7, #20, p7			; translation
                  [004140]  2576  
                  [004140]  2577  	lda	p5, ^x1171(r31)				; KxE,GH=3,ASM=1,V=1
                  [004140]  2578  	srl	p7, #<13+9>, p4				; byte offset+9
                  [004140]  2579  	sll	p4, #<EV6__DTB_PTE0__PFN__S+9>, p4	; pfn into position
                  [004140]  2580  	bis	p4, p5, p4				; produce the pte
                  [004140]  2581  
                  [004140]  2582  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
                  [004140]  2583  
                  [004140]  2584  	PVC_VIOLATE <2>				; ignore scoreboard violation
                  [004140]  2585  	hw_mtpr	p6, EV6__DTB_TAG0		; (2&6,0L) write tag0
                  [004140]  2586  	hw_mtpr p6, EV6__DTB_TAG1		; (1&5,1L) write tag1
                  [004140]  2587  	hw_mtpr	p4, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
                  [004140]  2588  	hw_mtpr	p4, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [004140]  2589  
                  [004140]  2590  	hw_mtpr	r31, <EV6__MM_STAT ! ^xF0>	; (4-7,0L) stall outside IQ
                  [004140]  2591  	hw_ret	(p23)				; (0L) return
                  [004140]  2592  .endc
                  [004140]  2593  
                  [004140]  2594  ;+
                  [004140]  2595  ; trap__invalid_dpte
                  [004140]  2596  ;
                  [004140]  2597  ; Entry:
                  [004140]  2598  ;	Branched to on invalid Dstream PTE fetched by DTB miss routine.
                  [004140]  2599  ;
                  [004140]  2600  ; Function:
                  [004140]  2601  ;	Prepare to take a Translation Not Valid or Access Violation
                  [004140]  2602  ;	exception. Take a different flow for pal mode.
                  [004140]  2603  ;
                  [004140]  2604  ; Current state:
                  [004140]  2605  ;	p4	PTE
                  [004140]  2606  ;	p5	no double miss: mm_stat 
                  [004140]  2607  ;		double miss: scratch
                  [004140]  2608  ;	p6	va
                  [004140]  2609  ;	p7	no double miss: exc_sum 
                  [004140]  2610  ;		double miss: <31:16>=mm_stat<15:0>,<15:1>=exc_sum<15:1>,<0>=1
                  [004140]  2611  ;	p23	pc of instruction taking DTB miss
                  [004140]  2612  ;
                  [004140]  2613  ; Register use:
                  [004140]  2614  ;	p20	available once we know we didn't trap from pal mode
                  [004140]  2615  ;
                  [004140]  2616  ;-
                  [004140]  2617  trap__invalid_dpte:
         F0E00001 [004140]  2618  	blbs	p7, trap__invalid_dpte_get	; did we double miss?
         C3E00001 [004144]  2619  	br	r31, trap__invalid_dpte_have	; we didn't
                  [004148]  2620  
                  [004148]  2621  trap__invalid_dpte_get:				; we double missed
         48E21685 [004148]  2622  	srl	p7, #16, p5			; recover mm_stat
                  [00414C]  2623  
                  [00414C]  2624  trap__invalid_dpte_have:
         F2E00031 [00414C]  2625  	blbs	p23, trap__tnv_in_pal			; TNV in pal mode
                  [004150]  2626  
         E0A00005 [004150]  2627  	blbc	p5, trap__invalid_dpte_check		; load => check x31
                  [004154]  2628  
         48A09687 [004154]  2629  	srl	p5, #EV6__MM_STAT__OPCODE__S, p7	; get opcode
         44E7F007 [004158]  2630  	and	p7, #EV6__MM_STAT__OPCODE__M, p7	; clean it
         40E315A7 [00415C]  2631  	cmpeq	p7, #^x18, p7				; ECB/WH64?
         F4E0002A [004160]  2632  	bne	p7, trap__invalid_dpte_dismiss		; dismiss if so
                  [004164]  2633  
         C3E00004 [004164]  2634  	br	r31, trap__invalid_dpte_no_dismiss	; store
                  [004168]  2635  ;
                  [004168]  2636  ; Check for load x31
                  [004168]  2637  ;
                  [004168]  2638  trap__invalid_dpte_check:
         48E11687 [004168]  2639  	srl	p7, #EV6__EXC_SUM__REG__S, p7	; get ra field
         44E3F007 [00416C]  2640  	and	p7, #EV6__EXC_SUM__REG__M, p7	; check for load x31
         40E3F5A7 [004170]  2641  	cmpeq	p7, #^x1F, p7			; compare against x31
         F4E00025 [004174]  2642  	bne	p7, trap__invalid_dpte_dismiss	; branch => dismiss
                  [004178]  2643  ;
                  [004178]  2644  ; Take a trap.
                  [004178]  2645  ;
                  [004178]  2646  trap__invalid_dpte_no_dismiss:
         63FF4000 [004178]  2647  	mb						; protect mm_stat and va
                  [00417C]  2648  
         46C11007 [00417C]  2649  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p7	; current mode
         46C1F014 [004180]  2650  	and	p_misc, #OSF_P_MISC__PS__M, p20		; save original ps
         E4E00009 [004184]  2651  	beq	p7, trap__invalid_dpte_stack		; skip switch if kernel
                  [004188]  2652  ;
                  [004188]  2653  ; Switch to kernel mode.
                  [004188]  2654  ; Current state:
                  [004188]  2655  ;	p4		PTE
                  [004188]  2656  ;	p20		original ps
                  [004188]  2657  ;
                  [004188]  2658  dpte_cm_offset = <trap__invalid_dpte_stack - trap__invalid_dpte_cm>
                  [004188]  2659  
         7FD51020 [004188]  2660  	hw_stq/p r30, PT__USP(p_temp)				; save user SP
         6FD51018 [00418C]  2661  	hw_ldq/p r30, PT__KSP(p_temp)				; get kernel SP
         48803684 [004190]  2662  	srl	p4, #<OSF_PTE__URE__S - OSF_PTE__KRE__S>, p4	; shift u to k
         46C1F116 [004194]  2663  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc		; cm=0, ipl=0
                  [004198]  2664  
         C0E00000 [004198]  2665  	br	p7, trap__invalid_dpte_cm		; change mode to kernel
                  [00419C]  2666  trap__invalid_dpte_cm:
         40E23407 [00419C]  2667  	addq	p7, #<dpte_cm_offset+1>, p7		; jump past in palmode
         77FF0910 [0041A0]  2668  	hw_mtpr	r31, EV6__PS				; (4,0L) switch to kern
         D3E00000 [0041A4]  2669  	bsr	r31, .					; push prediction stack
                  [0041A8]  2670  	PVC_JSR	dpte_cm					; synch up
File: ev6_pal_macros.mar
                  [0041A8]   531i  pvc_lbl \pcv_index, \pcv_jsr_dpte_cm0, osf
File: ev6_osf_pal.mar
         7BE7A000 [0041A8]  2671  	hw_ret_stall (p7)				; pop prediction stack
                  [0041AC]  2672  	PVC_JSR	dpte_cm, dest=1
File: ev6_pal_macros.mar
                  [0041AC]   534i  pvc_lbl \pcv_index, \pcv_jsr_dpte_cm0, osf, \pcv_jsr_dpte_cm0_inst
File: ev6_osf_pal.mar
                  [0041AC]  2673  ;
                  [0041AC]  2674  ; Take the trap. Be careful of tb miss!
                  [0041AC]  2675  ; Current state:
                  [0041AC]  2676  ;	p4		PTE. If user, now shifted right to kernel position
                  [0041AC]  2677  ;	p5		mm_stat
                  [0041AC]  2678  ;	p6		va
                  [0041AC]  2679  ;	p20		original ps
                  [0041AC]  2680  ;	p23		pc of instruction taking dtb miss
                  [0041AC]  2681  ;	p_misc__ps	if we were in kernel, original ps
                  [0041AC]  2682  ;			if we were in user, new ps = 0 (cm=0, ipl=0)
                  [0041AC]  2683  ;
                  [0041AC]  2684  
                  [0041AC]  2685  trap__invalid_dpte_stack:
         7EF51060 [0041AC]  2686  	hw_stq/p p23, PT__STACK_PC(p_temp)		; store away pc
                  [0041B0]  2687  
         7CD51068 [0041B0]  2688  	hw_stq/p p6, PT__NEW_A0(p_temp)			; save away va
         44A03005 [0041B4]  2689  	and	p5, #EV6__MM_STAT__WR__M, p5		; get r/w flag
         7CB51078 [0041B8]  2690  	hw_stq/p p5, PT__NEW_A2(p_temp)			; save r/w flag
                  [0041BC]  2691  
         48811684 [0041BC]  2692  	srl	p4, #OSF_PTE__KRE__S, p4		; get <re> to <0>
         47E03417 [0041C0]  2693  	bis	r31, #OSF_MMCSR__ACV, p23		; assume acv
         48809687 [0041C4]  2694  	srl	p4, #<OSF_PTE__KWE__S-OSF_PTE__KRE__S>, p7; get <we> to <0>
         44A70284 [0041C8]  2695  	cmovlbs	p5, p7, p4				; if write, check <we>
         44801297 [0041CC]  2696  	cmovlbs p4, #OSF_MMCSR__TNV, p23		; tnv if access okay
         7EF51070 [0041D0]  2697  	hw_stq/p p23, PT__NEW_A1(p_temp)		; save mmcsr
                  [0041D4]  2698  
         23DEFFD0 [0041D4]  2699  	lda	r30, <0-OSF_FRM__SIZE>(r30)		; allocate stack space
                  [0041D8]  2700  
         B69E0000 [0041D8]  2701  	stq	p20, OSF_FRM__PS(r30)			; save original ps
         B65E0028 [0041DC]  2702  	stq	r18, OSF_FRM__A2(r30)			; save a2
                  [0041E0]  2703  
         6E951060 [0041E0]  2704  	hw_ldq/p p20, PT__STACK_PC(p_temp)		; 1.39 get nextpc back
                  [0041E4]  2705  
         B7BE0010 [0041E4]  2706  	stq	r29, OSF_FRM__GP(r30)			; save gp
         B61E0018 [0041E8]  2707  	stq	r16, OSF_FRM__A0(r30)			; save a0
         B63E0020 [0041EC]  2708  	stq	r17, OSF_FRM__A1(r30)			; save a1
         B69E0008 [0041F0]  2709  	stq	p20, OSF_FRM__PC(r30)			; 1.39 save nextpc
                  [0041F4]  2710  
         6EF51048 [0041F4]  2711  	hw_ldq/p p23, PT__ENT_MM(p_temp)		; get entry point
         6FB51028 [0041F8]  2712  	hw_ldq/p r29, PT__KGP(p_temp)			; get kgp
         6E151068 [0041FC]  2713  	hw_ldq/p r16, PT__NEW_A0(p_temp)		; a0 <- va
         6E351070 [004200]  2714  	hw_ldq/p r17, PT__NEW_A1(p_temp)		; a1 <- MMCSR
         6E551078 [004204]  2715  	hw_ldq/p r18, PT__NEW_A2(p_temp)		; a2 <- cause
                  [004208]  2716  
         7BF78000 [004208]  2717  	hw_ret	(p23)					; to os
                  [00420C]  2718  
                  [00420C]  2719  ;+
                  [00420C]  2720  ; Dismiss the load to x31. We don't need a MB to hold up loads that
                  [00420C]  2721  ; may affect MM_STAT. To get here, we have taken a conditional branch
                  [00420C]  2722  ; that depended on the mfpr MM_STAT being issued.
                  [00420C]  2723  ;-
                  [00420C]  2724  trap__invalid_dpte_dismiss:
         42E09417 [00420C]  2725  	addq	p23, #4, p23			; dismiss, so increment pc
         7BF78000 [004210]  2726  	hw_ret	(p23)				; return
                  [004214]  2727  
                  [004214]  2728  ;+
                  [004214]  2729  ; DTB miss in PALmode
                  [004214]  2730  ;
                  [004214]  2731  ; There are two sources of tnv_in_pal --
                  [004214]  2732  ;	(1) urti user stack access - turn into mmfault
                  [004214]  2733  ;	(2) stack builders, rti, retsys -- take a ksp not valid halt
                  [004214]  2734  ;
                  [004214]  2735  ; In pass1, there can also be a tnv_in_pal for floating ld/st instructions.
                  [004214]  2736  ;
                  [004214]  2737  ; Current state:
                  [004214]  2738  ;	p4		PTE
                  [004214]  2739  ;	p5		mm_stat
                  [004214]  2740  ;	p6		va
                  [004214]  2741  ;	p7		exc_sum
                  [004214]  2742  ;	p23		pc of instruction taking DTB miss
                  [004214]  2743  ;
                  [004214]  2744  ;	PT__STACK_PC	in case of urti, pc+4 of call_pal invocation
                  [004214]  2745  ;			in case of rti & retsys, leave pc+4 for now
                  [004214]  2746  ;			in case of stack builders, whatever SavedPC was
                  [004214]  2747  ;			in case of istream mchk check for cmov, exc_addr 
                  [004214]  2748  ;- 
                  [004214]  2749  trap__tnv_in_pal:
         7F351118 [004214]  2750  	hw_stq/p r25, PT__R25(p_temp)	; get some scratch space
         7F551120 [004218]  2751  	hw_stq/p r26, PT__R26(p_temp)	; get some scratch space
                  [00421C]  2752  
         46E0711A [00421C]  2753  	bic	p23, #3, r26		; clean PAL pc
         673F1010 [004220]  2754  	hw_mfpr	r25, EV6__PAL_BASE	; (4,0L) get pal base
         433A053A [004224]  2755  	subq	r25, r26, r26		; pal base - cleaned pc
                  [004228]  2756  
         20FA349C [004228]  2757  	lda	p7, <call_pal__urti_ldq - trap__pal_base>(r26)
         48E07627 [00422C]  2758  	zapnot	p7, #^x3, p7		; 1.41 clean to be safe
         E4E00004 [004230]  2759  	beq	p7, trap__tnv_in_pal_urti
                  [004234]  2760  
                  [004234]  2761  					; 1.37 take out urti_stq
                  [004234]  2762  
                  [004234]  2763  					; 1.41 test for cmov check
         20FA61D4 [004234]  2764  	lda	p7, <sys__mchk_istream_check_cmov - trap__pal_base>(r26)
         48E07627 [004238]  2765  	zapnot	p7, #^x3, p7
         E4E00006 [00423C]  2766  	beq	p7, trap__tnv_in_pal_istream_mchk
                  [004240]  2767  
                  [004240]  2768  .if ne ev6_p1
                  [004240]  2769  	lda	p7, <trap__emul_ldf - trap__pal_base>(r26)
                  [004240]  2770  	beq	p7, trap__emul_ldst_tnv
                  [004240]  2771  	
                  [004240]  2772  	lda	p7, <trap__emul_ldg - trap__pal_base>(r26)
                  [004240]  2773  	beq	p7, trap__emul_ldst_tnv
                  [004240]  2774  	
                  [004240]  2775  	lda	p7, <trap__emul_lds - trap__pal_base>(r26)
                  [004240]  2776  	beq	p7, trap__emul_ldst_tnv
                  [004240]  2777  	
                  [004240]  2778  	lda	p7, <trap__emul_ldt - trap__pal_base>(r26)
                  [004240]  2779  	beq	p7, trap__emul_ldst_tnv
                  [004240]  2780  	
                  [004240]  2781  	lda	p7, <trap__emul_stf_s - trap__pal_base>(r26)
                  [004240]  2782  	beq	p7, trap__emul_ldst_tnv
                  [004240]  2783  	
                  [004240]  2784  	lda	p7, <trap__emul_stg_s - trap__pal_base>(r26)
                  [004240]  2785  	beq	p7, trap__emul_ldst_tnv
                  [004240]  2786  	
                  [004240]  2787  	lda	p7, <trap__emul_sts_s - trap__pal_base>(r26)
                  [004240]  2788  	beq	p7, trap__emul_ldst_tnv
                  [004240]  2789  	
                  [004240]  2790  	lda	p7, <trap__emul_stt_s - trap__pal_base>(r26)
                  [004240]  2791  	beq	p7, trap__emul_ldst_tnv
                  [004240]  2792  .endc
                  [004240]  2793  
         C3E00008 [004240]  2794  	br	r31, trap__ksp_invalid
                  [004244]  2795  ;+
                  [004244]  2796  ; trap__tnv_in_pal_urti
                  [004244]  2797  ;
                  [004244]  2798  ; Current state:
                  [004244]  2799  ;	p4		PTE
                  [004244]  2800  ;	p5		mm_stat
                  [004244]  2801  ;	p6		va
                  [004244]  2802  ;	p7		exc_sum
                  [004244]  2803  ;	r25		needs to be restored
                  [004244]  2804  ;	r26		needs to be restored
                  [004244]  2805  ;
                  [004244]  2806  ;	PT__STACK_PC	pc+4 of urti
                  [004244]  2807  ;-
                  [004244]  2808  trap__tnv_in_pal_urti:
         6F351118 [004244]  2809  	hw_ldq/p r25, PT__R25(p_temp)			; restore r25
         6F551120 [004248]  2810  	hw_ldq/p r26, PT__R26(p_temp)			; restore r26
                  [00424C]  2811  
         6EF51060 [00424C]  2812  	hw_ldq/p p23, PT__STACK_PC(p_temp)		; get urti pc+4
         42E09537 [004250]  2813  	subq	p23, #4, p23				; back up the pc
                  [004254]  2814  
         C3FFFFC8 [004254]  2815  	br	r31, trap__invalid_dpte_no_dismiss	; merge to post
                  [004258]  2816  ;+
                  [004258]  2817  ; trap__tnv_in_pal_istream_mchk
                  [004258]  2818  ;
                  [004258]  2819  ; Current state:
                  [004258]  2820  ;	p4		PTE
                  [004258]  2821  ;	p5		mm_stat
                  [004258]  2822  ;	p6		va
                  [004258]  2823  ;	p7		exc_sum
                  [004258]  2824  ;	r25		needs to be restored
                  [004258]  2825  ;	r26		needs to be restored
                  [004258]  2826  ;
                  [004258]  2827  ;	PT__STACK_PC	exc_addr
                  [004258]  2828  ;	PT__R1		saved mchk frame addr
                  [004258]  2829  ;-
                  [004258]  2830  trap__tnv_in_pal_istream_mchk:				; 1.41
         6F351118 [004258]  2831  	hw_ldq/p r25, PT__R25(p_temp)			; restore r25
         6F551120 [00425C]  2832  	hw_ldq/p r26, PT__R26(p_temp)			; restore r26
                  [004260]  2833  
         C3E007F6 [004260]  2834  	br	r31, sys__mchk_istream_cmov_fault	; error on cmov
                  [004264]  2835  ;+
                  [004264]  2836  ; KSP invalid
                  [004264]  2837  ;
                  [004264]  2838  ; Entry:
                  [004264]  2839  ;	Branched to on KSP not valid.
                  [004264]  2840  ;
                  [004264]  2841  ; Function:
                  [004264]  2842  ;	Restore r25 and r26.
                  [004264]  2843  ;	Recover original pc.
                  [004264]  2844  ;	Set PT__HALT_CODE to HALT__KSP_INVAL.
                  [004264]  2845  ;	Branch to update PCB and enter console.
                  [004264]  2846  ;
                  [004264]  2847  ; Current state:
                  [004264]  2848  ;	EV6__PS		kernel
                  [004264]  2849  ;
                  [004264]  2850  ;	PT__USP		updated on switch from user to kernel
                  [004264]  2851  ;	PT__STACK_PC	original SavedPC or pc+4
                  [004264]  2852  ;
                  [004264]  2853  ;	p20		original ps
                  [004264]  2854  ;	p_misc_ps	if we were in kernel, original ps
                  [004264]  2855  ;			if we were in user, ps = 0 (cm=0, ipl=0)
                  [004264]  2856  ;
                  [004264]  2857  ;	r25		needs to be restored
                  [004264]  2858  ;	r26		needs to be restored
                  [004264]  2859  ;	r30		pointing to base of stack frame		
                  [004264]  2860  ;-
                  [004264]  2861  trap__ksp_invalid:
         6F351118 [004264]  2862  	hw_ldq/p r25, PT__R25(p_temp)		; restore r25
         6F551120 [004268]  2863  	hw_ldq/p r26, PT__R26(p_temp)		; restore r26
                  [00426C]  2864  
         6EF51060 [00426C]  2865  	hw_ldq/p p23, PT__STACK_PC(p_temp)	; get back original pc
                  [004270]  2866  
         229F0002 [004270]  2867  	lda	p20, HALT__KSP_INVAL(r31)	; ksp invalid
         7E9510C8 [004274]  2868  	hw_stq/p p20, PT__HALT_CODE(p_temp)	; store code (??)
                  [004278]  2869  
         C3E00141 [004278]  2870  	br	r31, trap__update_pcb_and_halt
                  [00427C]  2871  ;+
                  [00427C]  2872  ; Do a 1-1 mapping
                  [00427C]  2873  ; Current state:
                  [00427C]  2874  ;	p6	va
                  [00427C]  2875  ;	p23	exc_addr
                  [00427C]  2876  
                  [00427C]  2877  ; We don't need a MB to hold up loads that may affect VA, etc.
                  [00427C]  2878  ; The writes to DTB_TAGx and DTB_PTE0 hold up loads.
                  [00427C]  2879  ;-
                  [00427C]  2880  trap__d1to1:
         20BF3301 [00427C]  2881  	lda	p5, ^x3301(r31)			; all r/w enable
         48C1B684 [004280]  2882  	srl	p6, #13, p4			; shift out the byte offset
         48841724 [004284]  2883  	sll	p4, #EV6__DTB_PTE0__PFN__S, p4	; get pfn into position
         44850404 [004288]  2884  	bis	p4, p5, p4			; produce the pte
                  [00428C]  2885  
                  [00428C]  2886  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
         47FF041F [00428C]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
                  [004290]  2887  
                  [004290]  2888  	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [004290]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         77E62044 [004290]  2889  	hw_mtpr	p6, EV6__DTB_TAG0		; (2&6,0L) write tag0
         77E6A022 [004294]  2890  	hw_mtpr p6, EV6__DTB_TAG1		; (1&5,1L) write tag1
         77E42155 [004298]  2891  	hw_mtpr	p4, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
         77E4A1AA [00429C]  2892  	hw_mtpr	p4, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [0042A0]  2893  
         77FF27F0 [0042A0]  2894  	hw_mtpr	r31, <EV6__MM_STAT ! ^xF0>	; (4-7,0L) stall outside IQ
                  [0042A4]  2895  
                  [0042A4]  2896      .if eq force_path				; 1.41
                  [0042A4]  2897  	hw_ret	(p23)				; do the ret
                  [0042A4]  2898      .iff
                  [0042A4]  2899  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align
                  [0042A4]  2900  	PVC_VIOLATE <1007>
                  [0042A4]  2901  	PVC_VIOLATE <1020>			; stop permutation
                  [0042A4]  2902  	hw_jmp	(p23)				; return with jmp
                  [0042A4]  2903  	br	r31, .-4			; stop predictor
                  [0042A4]  2904      .endc					; 1.41                                                
         7BF78000 [0042A4]  2897I 	hw_ret	(p23)				; do the ret
                  [0042A8]  2905      	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [0042A8]    61M         GOTO_FREE_CODE
00000000 00000000 [0042A8]    67M     .align 6
00000000 00000000 [0042B0]
00000000 00000000 [0042B8]
File: ev6_osf_pal.mar
                  [0042C0]  2906  
                  [0042C0]  2907  ;+
                  [0042C0]  2908  ; DFAULT - offset 380
                  [0042C0]  2909  ;
                  [0042C0]  2910  ; Entry:
                  [0042C0]  2911  ;	Vectored into via hardware trap on a Dstream fault or virtual
                  [0042C0]  2912  ;	address sign check error.
                  [0042C0]  2913  ;
                  [0042C0]  2914  ; Function:
                  [0042C0]  2915  ;	Prepare to take an Access Violation, FOR, or FOW.
                  [0042C0]  2916  ;
                  [0042C0]  2917  ; Note: VA and MM_STAT are not written on ld_vpte fault. Also, on
                  [0042C0]  2918  ; dfault not in pal, we can only get one of FOR or FOW (only
                  [0042C0]  2919  ; hw_ld/w can get both), so the order of checking does not matter.
                  [0042C0]  2920  ;
                  [0042C0]  2921  ; Register use:
                  [0042C0]  2922  ;	p4	scratch
                  [0042C0]  2923  ;	p5	mm_stat. For ld_vpte fault, should be unchanged from dtb miss
                  [0042C0]  2924  ;	p6	exc_addr
                  [0042C0]  2925  ;	p7	exc_sum
                  [0042C0]  2926  ;	p20	available once we determine we weren't in pal mode
                  [0042C0]  2927  ;
                  [0042C0]  2928  ; Exit state:
                  [0042C0]  2929  ;	On exit to trap__dc_tag_perr
                  [0042C0]  2930  ;	p5	mm_stat
                  [0042C0]  2931  ;	p6	pc of faulting instruction
                  [0042C0]  2932  ;	p7	exc_sum
                  [0042C0]  2933  ;
                  [0042C0]  2934  ;	On exit to dfault_in_pal
                  [0042C0]  2935  ;	p5	mm_stat
                  [0042C0]  2936  ;	p6	pc of faulting instruction
                  [0042C0]  2937  ;	p7	exc_sum
                  [0042C0]  2938  ;-
                  [0042C0]  2939  	START_HW_VECTOR <DFAULT>
File: ev6_pal_macros.mar
                  [0042C0]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000380]    49i TRAP__DFAULT:
File: ev6_osf_pal.mar
                  [000380]  2940  
         64DF0600 [000380]  2941  	hw_mfpr	p6, EV6__EXC_ADDR		; (0L) save exception address
         64FF0F00 [000384]  2942  	hw_mfpr p7, EV6__EXC_SUM		; (0L) get exc_sum
         64BF2700 [000388]  2943  	hw_mfpr	p5, EV6__MM_STAT		; (0L) get mm_stat
                  [00038C]  2944  
         48A15684 [00038C]  2945  	srl	p5, #EV6__MM_STAT__DC_TAG_PERR__S, p4
         F0801017 [000390]  2946  	blbs	p4, trap__dc_tag_perr		; dc_tag_perr => another flow
         F0C00FF9 [000394]  2947  	blbs	p6, trap__dfault_in_pal		; pal mode => another flow
                  [000398]  2948  
                  [000398]  2949  	CONT_HW_VECTOR <DFAULT>
File: ev6_pal_macros.mar
                  [000398]    76M     ASSUME <_pal_vec_cont> eq 0
         C3E00FC9 [000398]    81i 	br	r31, TRAP__DFAULT_CONT
                  [00039C]    84M                 ASSUME <.-_start_of_last_vec> le <^x80>
                  [00039C]    86M     GOTO_FREE_CODE
                  [0042C0]    67M     .align 6
                  [0042C0]    91i TRAP__DFAULT_CONT:
File: ev6_osf_pal.mar
                  [0042C0]  2950  
         E0A00005 [0042C0]  2951  	blbc	p5, trap__dfault_check		; load => check x31
                  [0042C4]  2952  
         48A09687 [0042C4]  2953  	srl	p5, #EV6__MM_STAT__OPCODE__S, p7	; get opcode
         44E7F007 [0042C8]  2954  	and	p7, #EV6__MM_STAT__OPCODE__M, p7	; clean it
         40E315A7 [0042CC]  2955  	cmpeq	p7, #^x18, p7				; ECB/WH64?
         F4E00028 [0042D0]  2956  	bne	p7, trap__dfault_dismiss		; dismiss if so
                  [0042D4]  2957  
         C3E00004 [0042D4]  2958  	br	r31, trap__dfault_no_dismiss	; store => no dismiss
                  [0042D8]  2959  
                  [0042D8]  2960  trap__dfault_check:
         48E11687 [0042D8]  2961  	srl	p7, #EV6__EXC_SUM__REG__S, p7	; get ra
         44E3F007 [0042DC]  2962  	and	p7, #EV6__EXC_SUM__REG__M, p7	; clean ra
         40E3F5A7 [0042E0]  2963  	cmpeq	p7, #^x1F, p7			; compare against x31
         F4E00023 [0042E4]  2964  	bne	p7, trap__dfault_dismiss	; branch => x31
                  [0042E8]  2965  ;
                  [0042E8]  2966  ; Take the trap.
                  [0042E8]  2967  ; Current state.
                  [0042E8]  2968  ;	p5	mm_stat
                  [0042E8]  2969  ;	p6	exc_addr
                  [0042E8]  2970  ;
                  [0042E8]  2971  trap__dfault_no_dismiss:
                  [0042E8]  2972  
         66FFC2F0 [0042E8]  2973  	hw_mfpr	p23, EV6__VA				; (4-7,1L) get va
                  [0042EC]  2974  
         63FF4000 [0042EC]  2975  	mb						; protect mm_stat and va
                  [0042F0]  2976  
         46C11004 [0042F0]  2977  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p4	; current mode
         46C1F014 [0042F4]  2978  	and	p_misc, #OSF_P_MISC__PS__M, p20		; save original ps
         E4800008 [0042F8]  2979  	beq	p4, trap__dfault_stack			; skip switch if kernel
                  [0042FC]  2980  ;
                  [0042FC]  2981  ; Switch to kernel mode.
                  [0042FC]  2982  ; Current state:
                  [0042FC]  2983  ;	p5		mm_stat
                  [0042FC]  2984  ;	p6		exc_addr
                  [0042FC]  2985  ;	p20		original ps
                  [0042FC]  2986  ;	p23		va
                  [0042FC]  2987  ;
                  [0042FC]  2988  dfault_cm_offset = <trap__dfault_stack - trap__dfault_cm>
                  [0042FC]  2989  
         7FD51020 [0042FC]  2990  	hw_stq/p r30, PT__USP(p_temp)				; save user SP
         6FD51018 [004300]  2991  	hw_ldq/p r30, PT__KSP(p_temp)				; get kernel SP
         46C1F116 [004304]  2992  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc		; cm=0, ipl=0
                  [004308]  2993  
         C0800000 [004308]  2994  	br	p4, trap__dfault_cm			; change mode to kernel
                  [00430C]  2995  trap__dfault_cm:
         40823404 [00430C]  2996  	addq	p4, #<dfault_cm_offset+1>, p4		; jump past in palmode
         77FF0910 [004310]  2997  	hw_mtpr	r31, EV6__PS				; (4,0L) switch to kern
         D3E00000 [004314]  2998  	bsr	r31, .					; push prediction stack
                  [004318]  2999  	PVC_JSR	dfault_cm				; synch up
File: ev6_pal_macros.mar
                  [004318]   531i  pvc_lbl \pcv_index, \pcv_jsr_dfault_cm0, osf
File: ev6_osf_pal.mar
         7BE4A000 [004318]  3000  	hw_ret_stall (p4)				; pop prediction stack
                  [00431C]  3001  	PVC_JSR	dfault_cm, dest=1
File: ev6_pal_macros.mar
                  [00431C]   534i  pvc_lbl \pcv_index, \pcv_jsr_dfault_cm0, osf, \pcv_jsr_dfault_cm0_inst
File: ev6_osf_pal.mar
                  [00431C]  3002  ;
                  [00431C]  3003  ; Take the trap. Be careful of tb miss!
                  [00431C]  3004  ; Current state:
                  [00431C]  3005  ;	p5		mm_stat
                  [00431C]  3006  ;	p6		exc_addr
                  [00431C]  3007  ;	p20		original ps
                  [00431C]  3008  ;	p23		va
                  [00431C]  3009  ;	p_misc__ps	if we were in kernel, original ps
                  [00431C]  3010  ;			if we were in user, new ps = 0 (cm=0, ipl=0)
                  [00431C]  3011  ;
                  [00431C]  3012  trap__dfault_stack:
         7CD51060 [00431C]  3013  	hw_stq/p p6, PT__STACK_PC(p_temp)		; store away pc
         7EF51068 [004320]  3014  	hw_stq/p p23, PT__NEW_A0(p_temp)		; store away va
         48A03687 [004324]  3015  	srl	p5, #1, p7				; shift mm_stat bits
         44E0F007 [004328]  3016  	and	p7, #^x7, p7				; clean to fow/for/acv
         44E03287 [00432C]  3017  	cmovlbs	p7, #1, p7				; take acv over fox
         7CF51070 [004330]  3018  	hw_stq/p p7, PT__NEW_A1(p_temp)			; MMCSR
         44A03004 [004334]  3019  	and	p5, #1, p4				; get r/w bit
         7C951078 [004338]  3020  	hw_stq/p p4, PT__NEW_A2(p_temp)			; store away r/w bit
                  [00433C]  3021  
         23DEFFD0 [00433C]  3022  	lda	r30, <0-OSF_FRM__SIZE>(r30)		; allocate stack space
                  [004340]  3023  
         B69E0000 [004340]  3024  	stq	p20, OSF_FRM__PS(r30)			; save original ps
         B65E0028 [004344]  3025  	stq	r18, OSF_FRM__A2(r30)			; save a2
                  [004348]  3026  
         6E951060 [004348]  3027  	hw_ldq/p p20, PT__STACK_PC(p_temp)		; 1.39 get nextpc back
                  [00434C]  3028  
         B7BE0010 [00434C]  3029  	stq	r29, OSF_FRM__GP(r30)			; save gp
         B61E0018 [004350]  3030  	stq	r16, OSF_FRM__A0(r30)			; save a0
         B63E0020 [004354]  3031  	stq	r17, OSF_FRM__A1(r30)			; save a1
         B69E0008 [004358]  3032  	stq	p20, OSF_FRM__PC(r30)			; 1.39 save pc
                  [00435C]  3033  
         6EF51048 [00435C]  3034  	hw_ldq/p p23, PT__ENT_MM(p_temp)		; get entry point
         6FB51028 [004360]  3035  	hw_ldq/p r29, PT__KGP(p_temp)			; get kgp
         6E151068 [004364]  3036  	hw_ldq/p r16, PT__NEW_A0(p_temp)		; a0 <- va
         6E351070 [004368]  3037  	hw_ldq/p r17, PT__NEW_A1(p_temp)		; a1 <- opcode
         6E551078 [00436C]  3038  	hw_ldq/p r18, PT__NEW_A2(p_temp)		; a2 <- register number
                  [004370]  3039  
         7BF78000 [004370]  3040  	hw_ret	(p23)					; to os
                  [004374]  3041  
                  [004374]  3042  ;+
                  [004374]  3043  ; Dismiss load x31
                  [004374]  3044  ;
                  [004374]  3045  ; We don't need a MB to hold up loads that may affect MM_STAT.
                  [004374]  3046  ; To get here, we have taken conditional branches that on the
                  [004374]  3047  ; mfpr MM_STAT being issued.
                  [004374]  3048  
                  [004374]  3049  ;-
                  [004374]  3050  trap__dfault_dismiss:
         40C09406 [004374]  3051  	addq	p6, #4, p6			; dismiss
         7BE68000 [004378]  3052  	hw_ret	(p6)
                  [00437C]  3053  ;+
                  [00437C]  3054  ; trap__dfault_in_pal
                  [00437C]  3055  ;
                  [00437C]  3056  ; Entry:
                  [00437C]  3057  ; 	Dstream fault trap has been taken, exc_addr points to pal code.
                  [00437C]  3058  ;
                  [00437C]  3059  ; Current state:
                  [00437C]  3060  ;	p5 		mm_stat
                  [00437C]  3061  ;	p6		pc of instruction causing Dstream fault. Can be from
                  [00437C]  3062  ;				call_pal PALcode
                  [00437C]  3063  ;				kernel stack processing (KSP not valid case)
                  [00437C]  3064  ;	p7		available
                  [00437C]  3065  ;	p23		if vpte dfault => exc_addr of instruction causing miss
                  [00437C]  3066  ;
                  [00437C]  3067  ;	PT__STACK_PC	in case of urti, pc+4 of call_pal invocation
                  [00437C]  3068  ;			in case of rti & retsys, leave pc+4 for now
                  [00437C]  3069  ;			in case of stack builders, whatever SavedPC was
                  [00437C]  3070  ;
                  [00437C]  3071  ;	CNS__FP_PC	for pass1, user pc of floating point ld/st
                  [00437C]  3072  ;
                  [00437C]  3073  ;	VA		faulting VA
                  [00437C]  3074  ;
                  [00437C]  3075  
                  [00437C]  3076  ; Exit state:
                  [00437C]  3077  ;-
                  [00437C]  3078  trap__dfault_in_pal:
         7F351118 [00437C]  3079  	hw_stq/p r25, PT__R25(p_temp)	; get some scratch space
         7F551120 [004380]  3080  	hw_stq/p r26, PT__R26(p_temp)	; get some scratch space
                  [004384]  3081  
         44C0711A [004384]  3082  	bic	p6, #3, r26		; clean PAL pc
         673F1010 [004388]  3083  	hw_mfpr	r25, EV6__PAL_BASE	; (4,0L) get pal base
         433A053A [00438C]  3084  	subq	r25, r26, r26		; pal base - cleaned pc
                  [004390]  3085  
                  [004390]  3086  	.if ne pte_eco			; 1.49 conditionalize further
                  [004390]  3087  	.if ne force_path2		; 1.44 test for ldbu in dtb miss
                  [004390]  3088  
                  [004390]  3089  	lda	p7, <trap__dtbm_single_hack1 - trap__pal_base>(r26)
                  [004390]  3090  	zapnot	p7, #^x3, p7
                  [004390]  3091  	beq	p7, trap__stc_hack
                  [004390]  3092  
                  [004390]  3093  	lda	p7, <trap__dtbm_single_hack2 - trap__pal_base>(r26)
                  [004390]  3094  	zapnot	p7, #^x3, p7
                  [004390]  3095  	beq	p7, trap__stc_hack
                  [004390]  3096  
                  [004390]  3097  	lda	p7, <trap__dtbm_single_hack3 - trap__pal_base>(r26)
                  [004390]  3098  	zapnot	p7, #^x3, p7
                  [004390]  3099  	beq	p7, trap__stc_hack
                  [004390]  3100  
                  [004390]  3101  	.endc				; 1.44 force_path2
                  [004390]  3102  	.endc				; 1.49 pte_eco
                  [004390]  3087I 	.if ne force_path2		; 1.44 test for ldbu in dtb miss
                  [004390]  3088I 
                  [004390]  3089I 	lda	p7, <trap__dtbm_single_hack1 - trap__pal_base>(r26)
                  [004390]  3090I 	zapnot	p7, #^x3, p7
                  [004390]  3091I 	beq	p7, trap__stc_hack
                  [004390]  3092I 
                  [004390]  3093I 	lda	p7, <trap__dtbm_single_hack2 - trap__pal_base>(r26)
                  [004390]  3094I 	zapnot	p7, #^x3, p7
                  [004390]  3095I 	beq	p7, trap__stc_hack
                  [004390]  3096I 
                  [004390]  3097I 	lda	p7, <trap__dtbm_single_hack3 - trap__pal_base>(r26)
                  [004390]  3098I 	zapnot	p7, #^x3, p7
                  [004390]  3099I 	beq	p7, trap__stc_hack
                  [004390]  3100I 
                  [004390]  3101I 	.endc				; 1.44 force_path2
                  [004390]  3103  	
         20FA0590 [004390]  3104  	lda	p7, <trap__itb_miss_vpte - trap__pal_base>(r26)
         E4E00011 [004394]  3105  	beq	p7, trap__ldvpte_dfault
                  [004398]  3106  
         20FA0320 [004398]  3107  	lda	p7, <trap__dtbm_single_vpte - trap__pal_base>(r26)
         E4E0000F [00439C]  3108  	beq	p7, trap__ldvpte_dfault
                  [0043A0]  3109  
         20FA349C [0043A0]  3110  	lda	p7, <call_pal__urti_ldq - trap__pal_base>(r26)
         48E07627 [0043A4]  3111  	zapnot	p7, #^x3, p7		; 1.41 clean to be safe
         E4E00004 [0043A8]  3112  	beq	p7, trap__dfault_in_pal_urti
                  [0043AC]  3113  
                  [0043AC]  3114  					; 1.37 take out urti_stq
                  [0043AC]  3115  
                  [0043AC]  3116  					; 1.41 test for cmov check
         20FA61D4 [0043AC]  3117  	lda	p7, <sys__mchk_istream_check_cmov - trap__pal_base>(r26)
         48E07627 [0043B0]  3118  	zapnot	p7, #^x3, p7
         E4E00006 [0043B4]  3119  	beq	p7, trap__dfault_in_pal_istream_mchk
                  [0043B8]  3120  
                  [0043B8]  3121  .if ne ev6_p1
                  [0043B8]  3122  	lda	p7, <trap__emul_ldf - trap__pal_base>(r26)
                  [0043B8]  3123  	beq	p7, trap__emul_ldst_dfault
                  [0043B8]  3124  	
                  [0043B8]  3125  	lda	p7, <trap__emul_ldg - trap__pal_base>(r26)
                  [0043B8]  3126  	beq	p7, trap__emul_ldst_dfault
                  [0043B8]  3127  	
                  [0043B8]  3128  	lda	p7, <trap__emul_lds - trap__pal_base>(r26)
                  [0043B8]  3129  	beq	p7, trap__emul_ldst_dfault
                  [0043B8]  3130  	
                  [0043B8]  3131  	lda	p7, <trap__emul_ldt - trap__pal_base>(r26)
                  [0043B8]  3132  	beq	p7, trap__emul_ldst_dfault
                  [0043B8]  3133  	
                  [0043B8]  3134  	lda	p7, <trap__emul_stf_s - trap__pal_base>(r26)
                  [0043B8]  3135  	beq	p7, trap__emul_ldst_dfault
                  [0043B8]  3136  	
                  [0043B8]  3137  	lda	p7, <trap__emul_stg_s - trap__pal_base>(r26)
                  [0043B8]  3138  	beq	p7, trap__emul_ldst_dfault
                  [0043B8]  3139  	
                  [0043B8]  3140  	lda	p7, <trap__emul_sts_s - trap__pal_base>(r26)
                  [0043B8]  3141  	beq	p7, trap__emul_ldst_dfault
                  [0043B8]  3142  	
                  [0043B8]  3143  	lda	p7, <trap__emul_stt_s - trap__pal_base>(r26)
                  [0043B8]  3144  	beq	p7, trap__emul_ldst_dfault
                  [0043B8]  3145  .endc
                  [0043B8]  3146  
         C3FFFFAA [0043B8]  3147  	br	r31, trap__ksp_invalid		; must be ksp invalid
                  [0043BC]  3148  
                  [0043BC]  3149  .if ne force_path2				; 1.44
                  [0043BC]  3150  ;+
                  [0043BC]  3151  ; trap__stc_hack
                  [0043BC]  3152  ;
                  [0043BC]  3153  ; Current state:
                  [0043BC]  3154  ;	p6		pal pc
                  [0043BC]  3155  ;	p23		original pc
                  [0043BC]  3156  ;	r25		needs to be restored
                  [0043BC]  3157  ;	r26		needs to be restored
                  [0043BC]  3158  ;
                  [0043BC]  3159  ; The real stx_c will fault as well. Recover back to
                  [0043BC]  3160  ; dtbm miss flow after the load.
                  [0043BC]  3161  ;-
                  [0043BC]  3162  trap__stc_hack:
                  [0043BC]  3163  	hw_ldq/p r25, PT__R25(p_temp)		; restore r25
                  [0043BC]  3164  	hw_ldq/p r26, PT__R26(p_temp)		; restore r26
                  [0043BC]  3165  
                  [0043BC]  3166  	addq	p6, #4, p6			; return past load
                  [0043BC]  3167  	hw_ret	(p6)				; return
                  [0043BC]  3168  .endc						; 1.44
                  [0043BC]  3169  ;+
                  [0043BC]  3170  ; trap__dfault_in_pal_urti
                  [0043BC]  3171  ;
                  [0043BC]  3172  ; Current state:
                  [0043BC]  3173  ;	p5 		mm_stat
                  [0043BC]  3174  ;	r25		needs to be restored
                  [0043BC]  3175  ;	r26		needs to be restored
                  [0043BC]  3176  ;
                  [0043BC]  3177  ;	VA		faulting VA
                  [0043BC]  3178  ;
                  [0043BC]  3179  ;	PT__STACK_PC	pc+4 of urti
                  [0043BC]  3180  ;
                  [0043BC]  3181  ; Exit to trap__dfault_merge_from_urti:
                  [0043BC]  3182  ;	p5		mm_stat
                  [0043BC]  3183  ;	p6		exc_addr
                  [0043BC]  3184  ;-
                  [0043BC]  3185  trap__dfault_in_pal_urti:
         6F351118 [0043BC]  3186  	hw_ldq/p r25, PT__R25(p_temp)			; restore r25
         6F551120 [0043C0]  3187  	hw_ldq/p r26, PT__R26(p_temp)			; restore r26
                  [0043C4]  3188  
         6CD51060 [0043C4]  3189  	hw_ldq/p p6, PT__STACK_PC(p_temp)		; get urti pc+4
         40C09526 [0043C8]  3190  	subq	p6, #4, p6				; back up the pc
         C3FFFFC6 [0043CC]  3191  	br	r31, trap__dfault_no_dismiss		; merge to post
                  [0043D0]  3192  ;+
                  [0043D0]  3193  ; trap__dfault_in_pal_istream_mchk
                  [0043D0]  3194  ;
                  [0043D0]  3195  ; Current state:
                  [0043D0]  3196  ;	p5 		mm_stat
                  [0043D0]  3197  ;	r25		needs to be restored
                  [0043D0]  3198  ;	r26		needs to be restored
                  [0043D0]  3199  ;
                  [0043D0]  3200  ;	VA		faulting VA
                  [0043D0]  3201  ;
                  [0043D0]  3202  ;	PT__STACK_PC	exc_addr
                  [0043D0]  3203  ;	PT__R1		save mchk frame addr
                  [0043D0]  3204  ;-
                  [0043D0]  3205  trap__dfault_in_pal_istream_mchk:				; 1.41
         6F351118 [0043D0]  3206  	hw_ldq/p r25, PT__R25(p_temp)			; restore r25
         6F551120 [0043D4]  3207  	hw_ldq/p r26, PT__R26(p_temp)			; restore r26
                  [0043D8]  3208  
         C3E00798 [0043D8]  3209  	br	r31, sys__mchk_istream_cmov_fault	; error on cmov
                  [0043DC]  3210  ;+
                  [0043DC]  3211  ; trap__ldvpte_dfault
                  [0043DC]  3212  ;
                  [0043DC]  3213  ; Entry:
                  [0043DC]  3214  ;	Branched to from dfault of ld_vpte during tb miss processing.
                  [0043DC]  3215  ;	For itb miss, the originator is user code. For dtb miss, the
                  [0043DC]  3216  ;	originator can be user code, PALcode (including stack processing).
                  [0043DC]  3217  ;
                  [0043DC]  3218  ;	This is a halt condition. This means that we had a valid level 2
                  [0043DC]  3219  ;	PTE with KRE/KWE=0 in the TB, pulled in by the double miss
                  [0043DC]  3220  ;	flow. The SRM states that protection is ignored on level 1
                  [0043DC]  3221  ;	and level 2 valid PTE's, implying that valid level 1 and
                  [0043DC]  3222  ;	level 2 PTE's must have KRE/WRE set so that TB accesses work.
                  [0043DC]  3223  ;
                  [0043DC]  3224  ; Function:
                  [0043DC]  3225  ;	Restore r25 and r26.
                  [0043DC]  3226  ;	Set PT__HALT_CODE to HALT__PTBR_INVAL.
                  [0043DC]  3227  ;	Recover original pc.
                  [0043DC]  3228  ;	Branch to update PCB and enter console.
                  [0043DC]  3229  ;
                  [0043DC]  3230  ; Current state:
                  [0043DC]  3231  ;	r25		needs to be restored
                  [0043DC]  3232  ;	r26		needs to be restored
                  [0043DC]  3233  ;
                  [0043DC]  3234  ;	p23		1.44 pc of instruction causing tb miss
                  [0043DC]  3235  ;-
                  [0043DC]  3236  trap__ldvpte_dfault:
         6F351118 [0043DC]  3237  	hw_ldq/p r25, PT__R25(p_temp)			; restore r25
         6F551120 [0043E0]  3238  	hw_ldq/p r26, PT__R26(p_temp)			; restore r26
                  [0043E4]  3239  
         229F0004 [0043E4]  3240  	lda	p20, HALT__PTBR_INVAL(r31)		; ptbr invalid
         7E9510C8 [0043E8]  3241  	hw_stq/p p20, PT__HALT_CODE(p_temp)		; store code (??)
                  [0043EC]  3242  
                  [0043EC]  3243  	; 1.44 delete PT_VPTE_PC load into p23. p23 still valid.
         C3E000E4 [0043EC]  3244  	br	r31, trap__update_pcb_and_halt
                  [0043F0]  3245  
                  [0043F0]  3246  ;+
                  [0043F0]  3247  ; dc_tag_perr
                  [0043F0]  3248  ;
                  [0043F0]  3249  ; Dcache tag parity error occured during the initial tag probe of a load
                  [0043F0]  3250  ; or store instruction. This error created a synchronous fault to the dfault
                  [0043F0]  3251  ; PALcode entry point, and is correctable. The virtual address associated
                  [0043F0]  3252  ; with the error is available in the VA register.
                  [0043F0]  3253  ;
                  [0043F0]  3254  ; We evict using 2 hw_ld's with pa's that with the same index, and
                  [0043F0]  3255  ; different tags from each other.
                  [0043F0]  3256  ;
                  [0043F0]  3257  ; WARNING!!!!! This code really only works if both sets were originally
                  [0043F0]  3258  ; enabled. Otherwise we could load into the normally disabled cache, and
                  [0043F0]  3259  ; could hit there even when it is re-disabled. So if we have systems that
                  [0043F0]  3260  ; we allow to run with one cache, we have to be careful to chose pa's that
                  [0043F0]  3261  ; the PALcode would normally never touch.
                  [0043F0]  3262  ;
                  [0043F0]  3263  ; If we are in PALmode, we do an error halt. Shadow registers have already
                  [0043F0]  3264  ; been clobbered.
                  [0043F0]  3265  ;
                  [0043F0]  3266  ; Current state:
                  [0043F0]  3267  ;	p5		mm_stat
                  [0043F0]  3268  ;	p6		exc_addr
                  [0043F0]  3269  ;	p7		exc_sum
                  [0043F0]  3270  ;-
                  [0043F0]  3271  NO_DCTAG_PAR_EN = -
                  [0043F0]  3272  		<<dcache_set_en@EV6__DC_CTL__SET_EN__S> ! -
                  [0043F0]  3273  		 <0@EV6__DC_CTL__DCTAG_PAR_EN__S> ! -
                  [0043F0]  3274  		 <0@EV6__DC_CTL__DCDAT_ERR_EN__S>>
                  [0043F0]  3275  
                  [0043F0]  3276  	ALIGN_FETCH_BLOCK
File: ev6_pal_macros.mar
                  [0043F0]   267i 	.align 4
File: ev6_osf_pal.mar
                  [0043F0]  3277  
                  [0043F0]  3278  trap__dc_tag_perr:
         649FC2F0 [0043F0]  3279  	hw_mfpr	p4, EV6__VA			; (4-7,1L) get va
         44C60417 [0043F4]  3280  	bis	p6, p6, p23			; move exc_addr to p23
         47E07414 [0043F8]  3281  	bis	r31, #NO_DCTAG_PAR_EN, p20	; disable dctag_par_en
         77F42940 [0043FC]  3282  	hw_mtpr	p20, EV6__DC_CTL		; (6,0L)
                  [004400]  3283  
         77F42940 [004400]  3284  	hw_mtpr	p20, EV6__DC_CTL		; (6,0L) force retire
         489F1604 [004404]  3285  	zap	p4, #^xF8, p4			; use va<23:0> as a pa
                  [004408]  3286  
         63FF4000 [004408]  3287  	mb
                  [00440C]  3288  
         24DF0001 [00440C]  3289  	ldah	p6, 1(r31)			; use <16> as a toggle bit
         44860806 [004410]  3290  	xor	p4, p6, p6			; xor to get toggle
         6CE61000 [004414]  3291  	hw_ldq/p p7, (p6)			; force evict from one set
                  [004418]  3292  
         24DF0002 [004418]  3293  	ldah	p6, 2(r31)			; use <17> as a toggle bit
         44860806 [00441C]  3294  	xor	p4, p6, p6			; xor to get toggle
         6CE61000 [004420]  3295  	hw_ldq/p p7, (p6)			; force evict from other
                  [004424]  3296  
         63FF4000 [004424]  3297  	mb					; force completion
                  [004428]  3298  
                  [004428]  3299  	ALIGN_FETCH_BLOCK <^x47FF041F>
File: ev6_pal_macros.mar
47FF041F 47FF041F [004428]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
                  [004430]  3300  
         6E951088 [004430]  3301  	hw_ldq/p p20, PT__IMPURE(p_temp)	; impure base
         6E941398 [004434]  3302  	hw_ldq/p p20, CNS__DC_CTL(p20)		; get old DC_CTL value
         77F42940 [004438]  3303  	hw_mtpr	p20, EV6__DC_CTL		; (6,0L) restore DC_CTL
         47FF041F [00443C]  3304  	bis	r31, r31, r31
                  [004440]  3305  
         77F42940 [004440]  3306  	hw_mtpr	p20, EV6__DC_CTL		; (6,0L) force retire
         C3E006BE [004444]  3307  	br	r31, sys__mchk_dc_tag_perr	; post retryable mchk
                  [004448]  3308  
                  [004448]  3309  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [004448]    61M         GOTO_FREE_CODE
00000000 00000000 [004448]    67M     .align 6
00000000 00000000 [004450]
00000000 00000000 [004458]
00000000 00000000 [004460]
00000000 00000000 [004468]
00000000 00000000 [004470]
00000000 00000000 [004478]
File: ev6_osf_pal.mar
                  [004480]  3310  
                  [004480]  3311  ;+
                  [004480]  3312  ; OPCDEC - offset 400
                  [004480]  3313  ;
                  [004480]  3314  ; Entry:
                  [004480]  3315  ;	Vectored into via hardware trap on illegal opcode or function field
                  [004480]  3316  ;	fault.
                  [004480]  3317  ; Function:
                  [004480]  3318  ;	Build stack frame.
                  [004480]  3319  ;		r16 (a0)	opDec code
                  [004480]  3320  ;		r17 (a1)	unpredictable
                  [004480]  3321  ;		r18 (a2)	unpredictable
                  [004480]  3322  ;	Vector via entIF.
                  [004480]  3323  ;-
                  [004480]  3324  
                  [004480]  3325  	START_HW_VECTOR <OPCDEC>
File: ev6_pal_macros.mar
                  [004480]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000400]    49i TRAP__OPCDEC:
File: ev6_osf_pal.mar
                  [000400]  3326  
                  [000400]  3327  ASSUME OSF_P_MISC__PS__S eq 0
                  [000400]  3328  
         66FF0600 [000400]  3329  	hw_mfpr	p23, EV6__EXC_ADDR			; (0L) save exc_addr
                  [000404]  3330  	NOP						; no conditional br
File: ev6_pal_macros.mar
         47FF041F [000404]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [000408]  3331  	NOP						;	in 1st block
File: ev6_pal_macros.mar
         47FF041F [000408]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [00040C]  3332  	NOP
File: ev6_pal_macros.mar
         47FF041F [00040C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [000410]  3333  
                  [000410]  3334  .if ne ev6_p1
                  [000410]  3335  	hw_ldq/p p4, PT__IMPURE(p_temp)		; get base of impure area
                  [000410]  3336  	br	r31, trap__emul_merge		; let floating emulator handle
                  [000410]  3337  trap__opcdec_merge:
                  [000410]  3338  .endc
                  [000410]  3339  
         F2E00046 [000410]  3340  	blbs	p23, trap__pal_exc_bugcheck		; mchk if fen within pal
         42E09417 [000414]  3341  	addq	p23, #4, p23				; next pc
                  [000418]  3342  
                  [000418]  3343  trap__opcdec_call_pal:
         46C11004 [000418]  3344  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p4	; current mode
         46C1F014 [00041C]  3345  	and	p_misc, #OSF_P_MISC__PS__M, p20		; save original ps
         E4800008 [000420]  3346  	beq	p4, trap__opcdec_stack			; skip switch if kernel
                  [000424]  3347  ;
                  [000424]  3348  ; Switch to kernel mode. 
                  [000424]  3349  ;
                  [000424]  3350  opcdec_cm_offset = <trap__opcdec_stack - trap__opcdec_cm>
                  [000424]  3351  
         7FD51020 [000424]  3352  	hw_stq/p r30, PT__USP(p_temp)			; save user SP
         6FD51018 [000428]  3353  	hw_ldq/p r30, PT__KSP(p_temp)			; get kernel SP
         46C1F116 [00042C]  3354  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc	; cm=0, ipl=0
                  [000430]  3355  
         C0C00000 [000430]  3356  	br	p6, trap__opcdec_cm			; change mode to kernel
                  [000434]  3357  trap__opcdec_cm:
         40C23406 [000434]  3358  	addq	p6, #<opcdec_cm_offset+1>, p6		; jump past in palmode
         77FF0910 [000438]  3359  	hw_mtpr	r31, EV6__PS				; (4,0L) switch to kern
         D3E00000 [00043C]  3360  	bsr	r31, .					; push prediction stack
                  [000440]  3361  	PVC_JSR	opcdec_cm				; synch up
File: ev6_pal_macros.mar
                  [000440]   531i  pvc_lbl \pcv_index, \pcv_jsr_opcdec_cm0, osf
File: ev6_osf_pal.mar
         7BE6A000 [000440]  3362  	hw_ret_stall (p6)				; pop prediction stack
                  [000444]  3363  	PVC_JSR	opcdec_cm, dest=1
File: ev6_pal_macros.mar
                  [000444]   534i  pvc_lbl \pcv_index, \pcv_jsr_opcdec_cm0, osf, \pcv_jsr_opcdec_cm0_inst
File: ev6_osf_pal.mar
                  [000444]  3364  ;
                  [000444]  3365  ; Take the trap. Be careful of tb miss!
                  [000444]  3366  ; Current state:
                  [000444]  3367  ;	p_misc__ps	if we were in kernel, original ps
                  [000444]  3368  ;			if we were in user, new ps = 0 (cm=0, ipl=0)
                  [000444]  3369  ;	p20		original ps
                  [000444]  3370  ;	p23		nextpc
                  [000444]  3371  ;
                  [000444]  3372  trap__opcdec_stack:
         7EF51060 [000444]  3373  	hw_stq/p p23, PT__STACK_PC(p_temp)		; store away nextpc
                  [000448]  3374  
         23DEFFD0 [000448]  3375  	lda	r30, <0-OSF_FRM__SIZE>(r30)		; allocate stack space
                  [00044C]  3376  
         B69E0000 [00044C]  3377  	stq	p20, OSF_FRM__PS(r30)			; save original ps
         B65E0028 [000450]  3378  	stq	r18, OSF_FRM__A2(r30)			; save a2
                  [000454]  3379  
         6E951060 [000454]  3380  	hw_ldq/p p20, PT__STACK_PC(p_temp)		; 1.39 get pc back
                  [000458]  3381  
         B7BE0010 [000458]  3382  	stq	r29, OSF_FRM__GP(r30)			; save gp
         B61E0018 [00045C]  3383  	stq	r16, OSF_FRM__A0(r30)			; save a0
         B63E0020 [000460]  3384  	stq	r17, OSF_FRM__A1(r30)			; save a1
         B69E0008 [000464]  3385  	stq	p20, OSF_FRM__PC(r30)			; 1.39 save next pc
                  [000468]  3386  
         6EF51038 [000468]  3387  	hw_ldq/p p23, PT__ENT_IF(p_temp)		; get entry point
         6FB51028 [00046C]  3388  	hw_ldq/p r29, PT__KGP(p_temp)			; get kgp
         47E09410 [000470]  3389  	bis	r31, #OSF_A0__OPDEC, r16		; set a0 
                  [000474]  3390  
         7BF78000 [000474]  3391  	hw_ret	(p23)					; to os
                  [000478]  3392  
                  [000478]  3393  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [000478]    57i         ASSUME <.-_start_of_last_vec> le <^x80>
                  [000478]    61M         GOTO_FREE_CODE
                  [004480]    67M     .align 6
File: ev6_osf_pal.mar
                  [004480]  3394  
                  [004480]  3395  ;+
                  [004480]  3396  ; IACV - offset 480
                  [004480]  3397  ;
                  [004480]  3398  ; Entry:
                  [004480]  3399  ;	Vectored into via hardware trap on a Istream access violation or
                  [004480]  3400  ;	virtual address sign check/overflow/underflow error.
                  [004480]  3401  ;
                  [004480]  3402  ; Function:
                  [004480]  3403  ;	For native mode, take an exception with the exception pc as follows:
                  [004480]  3404  ;	IF (bad_iva, i.e, jsr)
                  [004480]  3405  ;	THEN exception pc = va<63:0>
                  [004480]  3406  ;	ELSE	IF (pc_ovfl & va_48)
                  [004480]  3407  ;		THEN	IF (exc_addr<47>)
                  [004480]  3408  ;			THEN exception pc = exc_addr<47:0> with <63:48>=0
                  [004480]  3409  ;			ELSE exception pc = exc_addr<47:0> with <63;48>=1
                  [004480]  3410  ;		ELSE	exception pc = exc_addr<63:0>
                  [004480]  3411  ;
                  [004480]  3412  ;	For PALmode, enter console with exception pc as follows:
                  [004480]  3413  ;	Has to be bad_iva, i.e. jsr with exception pc= va<63:1>!1
                  [004480]  3414  ;
                  [004480]  3415  ; Register use:
                  [004480]  3416  ;	p4	temporary
                  [004480]  3417  ;	p5	temporary
                  [004480]  3418  ;	p6	exc_addr
                  [004480]  3419  ;	p7	exc_sum
                  [004480]  3420  ;-
                  [004480]  3421  	START_HW_VECTOR <IACV>
File: ev6_pal_macros.mar
                  [004480]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000480]    49i TRAP__IACV:
File: ev6_osf_pal.mar
                  [000480]  3422  
         64DF0600 [000480]  3423  	hw_mfpr	p6, EV6__EXC_ADDR		; (0L) save exception address
         64FF0F00 [000484]  3424  	hw_mfpr	p7, EV6__EXC_SUM		; (0L) check bad_iva and pc_ovfl
                  [000488]  3425  	NOP					; no conditional br
File: ev6_pal_macros.mar
         47FF041F [000488]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [00048C]  3426  	NOP					;	in 1st block
File: ev6_pal_macros.mar
         47FF041F [00048C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [000490]  3427  
         F0C01015 [000490]  3428  	blbs	p6, trap__iacv_pal		; set=>bad iva in pal mode!
         48E1B684 [000494]  3429  	srl	p7, #EV6__EXC_SUM__BAD_IVA__S, p4
         F080000F [000498]  3430  	blbs	p4, trap__iacv_bad_iva		; set=>bad_iva
         48E53684 [00049C]  3431  	srl	p7, #EV6__EXC_SUM__PC_OVFL__S, p4
         F0800001 [0004A0]  3432  	blbs	p4, trap__iacv_pc_ovfl		; set=>pc_ovfl
         C3E00FF6 [0004A4]  3433  	br	r31, trap__iacv_post		; normal acv
                  [0004A8]  3434  ;
                  [0004A8]  3435  ; We had a pc overflow/underflow. If 43 bit mode, we can use exc_addr. If
                  [0004A8]  3436  ; 48 bit mode, we need to look at bit 47 and do some work to produce the
                  [0004A8]  3437  ; correct exception pc.
                  [0004A8]  3438  ;
                  [0004A8]  3439  trap__iacv_pc_ovfl:
         649F1110 [0004A8]  3440  	hw_mfpr	p4, EV6__I_CTL			; (4,0L) look at va_48
         4881F684 [0004AC]  3441  	srl	p4, #EV6__I_CTL__VA_48__S, p4
         F0800001 [0004B0]  3442  	blbs	p4, trap__iacv_va_48		; set=>pc_ovfl & va_48
         C3E00FF2 [0004B4]  3443  	br	r31, trap__iacv_post		; post as is from exc_addr
                  [0004B8]  3444  
                  [0004B8]  3445  trap__iacv_va_48:				; pc_ovfl & va_48
         48C5F684 [0004B8]  3446  	srl	p6, #47, p4			; check exc_addr<47>
         E0800002 [0004BC]  3447  	blbc	p4, trap__iacv_under		; branch for underflow
         48D81606 [0004C0]  3448  	zap	p6, #^xC0, p6			; overflow=> <63:48>=0
         C3E00FEE [0004C4]  3449  	br	r31, trap__iacv_post		; post
                  [0004C8]  3450  
                  [0004C8]  3451  trap__iacv_under:				; underflow=> <63:48>=1
         43E03524 [0004C8]  3452  	subq	r31, #1, p4			; generate all 1s
         48981624 [0004CC]  3453  	zapnot	p4, #^xC0, p4			; clean lower bytes
         44C40406 [0004D0]  3454  	or	p6, p4, p6			; or 1s into <63:48>
         C3E00FEA [0004D4]  3455  	br	r31, trap__iacv_post		; post
                  [0004D8]  3456  ;
                  [0004D8]  3457  ; JSR memory format instruction generated a bad va.
                  [0004D8]  3458  ; Restrictions list says <63:1> are valid. Should we zap <0>?? Yes, for now.
                  [0004D8]  3459  ;	
                  [0004D8]  3460  trap__iacv_bad_iva:
         64FFC2F0 [0004D8]  3461  	hw_mfpr p7, EV6__VA			; (4-7,1L) get address from va
         44E03106 [0004DC]  3462  	bic	p7, #1, p6			; zap bit <0> and store in p6
                  [0004E0]  3463  
         63FF4000 [0004E0]  3464  	mb					; protect va (??)
                  [0004E4]  3465  
         C3E00FE6 [0004E4]  3466  	br	r31, trap__iacv_post		; post
                  [0004E8]  3467  
                  [0004E8]  3468  	CONT_HW_VECTOR				; continue in free space
File: ev6_pal_macros.mar
                  [0004E8]    76M     ASSUME <_pal_vec_cont> eq 0
                  [0004E8]    84M     ASSUME <.-_start_of_last_vec> le <^x80>
                  [0004E8]    86M     GOTO_FREE_CODE
                  [004480]    67M     .align 6
File: ev6_osf_pal.mar
                  [004480]  3469  ;
                  [004480]  3470  ; Post the trap.
                  [004480]  3471  ; Current state:
                  [004480]  3472  ;	p6	exc_addr
                  [004480]  3473  ;
                  [004480]  3474  trap__iacv_post:
         46C11007 [004480]  3475  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p7	; current mode
         46C1F014 [004484]  3476  	and	p_misc, #OSF_P_MISC__PS__M, p20		; save original ps
         E4E00008 [004488]  3477  	beq	p7, trap__iacv_stack			; skip switch if kernel
                  [00448C]  3478  ;
                  [00448C]  3479  ; Switch to kernel mode.
                  [00448C]  3480  ; Current state:
                  [00448C]  3481  ;	p6		exc_addr
                  [00448C]  3482  ;	p20		original ps
                  [00448C]  3483  ;
                  [00448C]  3484  iacv_cm_offset = <trap__iacv_stack - trap__iacv_cm>
                  [00448C]  3485  
         7FD51020 [00448C]  3486  	hw_stq/p r30, PT__USP(p_temp)				; save user SP
         6FD51018 [004490]  3487  	hw_ldq/p r30, PT__KSP(p_temp)				; get kernel SP
         46C1F116 [004494]  3488  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc		; cm=0, ipl=0
                  [004498]  3489  
         C0E00000 [004498]  3490  	br	p7, trap__iacv_cm			; change mode to kernel
                  [00449C]  3491  trap__iacv_cm:
         40E23407 [00449C]  3492  	addq	p7, #<iacv_cm_offset+1>, p7		; jump past in palmode
         77FF0910 [0044A0]  3493  	hw_mtpr	r31, EV6__PS				; (4,0L) switch to kern
         D3E00000 [0044A4]  3494  	bsr	r31, .					; push prediction stack
                  [0044A8]  3495  	PVC_JSR	iacv_cm					; synch up
File: ev6_pal_macros.mar
                  [0044A8]   531i  pvc_lbl \pcv_index, \pcv_jsr_iacv_cm0, osf
File: ev6_osf_pal.mar
         7BE7A000 [0044A8]  3496  	hw_ret_stall (p7)				; pop prediction stack
                  [0044AC]  3497  	PVC_JSR	iacv_cm, dest=1
File: ev6_pal_macros.mar
                  [0044AC]   534i  pvc_lbl \pcv_index, \pcv_jsr_iacv_cm0, osf, \pcv_jsr_iacv_cm0_inst
File: ev6_osf_pal.mar
                  [0044AC]  3498  ;
                  [0044AC]  3499  ; Take the trap. Be careful of tb miss!
                  [0044AC]  3500  ; Current state:
                  [0044AC]  3501  ;	p6		exc_addr
                  [0044AC]  3502  ;	p20		original ps
                  [0044AC]  3503  ;	p_misc__ps	if we were in kernel, original ps
                  [0044AC]  3504  ;			if we were in user, new ps = 0 (cm=0, ipl=0)
                  [0044AC]  3505  ;
                  [0044AC]  3506  trap__iacv_stack:
         7CD51060 [0044AC]  3507  	hw_stq/p p6, PT__STACK_PC(p_temp)		; store away pc
                  [0044B0]  3508  
         23DEFFD0 [0044B0]  3509  	lda	r30, <0-OSF_FRM__SIZE>(r30)		; allocate stack space
                  [0044B4]  3510  
         B69E0000 [0044B4]  3511  	stq	p20, OSF_FRM__PS(r30)			; save original ps
         B65E0028 [0044B8]  3512  	stq	r18, OSF_FRM__A2(r30)			; save a2
                  [0044BC]  3513  
         6E951060 [0044BC]  3514  	hw_ldq/p p20, PT__STACK_PC(p_temp)		; 1.39 get nextpc back
                  [0044C0]  3515  
         B7BE0010 [0044C0]  3516  	stq	r29, OSF_FRM__GP(r30)			; save gp
         B61E0018 [0044C4]  3517  	stq	r16, OSF_FRM__A0(r30)			; save a0
         B63E0020 [0044C8]  3518  	stq	r17, OSF_FRM__A1(r30)			; save a1
         B69E0008 [0044CC]  3519  	stq	p20, OSF_FRM__PC(r30)			; 1.39 save pc
                  [0044D0]  3520  
         6EF51048 [0044D0]  3521  	hw_ldq/p p23, PT__ENT_MM(p_temp)		; get entry point
         6FB51028 [0044D4]  3522  	hw_ldq/p r29, PT__KGP(p_temp)			; get kgp
         469F0410 [0044D8]  3523  	bis	p20, r31, r16				; 1.39 a0 <- pc/va
         223F0001 [0044DC]  3524  	lda	r17, OSF_MMCSR__ACV(r31)		; a1 <- MMCSR
         43E03532 [0044E0]  3525  	subq	r31, #1, r18				; a2 <- istream (-1)
                  [0044E4]  3526  
         7BF78000 [0044E4]  3527  	hw_ret	(p23)					; to os
                  [0044E8]  3528  ;
                  [0044E8]  3529  ; JSR memory format instruction generated a bad va while in pal mode.
                  [0044E8]  3530  ; We don't even bother checking the bad_iva bit, because that's the only
                  [0044E8]  3531  ; way we can get here in pal mode.
                  [0044E8]  3532  ;
                  [0044E8]  3533  ; Set PT__HALT_CODE to HALT__SW_HALT. (Is there a better one ??)
                  [0044E8]  3534  ; Branch to update PCB and enter console.
                  [0044E8]  3535  ;
                  [0044E8]  3536  ; For now, we stick a MB in to ensure that the mfpr VA is issued, though
                  [0044E8]  3537  ; it's unlikely we will have any virtual loads after this.
                  [0044E8]  3538  ;
                  [0044E8]  3539  
                  [0044E8]  3540  trap__iacv_pal:
         64FFC2F0 [0044E8]  3541  	hw_mfpr	p7, EV6__VA			; (4-7,1L) get address from va
         44E03407 [0044EC]  3542  	bis	p7, #1, p7			; or in PALmode bit
         229F0005 [0044F0]  3543  	lda	p20, HALT__SW_HALT(r31)		; is there a better code ??
         7E9510C8 [0044F4]  3544  	hw_stq/p p20, PT__HALT_CODE(p_temp)	; store code (??)
         44FF0417 [0044F8]  3545  	bis	p7, r31, p23			; fault pc to p23
                  [0044FC]  3546  
         63FF4000 [0044FC]  3547  	mb					; make sure we issue mfpr VA
                  [004500]  3548  
         C3E0009F [004500]  3549  	br	r31, trap__update_pcb_and_halt
                  [004504]  3550  
                  [004504]  3551  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [004504]    61M         GOTO_FREE_CODE
00000000 00000000 [004504]    67M     .align 6
00000000 00000000 [00450C]
00000000 00000000 [004514]
00000000 00000000 [00451C]
00000000 00000000 [004524]
00000000 00000000 [00452C]
00000000 00000000 [004534]
         00000000 [00453C]
File: ev6_osf_pal.mar
                  [004540]  3552  ;+
                  [004540]  3553  ; MCHK - offset 500
                  [004540]  3554  ;
                  [004540]  3555  ; Entry:
                  [004540]  3556  ;	Vectored into via hardware trap on a machine check.
                  [004540]  3557  ;-
                  [004540]  3558  	START_HW_VECTOR <MCHK>
File: ev6_pal_macros.mar
                  [004540]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000500]    49i TRAP__MCHK:
File: ev6_osf_pal.mar
                  [000500]  3559  
         66FF0600 [000500]  3560  	hw_mfpr	p23, EV6__EXC_ADDR		; (0L) exception addr
         47FF041F [000504]  3561  	bis	r31, r31, r31			; 1.41 cut down on double mchks
         47FF041F [000508]  3562  	bis	r31, r31, r31
         47FF041F [00050C]  3563  	bis	r31, r31, r31
                  [000510]  3564  
         E7E00000 [000510]  3565  	beq	r31, trap__mchk_mb
                  [000514]  3566  trap__mchk_mb:
         63FF4000 [000514]  3567  	mb
         63FF4000 [000518]  3568  	mb					; 1.41 end of new part
         C3E016B8 [00051C]  3569  	br	r31, sys__mchk			; finish in system part
                  [000520]  3570  ;
                  [000520]  3571  ; Bugcheck from call_pal
                  [000520]  3572  ; Current state:
                  [000520]  3573  ;	p23		pc+4 of call_pal
                  [000520]  3574  ;
                  [000520]  3575  trap__pal_os_bugcheck:
         42E09537 [000520]  3576  	subq	p23, #4, p23			; decrement pc
         20FF0090 [000524]  3577  	lda	p7, MCHK__OS_BUGCHECK(r31)	; mchk code
         C3E00001 [000528]  3578  	br	r31, trap__pal_bugcheck
                  [00052C]  3579  ;
                  [00052C]  3580  ; Bugcheck from pal mode
                  [00052C]  3581  ; Current state:
                  [00052C]  3582  ;	p23		exc_addr
                  [00052C]  3583  ;
                  [00052C]  3584  trap__pal_exc_bugcheck:
         20FF008E [00052C]  3585  	lda	p7, MCHK__BUGCHECK(r31)		; mchk code
                  [000530]  3586  
                  [000530]  3587  trap__pal_bugcheck:
                  [000530]  3588  
         48E51727 [000530]  3589  	sll	p7, #OSF_P_MISC__MCHK_CODE__S, p7
         4AC050C5 [000534]  3590  	extbl	p_misc, #2, p5			; get mces
         4ACF1616 [000538]  3591  	zap	p_misc, #^x78, p_misc		; clear mchk_code & SCBv
                  [00053C]  3592  
         44A03406 [00053C]  3593  	bis	p5, #<1@MCES__MCHK__S>, p6	; set MCES<MCHK>
         48C21726 [000540]  3594  	sll	p6, #OSF_P_MISC__MCES__MCHK__S, p6
                  [000544]  3595  
         209F0670 [000544]  3596  	lda	p4, SCB__PROCMCHK(r31)		; SCB vector
         48831724 [000548]  3597  	sll	p4, #OSF_P_MISC__SCBV__S, p4	; move SCBv into position
                  [00054C]  3598  
         44C40406 [00054C]  3599  	bis	p6, p4, p6			; or mces and scbv
         44C70416 [000550]  3600  	bis	p6, p7, p_misc			; or mchk code
                  [000554]  3601  
         F0A0179B [000554]  3602  	blbs	p5, sys__double_machine_check	; halt on double
                  [000558]  3603  ;
                  [000558]  3604  ; Now compute where the frame is.
                  [000558]  3605  ;
                  [000558]  3606  	CONT_HW_VECTOR<MCHK>				; 1.41 move to here
File: ev6_pal_macros.mar
                  [000558]    76M     ASSUME <_pal_vec_cont> eq 0
         C3E00FF9 [000558]    81i 	br	r31, TRAP__MCHK_CONT
                  [00055C]    84M                 ASSUME <.-_start_of_last_vec> le <^x80>
                  [00055C]    86M     GOTO_FREE_CODE
                  [004540]    67M     .align 6
                  [004540]    91i TRAP__MCHK_CONT:
File: ev6_osf_pal.mar
                  [004540]  3607  
         6C951098 [004540]  3608  	hw_ldq/p p4, PT__WHAMI(p_temp)			; get whami
                  [004544]  3609  
         20BF0400 [004544]  3610  	lda	p5, PAL__LOGOUT_SPECIFIC_SIZE(r31)	; short&long size
         4C850405 [004548]  3611  	mulq	p4, p5, p5				; * whami
                  [00454C]  3612  
                  [00454C]  3613  	GET_32CONS	p6, PAL__LOGOUT_BASE, r31	; logout base
File: ev6_pal_macros.mar
                  [00454C]   239i  ASSUME <pal__logout_base> le  <^x7FFFFFFF>
         24DF0000 [00454C]   240M 	ldah	p6,<<pal__logout_base>+32768>@-16(r31); + xxx<31:16>
         20C66000 [004550]   241M 	lda	p6,<<pal__logout_base> & ^XFFFF>(p6) ; r31+xxx<15:0>
File: ev6_osf_pal.mar
         40A60405 [004554]  3614  	addq	p5, p6, p5				; (size*whami) + base
         20A50100 [004558]  3615  	lda	p5, MCHK__BASE(p5)			; start of mchk area
                  [00455C]  3616  
         7EE51058 [00455C]  3617  	hw_stq/p p23, MCHK__EXC_ADDR(p5)		; store exc_addr
         7EF51060 [004560]  3618  	hw_stq/p p23, PT__STACK_PC(p_temp)		; save fault pc
                  [004564]  3619  							; 1.41 delete
                  [004564]  3620  							;   erroneous branch
         649F0D00 [004564]  3621  	hw_mfpr	p4, EV6__ISUM				; 1.41 get isum here
         7C851068 [004568]  3622  	hw_stq/p p4, MCHK__ISUM(p5)			; 1.41 save isum
                  [00456C]  3623  ;
                  [00456C]  3624  ; To be neat, write 0 to the cbox logout quadwords and mm_stat logout
                  [00456C]  3625  ; quadword. Log ic_stat and dc_stat but don't clear them.
                  [00456C]  3626  ;
         7FE51030 [00456C]  3627  	hw_stq/p r31, MCHK_CRD__DC1_SYNDROME(p5)	; store 0
         7FE51038 [004570]  3628  	hw_stq/p r31, MCHK_CRD__DC0_SYNDROME(p5)	; store 0
         7FE51040 [004574]  3629  	hw_stq/p r31, MCHK_CRD__C_STAT(p5)		; store 0
         7FE51048 [004578]  3630  	hw_stq/p r31, MCHK_CRD__C_STS(p5)		; store 0
         7FE51028 [00457C]  3631  	hw_stq/p r31, MCHK_CRD__C_ADDR(p5)		; store 0
                  [004580]  3632  
         7FE51050 [004580]  3633  	hw_stq/p r31, MCHK_CRD__MM_STAT(p5)		; store 0
                  [004584]  3634  
         649F1610 [004584]  3635  	hw_mfpr p4, EV6__I_STAT				; (4,0L) get i_stat
         64DF2A40 [004588]  3636  	hw_mfpr	p6, EV6__DC_STAT			; (6,0L) get dc_stat
         7C851018 [00458C]  3637  	hw_stq/p p4, MCHK_CRD__I_STAT(p5)		; store i_stat
         7CC51020 [004590]  3638  	hw_stq/p p6, MCHK_CRD__DC_STAT(p5)		; store dc_stat
                  [004594]  3639  
         47FF0414 [004594]  3640  	bis	r31, r31, p20				; no retry
         C3E006DF [004598]  3641  	br	r31, sys__mchk_header			; merge
                  [00459C]  3642  
                  [00459C]  3643  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [00459C]    61M         GOTO_FREE_CODE
00000000 00000000 [00459C]    67M     .align 6
00000000 00000000 [0045A4]
00000000 00000000 [0045AC]
00000000 00000000 [0045B4]
         00000000 [0045BC]
File: ev6_osf_pal.mar
                  [0045C0]  3644  
                  [0045C0]  3645  ;+
                  [0045C0]  3646  ; ITB_MISS - offset 580
                  [0045C0]  3647  ;
                  [0045C0]  3648  ; Entry:
                  [0045C0]  3649  ;	Vectored into via hardware trap on Istream translation buffer miss.
                  [0045C0]  3650  ;
                  [0045C0]  3651  ; Function:
                  [0045C0]  3652  ;	Do a virtual fetch of the PTE, and fill the ITB if the PTE is both
                  [0045C0]  3653  ;	valid and is not FOE. If invalid or FOE, exit to trap__invalid_ipte
                  [0045C0]  3654  ;	or trap__foe. The virtual fetch can trap into double.
                  [0045C0]  3655  ;
                  [0045C0]  3656  ; Note:
                  [0045C0]  3657  ;	The ITB_PTE register has the PFN starting at bit 13, so the
                  [0045C0]  3658  ;	fetched pte must be manipulated before being written.
                  [0045C0]  3659  ;	Also, we want to keep the main flow in a single cache line
                  [0045C0]  3660  ;	(4 fetch blocks) to be as efficient as possible.
                  [0045C0]  3661  ;
                  [0045C0]  3662  ; NOTE: 
                  [0045C0]  3663  ;	1-to-1 mapping scheme implemented with bit in p_misc shadow
                  [0045C0]  3664  ; 	register. And we can probably stick it in bit 63 and just branch
                  [0045C0]  3665  ;	on negative. Right now we shift and test. Critical path has the
                  [0045C0]  3666  ;	cycle count.
                  [0045C0]  3667  ;
                  [0045C0]  3668  ; Register use:
                  [0045C0]  3669  ;	p4	shadow register reserved for itb/dtb miss
                  [0045C0]  3670  ;	p5	shadow register reserved for double miss
                  [0045C0]  3671  ;	p6	shadow register reserved for itb/dtb miss
                  [0045C0]  3672  ;	p7	shadow register reserved for dtb miss
                  [0045C0]  3673  ;	p_misc	physical mode bit
                  [0045C0]  3674  ;	p23	exc_addr of instruction causing ITB miss
                  [0045C0]  3675  ;
                  [0045C0]  3676  ; Exit state:
                  [0045C0]  3677  ;	On exit to trap__invalid_ipte or trap__foe
                  [0045C0]  3678  ;	p4	PTE
                  [0045C0]  3679  ;	p23	pc of instruction causing ITB miss
                  [0045C0]  3680  ;-
                  [0045C0]  3681  	START_HW_VECTOR <ITB_MISS>
File: ev6_pal_macros.mar
                  [0045C0]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000580]    49i TRAP__ITB_MISS:
File: ev6_osf_pal.mar
                  [000580]  3682  
                  [000580]  3683  ASSUME OSF_P_MISC__PHYS__S eq 63
                  [000580]  3684  
         649F0710 [000580]  3685  	hw_mfpr	p4, EV6__IVA_FORM		; (0L) get vpte address
         66FF0600 [000584]  3686  	hw_mfpr	p23, EV6__EXC_ADDR		; (0L) get exception address 
         20DF0FFF [000588]  3687  	lda	p6, ^x0FFF(r31)			; (xU) create mask for prot
         47FF041F [00058C]  3688  	bis	r31, r31, r31			; (xU) fill out fetch block
                  [000590]  3689  
                  [000590]  3690  trap__itb_miss_vpte:
         6C845000 [000590]  3691  	hw_ldq/v p4, (p4)			; (xL) get vpte
         44860005 [000594]  3692  	and	p4, p6, p5			; (xL) get prot bits
         EAC01009 [000598]  3693  	blt	p_misc, trap__i1to1		; (xU) 1-to-1 => branch
         48841686 [00059C]  3694  	srl	p4, #OSF_PTE__PFN__S, p6	; (xU) shift PFN to <0>
                  [0005A0]  3695  
         48C1B726 [0005A0]  3696  	sll	p6, #EV6__ITB_PTE__PFN__S, p6	; (xU) shift PFN into place
         44811007 [0005A4]  3697  	and	p4, #<1@OSF_PTE__FOE__S>, p7	; (xL) get FOE bit
         E080100E [0005A8]  3698  	blbc	p4, trap__invalid_ipte		; (xU) invalid => branch
         F4E0100B [0005AC]  3699  	bne	p7, trap__foe			; (xU) FOE => branch
                  [0005B0]  3700  
         4880F687 [0005B0]  3701  	srl	p4, #7, p7			; check for mb bit
         44A60406 [0005B4]  3702  	bis	p5, p6, p6			; (xL) PTE in ITB format
                  [0005B8]  3703  
                  [0005B8]  3704  .if eq force_path2				; 1.44 force_path2 = 0
                  [0005B8]  3705  
                  [0005B8]  3706  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
                  [0005B8]  3707  
                  [0005B8]  3708  	PVC_VIOLATE <2>				; ignore scoreboard violation
                  [0005B8]  3709  	hw_mtpr	p23, EV6__ITB_TAG		; (6,0L) write tag
                  [0005B8]  3710  	hw_mtpr	p6, <EV6__ITB_PTE ! ^x40>	; (0&4&6,0L) write PTE
                  [0005B8]  3711  
                  [0005B8]  3712  ASSUME <tb_mb_en + pte_eco> ne 2
                  [0005B8]  3713  
                  [0005B8]  3714    .if ne pte_eco
                  [0005B8]  3715  	blbc    p7, trap__itb_miss_mb		; branch for mb
                  [0005B8]  3716  	hw_ret_stall (p23)			; return
                  [0005B8]  3717  
                  [0005B8]  3718  trap__itb_miss_mb:
                  [0005B8]  3719  	mb
                  [0005B8]  3720  	hw_ret_stall (p23)			; return
                  [0005B8]  3721    .iff
                  [0005B8]  3722  	hw_ret_stall (p23)			; return
                  [0005B8]  3723    .endc						; pte_eco
                  [0005B8]  3724  
                  [0005B8]  3725  .iff						; 1.44 force_path2 = 1
                  [0005B8]  3726  ;
                  [0005B8]  3727  ; We need to avoid the situation where a ldx_l has acquired a lock,
                  [0005B8]  3728  ; another processor has taken it, and a bad path before a stx_c has
                  [0005B8]  3729  ; a load which pulls the data back in and makes it look like the
                  [0005B8]  3730  ; lock has succeeded.
                  [0005B8]  3731  ;
                  [0005B8]  3732  ; Hold up pte write, which holds up loads. Since hw_ret_stall is in
                  [0005B8]  3733  ; same fetch block (it would normally scoreboard stall off bit 0),
                  [0005B8]  3734  ; it fires off right away and will mispredict before any loads
                  [0005B8]  3735  ; can happen.
                  [0005B8]  3736  ;
                  [0005B8]  3737  	mb					; allow hw_ret to fire
                  [0005B8]  3738  	mulq	p6, #1, p6			; hold up loads
                  [0005B8]  3739  
                  [0005B8]  3740  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
                  [0005B8]  3741  
                  [0005B8]  3742  	PVC_VIOLATE <2>				; ignore scoreboard violation
                  [0005B8]  3743  	mulq	p6, #1, p6			; hold up loads
                  [0005B8]  3744  	hw_mtpr	p23, EV6__ITB_TAG		; (6,0L) write tag
                  [0005B8]  3745  	hw_mtpr	p6, <EV6__ITB_PTE ! ^x40>	; (0&4&6,0L) write PTE
                  [0005B8]  3746  	hw_ret_stall (p23)			; mis-predict before any loads
                  [0005B8]  3747  
                  [0005B8]  3748  .endc						; 1.44 force_path2
                  [0005B8]  3705I 
                  [0005B8]  3706I 	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
47FF041F 47FF041F [0005B8]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
                  [0005C0]  3707I 
                  [0005C0]  3708I 	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [0005C0]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         77F70040 [0005C0]  3709I 	hw_mtpr	p23, EV6__ITB_TAG		; (6,0L) write tag
         77E60151 [0005C4]  3710I 	hw_mtpr	p6, <EV6__ITB_PTE ! ^x40>	; (0&4&6,0L) write PTE
                  [0005C8]  3711I 
                  [0005C8]  3712I ASSUME <tb_mb_en + pte_eco> ne 2
                  [0005C8]  3713I 
                  [0005C8]  3714I   .if ne pte_eco
                  [0005C8]  3715I 	blbc    p7, trap__itb_miss_mb		; branch for mb
                  [0005C8]  3716I 	hw_ret_stall (p23)			; return
                  [0005C8]  3717I 
                  [0005C8]  3718I trap__itb_miss_mb:
                  [0005C8]  3719I 	mb
                  [0005C8]  3720I 	hw_ret_stall (p23)			; return
                  [0005C8]  3721I   .iff
                  [0005C8]  3722I 	hw_ret_stall (p23)			; return
                  [0005C8]  3723I   .endc						; pte_eco
         E0E00001 [0005C8]  3715I 	blbc    p7, trap__itb_miss_mb		; branch for mb
         7BF7A000 [0005CC]  3716I 	hw_ret_stall (p23)			; return
                  [0005D0]  3717I 
                  [0005D0]  3718I trap__itb_miss_mb:
         63FF4000 [0005D0]  3719I 	mb
         7BF7A000 [0005D4]  3720I 	hw_ret_stall (p23)			; return
                  [0005D8]  3724I   
                  [0005D8]  3749  
                  [0005D8]  3750  	CONT_HW_VECTOR				; 1.41 continue in free space
File: ev6_pal_macros.mar
                  [0005D8]    76M     ASSUME <_pal_vec_cont> eq 0
                  [0005D8]    84M     ASSUME <.-_start_of_last_vec> le <^x80>
                  [0005D8]    86M     GOTO_FREE_CODE
                  [0045C0]    67M     .align 6
File: ev6_osf_pal.mar
                  [0045C0]  3751  
                  [0045C0]  3752  ;+
                  [0045C0]  3753  ; Do a 1-1 mapping
                  [0045C0]  3754  ; Current state
                  [0045C0]  3755  ;	p23	exc_addr
                  [0045C0]  3756  ;-
                  [0045C0]  3757  trap__i1to1:
         4AE1B686 [0045C0]  3758  	srl	p23, #13, p6			; shift out the byte offset
         20BF0301 [0045C4]  3759  	lda	p5, ^x0301(r31)			; all read enable
         48C1B726 [0045C8]  3760  	sll	p6, #EV6__ITB_PTE__PFN__S, p6	; get pfn into position
         44C50406 [0045CC]  3761  	bis	p6, p5, p6			; produce the pte
                  [0045D0]  3762  
                  [0045D0]  3763  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
                  [0045D0]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
                  [0045D0]  3764  
                  [0045D0]  3765  	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [0045D0]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         77F70040 [0045D0]  3766  	hw_mtpr	p23, EV6__ITB_TAG		; (6,0L) write tag
         77E60151 [0045D4]  3767  	hw_mtpr	p6, <EV6__ITB_PTE ! ^x40>	; (0&4&6,0L) write PTE
                  [0045D8]  3768  
                  [0045D8]  3769      .if eq force_path				; 1.41
                  [0045D8]  3770  	hw_ret_stall (p23)			; return
                  [0045D8]  3771      .iff
                  [0045D8]  3772  	ALIGN_FETCH_BLOCK <^x47FF041F>
                  [0045D8]  3773  	PVC_VIOLATE <1007>
                  [0045D8]  3774  	PVC_VIOLATE <1020>			; stop permutation
                  [0045D8]  3775  	hw_jmp_stall (p23)			; return with jmp
                  [0045D8]  3776  	br	r31, .-4			; stop predictor
                  [0045D8]  3777      .endc					; 1.41
         7BF7A000 [0045D8]  3770I 	hw_ret_stall (p23)			; return
                  [0045DC]  3778      
                  [0045DC]  3779  
                  [0045DC]  3780  ;+
                  [0045DC]  3781  ; trap__foe - Fault On Execute Istream PTE fetched by ITB miss routine.
                  [0045DC]  3782  ;
                  [0045DC]  3783  ; Entry:
                  [0045DC]  3784  ;	On branch from trap__itb_miss flow.
                  [0045DC]  3785  ;
                  [0045DC]  3786  ; Function:
                  [0045DC]  3787  ;	At this point, we know FOE is set, and TNV isn't.
                  [0045DC]  3788  ;	But we haven't checked for ACV. Assume FOE and merge
                  [0045DC]  3789  ;	with invalid Istream PTE code.
                  [0045DC]  3790  ;
                  [0045DC]  3791  ; Current state:
                  [0045DC]  3792  ;	p4	PTE
                  [0045DC]  3793  ;	p23	faulting va/pc
                  [0045DC]  3794  ;
                  [0045DC]  3795  ; Exit state:
                  [0045DC]  3796  ;	On exit to trap__invalid_ipte_merge
                  [0045DC]  3797  ;	p4	PTE
                  [0045DC]  3798  ;	p5	OSF_MMCSR__FOE
                  [0045DC]  3799  ;	p23	pc/va of instruction causing ITB miss
                  [0045DC]  3800  ;-
                  [0045DC]  3801  trap__foe:
         20BF0003 [0045DC]  3802  	lda	p5, OSF_MMCSR__FOE(r31)		; assume FOE
         C3E00001 [0045E0]  3803  	br	r31, trap__invalid_ipte_merge	; Merge with invalid flow
                  [0045E4]  3804  
                  [0045E4]  3805  ;+
                  [0045E4]  3806  ; trap__invalid_ipte - Invalid Istream PTE fetched by ITB miss routine.
                  [0045E4]  3807  ;
                  [0045E4]  3808  ; Entry:
                  [0045E4]  3809  ;	On branch from trap__itb_miss flow.
                  [0045E4]  3810  ;
                  [0045E4]  3811  ; Function:
                  [0045E4]  3812  ;	At this point, we know we know we have TNV, but we haven't checked
                  [0045E4]  3813  ;	for ACV, which takes precedence. We also have a merge from the
                  [0045E4]  3814  ;	trap__foe flow, which was entered on FOE and no TNV. Take
                  [0045E4]  3815  ;	a trap.
                  [0045E4]  3816  ;
                  [0045E4]  3817  ; Current state:
                  [0045E4]  3818  ;	p4		PTE
                  [0045E4]  3819  ;	p23		faulting va/pc
                  [0045E4]  3820  ;
                  [0045E4]  3821  ; When merging from trap_foe:
                  [0045E4]  3822  ;	p5		OSF_MMCSR__FOE
                  [0045E4]  3823  ;-
                  [0045E4]  3824  
                  [0045E4]  3825  trap__invalid_ipte:
         20BF0000 [0045E4]  3826  	lda	p5, OSF_MMCSR__TNV(r31)			; assume TNV
                  [0045E8]  3827  
                  [0045E8]  3828  trap__invalid_ipte_merge:				; merge from FOE flow
         46C11007 [0045E8]  3829  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p7	; current mode
         46C1F014 [0045EC]  3830  	and	p_misc, #OSF_P_MISC__PS__M, p20		; save original ps
         E4E00009 [0045F0]  3831  	beq	p7, trap__invalid_ipte_stack		; skip switch if kernel
                  [0045F4]  3832  ;
                  [0045F4]  3833  ; Switch to kernel mode.
                  [0045F4]  3834  ; Current state:
                  [0045F4]  3835  ;	p4		PTE
                  [0045F4]  3836  ;	p5		marks TNV or FOE
                  [0045F4]  3837  ;	p20		original ps
                  [0045F4]  3838  ;
                  [0045F4]  3839  ipte_cm_offset = <trap__invalid_ipte_stack - trap__invalid_ipte_cm>
                  [0045F4]  3840  
         7FD51020 [0045F4]  3841  	hw_stq/p r30, PT__USP(p_temp)				; save user SP
         6FD51018 [0045F8]  3842  	hw_ldq/p r30, PT__KSP(p_temp)				; get kernel SP
         48803684 [0045FC]  3843  	srl	p4, #<OSF_PTE__URE__S - OSF_PTE__KRE__S>, p4	; shift u to k
         46C1F116 [004600]  3844  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc		; cm=0, ipl=0
                  [004604]  3845  
         C0E00000 [004604]  3846  	br	p7, trap__invalid_ipte_cm		; change mode to kernel
                  [004608]  3847  trap__invalid_ipte_cm:
         40E23407 [004608]  3848  	addq	p7, #<ipte_cm_offset+1>, p7		; jump past in palmode
         77FF0910 [00460C]  3849  	hw_mtpr	r31, EV6__PS				; (4,0L) switch to kern
         D3E00000 [004610]  3850  	bsr	r31, .					; push prediction stack
                  [004614]  3851  	PVC_JSR	ipte_cm					; synch up
File: ev6_pal_macros.mar
                  [004614]   531i  pvc_lbl \pcv_index, \pcv_jsr_ipte_cm0, osf
File: ev6_osf_pal.mar
         7BE7A000 [004614]  3852  	hw_ret_stall (p7)				; pop prediction stack
                  [004618]  3853  	PVC_JSR	ipte_cm, dest=1
File: ev6_pal_macros.mar
                  [004618]   534i  pvc_lbl \pcv_index, \pcv_jsr_ipte_cm0, osf, \pcv_jsr_ipte_cm0_inst
File: ev6_osf_pal.mar
                  [004618]  3854  ;
                  [004618]  3855  ; Take the trap. Be careful of tb miss!
                  [004618]  3856  ; Current state:
                  [004618]  3857  ;	p4		PTE. If user, now shifted right to kernel position
                  [004618]  3858  ;	p5		TNV or FOE
                  [004618]  3859  ;	p20		original ps
                  [004618]  3860  ;	p23		pc of instruction taking itb miss
                  [004618]  3861  ;	p_misc__ps	if we were in kernel, original ps
                  [004618]  3862  ;			if we were in user, new ps = 0 (cm=0, ipl=0)
                  [004618]  3863  ;
                  [004618]  3864  
                  [004618]  3865  trap__invalid_ipte_stack:
         7EF51060 [004618]  3866  	hw_stq/p p23, PT__STACK_PC(p_temp)		; store away pc
                  [00461C]  3867  
         48811684 [00461C]  3868  	srl	p4, #OSF_PTE__KRE__S, p4		; get <re> to <0>
         448032C5 [004620]  3869  	cmovlbc p4, #OSF_MMCSR__ACV, p5			; acv over the others
         7CB51070 [004624]  3870  	hw_stq/p p5, PT__NEW_A1(p_temp)			; save mmcsr
                  [004628]  3871  
         23DEFFD0 [004628]  3872  	lda	r30, <0-OSF_FRM__SIZE>(r30)		; allocate stack space
                  [00462C]  3873  
         B69E0000 [00462C]  3874  	stq	p20, OSF_FRM__PS(r30)			; save original ps
         B65E0028 [004630]  3875  	stq	r18, OSF_FRM__A2(r30)			; save a2
                  [004634]  3876  
         6E951060 [004634]  3877  	hw_ldq/p p20, PT__STACK_PC(p_temp)		; 1.39 get nextpc back
                  [004638]  3878  
         B7BE0010 [004638]  3879  	stq	r29, OSF_FRM__GP(r30)			; save gp
         B61E0018 [00463C]  3880  	stq	r16, OSF_FRM__A0(r30)			; save a0
         B63E0020 [004640]  3881  	stq	r17, OSF_FRM__A1(r30)			; save a1
         B69E0008 [004644]  3882  	stq	p20, OSF_FRM__PC(r30)			; 1.39 save nextpc
                  [004648]  3883  
         469F0410 [004648]  3884  	bis	p20, r31, r16				; 1.39 a0 <- pc/va
         43E03532 [00464C]  3885  	subq	r31, #1, r18				; a2 <- istream (-1)
         6EF51048 [004650]  3886  	hw_ldq/p p23, PT__ENT_MM(p_temp)		; get entry point
         6FB51028 [004654]  3887  	hw_ldq/p r29, PT__KGP(p_temp)			; get kgp
         6E351070 [004658]  3888  	hw_ldq/p r17, PT__NEW_A1(p_temp)		; a1 <- MMCSR
                  [00465C]  3889  
         7BF78000 [00465C]  3890  	hw_ret	(p23)					; to os
                  [004660]  3891  
                  [004660]  3892  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [004660]    61M         GOTO_FREE_CODE
00000000 00000000 [004660]    67M     .align 6
00000000 00000000 [004668]
00000000 00000000 [004670]
00000000 00000000 [004678]
File: ev6_osf_pal.mar
                  [004680]  3893  
                  [004680]  3894  ;+
                  [004680]  3895  ; ARITH - offset 600
                  [004680]  3896  ;
                  [004680]  3897  ; Entry:
                  [004680]  3898  ;	Vectored into via hardware trap on an arithmetic exception
                  [004680]  3899  ;	synchronous trap.
                  [004680]  3900  ;
                  [004680]  3901  ; Function:
                  [004680]  3902  ;	For floating exceptions, we may just update the FPCR (see below)
                  [004680]  3903  ;	and return to the user.
                  [004680]  3904  ;
                  [004680]  3905  ;	Otherwise build stack frame.
                  [004680]  3906  ;		r16 (a0)	Exception summary
                  [004680]  3907  ;		r17 (a1)	Register mask
                  [004680]  3908  ;		r18 (a2)	unpredictable
                  [004680]  3909  ;	Vector via entArith.
                  [004680]  3910  ;
                  [004680]  3911  ; Notes on FPCR register:
                  [004680]  3912  ;	The FPCR is both a status and control register. The status reflect
                  [004680]  3913  ;	problems encountered with the instruction. The 'disable' control bits
                  [004680]  3914  ;	and instruction modifiers have an effect on trapping to the os.
                  [004680]  3915  ;
                  [004680]  3916  ;	If a trap disable bit is set and an instruction with the /S
                  [004680]  3917  ;	qualifier set generates the associated trapping result, EV6
                  [004680]  3918  ;	produces the IEEE non-trapping result and suppresses the trap.
                  [004680]  3919  ;
                  [004680]  3920  ; 	On EV6, PALcode assistance is required to assure correction operation
                  [004680]  3921  ;	of the status bits. When the status *changes* from what is in the FPCR,
                  [004680]  3922  ;	an arithmetic exception is taken, even if there is to be no trap. The
                  [004680]  3923  ;	status changes are marked in EXC_SUM SET_condition bits. The PALcode
                  [004680]  3924  ;	uses these bits to update the FPCR. The EXC_SUM condition bits are
                  [004680]  3925  ;	examined to determine whether a trap should be delivered.
                  [004680]  3926  ;
                  [004680]  3927  ;		trap bit	set_x bit	actions
                  [004680]  3928  ;		--------	---------	-------
                  [004680]  3929  ;		0		1		no trap, set FPCR status bit
                  [004680]  3930  ;		1		0		trap, don't set FPCR bit
                  [004680]  3931  ;		1		1		trap, set FPCR status bit
                  [004680]  3932  ;
                  [004680]  3933  ;
                  [004680]  3934  ; Notes on EXC_SUM register:
                  [004680]  3935  ;		int - bit 7	iov - bit 6
                  [004680]  3936  ;		-----------	-----------
                  [004680]  3937  ;		0		1		fbox int overflow
                  [004680]  3938  ;		1		1		ebox int overflow
                  [004680]  3939  ;-
                  [004680]  3940  
                  [004680]  3941  	START_HW_VECTOR <ARITH>
File: ev6_pal_macros.mar
                  [004680]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000600]    49i TRAP__ARITH:
File: ev6_osf_pal.mar
                  [000600]  3942  
         64FF0F00 [000600]  3943  	hw_mfpr	p7, EV6__EXC_SUM			; (0L)
         66FF0600 [000604]  3944  	hw_mfpr	p23, EV6__EXC_ADDR			; (0L) exception addr
                  [000608]  3945  
                  [000608]  3946  .if ne ev6_p1
                  [000608]  3947  trap__arith_merge:					; merge for fp emulation
                  [000608]  3948  .endc
                  [000608]  3949  
         44F01004 [000608]  3950  	and	p7, #<1@EV6__EXC_SUM__INT__S>, p4	; check for int ovr
         48E11685 [00060C]  3951  	srl	p7, #EV6__EXC_SUM__REG__S, p5		; shift register field
         44A3F005 [000610]  3952  	and	p5, #EV6__EXC_SUM__REG__M, p5		; isolate register
                  [000614]  3953  
         F2FFFFC5 [000614]  3954  	blbs	p23, trap__pal_exc_bugcheck		; bugcheck on pal
                  [000618]  3955  
         48F81607 [000618]  3956  	zap	p7, #^xC0, p7				; clean <63:48>
         42E09417 [00061C]  3957  	addq	p23, #4, p23				; adjust to nextpc
         F4800001 [000620]  3958  	bne	p4, trap__arith_int			; branch on int case
         40A41405 [000624]  3959  	addq	p5, #32, p5				; set up for fx mask
                  [000628]  3960  
                  [000628]  3961  trap__arith_int:
         48E55684 [000628]  3962  	srl	p7, #EV6__EXC_SUM__SET_INV__S, p4	; check for FPCR update
         44EFF007 [00062C]  3963  	and	p7, #^x7F, p7				; isolate <6:0>
         E4801022 [000630]  3964  	beq	p4, trap__arith_post			; just post
                  [000634]  3965  
                  [000634]  3966  	CONT_HW_VECTOR <ARITH>
File: ev6_pal_macros.mar
                  [000634]    76M     ASSUME <_pal_vec_cont> eq 0
         C3E01012 [000634]    81i 	br	r31, TRAP__ARITH_CONT
                  [000638]    84M                 ASSUME <.-_start_of_last_vec> le <^x80>
                  [000638]    86M     GOTO_FREE_CODE
                  [004680]    67M     .align 6
                  [004680]    91i TRAP__ARITH_CONT:
File: ev6_osf_pal.mar
                  [004680]  3967  
                  [004680]  3968  ;
                  [004680]  3969  ; Update FPCR. Then check to see if we post.
                  [004680]  3970  ;
                  [004680]  3971  .if eq ev6_p1
                  [004680]  3972  
                  [004680]  3973  	ftoit	f0, p6				; save f0 (thanks to ftoit!)
                  [004680]  3974  	mf_fpcr	f0				; get current FPCR
                  [004680]  3975  	sll	p4, #EV6__FPCR__INV__S, p4	; shift status into place
                  [004680]  3976  	ftoit	f0, p20				; convert FPCR to integer
                  [004680]  3977  	bis	p20, p4, p20			; or in new status bits
                  [004680]  3978  	itoft	p20, f0				; turn back into float
                  [004680]  3979  
                  [004680]  3980  arith_fpcr_offset = <trap__arith_finish - trap__arith_fpcr>
                  [004680]  3981  
                  [004680]  3982  	br	p4, trap__arith_fpcr
                  [004680]  3983  trap__arith_fpcr:
                  [004680]  3984  	addq	p4, #<arith_fpcr_offset+1>, p4	; set up to jump past in palmode
                  [004680]  3985  	mt_fpcr	f0				; write FPCR
                  [004680]  3986  	bsr	r31, .				; push prediction stack
                  [004680]  3987  	PVC_JSR arith_fpcr			; synch up
                  [004680]  3988  	hw_ret_stall (p4)			; pop prediction stack
                  [004680]  3989  	PVC_JSR arith_fpcr, dest=1
                  [004680]  3990  
                  [004680]  3991  trap__arith_finish:
                  [004680]  3992  	itoft	p6, f0				; restore f0
                  [004680]  3993  	bic	p7, #1, p6			; check <6:1>
                  [004680]  3994  	bne	p6, trap__arith_post		; post if indicated
                  [004680]  3995  
                  [004680]  3996  .endc
                  [004680]  3972I 
         701F0E06 [004680]  3973I 	ftoit	f0, p6				; save f0 (thanks to ftoit!)
         5C0004A0 [004684]  3974I 	mf_fpcr	f0				; get current FPCR
         48869724 [004688]  3975I 	sll	p4, #EV6__FPCR__INV__S, p4	; shift status into place
         701F0E14 [00468C]  3976I 	ftoit	f0, p20				; convert FPCR to integer
         46840414 [004690]  3977I 	bis	p20, p4, p20			; or in new status bits
         529F0480 [004694]  3978I 	itoft	p20, f0				; turn back into float
                  [004698]  3979I 
                  [004698]  3980I arith_fpcr_offset = <trap__arith_finish - trap__arith_fpcr>
                  [004698]  3981I 
         C0800000 [004698]  3982I 	br	p4, trap__arith_fpcr
                  [00469C]  3983I trap__arith_fpcr:
         40823404 [00469C]  3984I 	addq	p4, #<arith_fpcr_offset+1>, p4	; set up to jump past in palmode
         5C000480 [0046A0]  3985I 	mt_fpcr	f0				; write FPCR
         D3E00000 [0046A4]  3986I 	bsr	r31, .				; push prediction stack
                  [0046A8]  3987I 	PVC_JSR arith_fpcr			; synch up
File: ev6_pal_macros.mar
                  [0046A8]   531i  pvc_lbl \pcv_index, \pcv_jsr_arith_fpcr0, osf
File: ev6_osf_pal.mar
         7BE4A000 [0046A8]  3988I 	hw_ret_stall (p4)			; pop prediction stack
                  [0046AC]  3989I 	PVC_JSR arith_fpcr, dest=1
File: ev6_pal_macros.mar
                  [0046AC]   534i  pvc_lbl \pcv_index, \pcv_jsr_arith_fpcr0, osf, \pcv_jsr_arith_fpcr0_inst
File: ev6_osf_pal.mar
                  [0046AC]  3990I 
                  [0046AC]  3991I trap__arith_finish:
         50DF0480 [0046AC]  3992I 	itoft	p6, f0				; restore f0
         44E03106 [0046B0]  3993I 	bic	p7, #1, p6			; check <6:1>
         F4C00001 [0046B4]  3994I 	bne	p6, trap__arith_post		; post if indicated
                  [0046B8]  3995I 
                  [0046B8]  3997  
         7BF78000 [0046B8]  3998  	hw_ret	(p23)				; back to user
                  [0046BC]  3999  
                  [0046BC]  4000  ;
                  [0046BC]  4001  ; Current state:
                  [0046BC]  4002  ;	p5	register number (adjusted for float)
                  [0046BC]  4003  ;	p7	exc_sum<6:0>
                  [0046BC]  4004  ;	p20	1
                  [0046BC]  4005  ;	p23	next pc	
                  [0046BC]  4006  ;
                  [0046BC]  4007  trap__arith_post:
         229F0001 [0046BC]  4008  	lda	p20, 1(r31)				; get a 1 for mask
         4A850725 [0046C0]  4009  	sll	p20, p5, p5				; register number to mask
                  [0046C4]  4010  
         46C11004 [0046C4]  4011  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p4	; current mode
         46C1F014 [0046C8]  4012  	and	p_misc, #OSF_P_MISC__PS__M, p20		; save original ps
         E4800008 [0046CC]  4013  	beq	p4, trap__arith_stack			; skip switch if kernel
                  [0046D0]  4014  ;
                  [0046D0]  4015  ; Switch to kernel mode. 
                  [0046D0]  4016  ;
                  [0046D0]  4017  arith_cm_offset = <trap__arith_stack - trap__arith_cm>
                  [0046D0]  4018  
         7FD51020 [0046D0]  4019  	hw_stq/p r30, PT__USP(p_temp)			; save user SP
         6FD51018 [0046D4]  4020  	hw_ldq/p r30, PT__KSP(p_temp)			; get kernel SP
         46C1F116 [0046D8]  4021  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc	; cm=0, ipl=0
                  [0046DC]  4022  
         C0C00000 [0046DC]  4023  	br	p6, trap__arith_cm			; change mode to kernel
                  [0046E0]  4024  trap__arith_cm:
         40C23406 [0046E0]  4025  	addq	p6, #<arith_cm_offset+1>, p6		; jump past in palmode
         77FF0910 [0046E4]  4026  	hw_mtpr	r31, EV6__PS				; (4,0L) switch to kern
         D3E00000 [0046E8]  4027  	bsr	r31, .					; push prediction stack
                  [0046EC]  4028  	PVC_JSR	arith_cm				; synch up
File: ev6_pal_macros.mar
                  [0046EC]   531i  pvc_lbl \pcv_index, \pcv_jsr_arith_cm0, osf
File: ev6_osf_pal.mar
         7BE6A000 [0046EC]  4029  	hw_ret_stall (p6)				; pop prediction stack
                  [0046F0]  4030  	PVC_JSR	arith_cm, dest=1
File: ev6_pal_macros.mar
                  [0046F0]   534i  pvc_lbl \pcv_index, \pcv_jsr_arith_cm0, osf, \pcv_jsr_arith_cm0_inst
File: ev6_osf_pal.mar
                  [0046F0]  4031  ;
                  [0046F0]  4032  ; Take the trap. Be careful of tb miss!
                  [0046F0]  4033  ; Current state:
                  [0046F0]  4034  ;	p5	register mask
                  [0046F0]  4035  ;	p7	exc_sum<6:0>
                  [0046F0]  4036  ;	p_misc__ps	if we were in kernel, original ps
                  [0046F0]  4037  ;			if we were in user, new ps = 0 (cm=0, ipl=0)
                  [0046F0]  4038  ;	p20		original ps
                  [0046F0]  4039  ;	p23	next pc	
                  [0046F0]  4040  ;
                  [0046F0]  4041  trap__arith_stack:
         7EF51060 [0046F0]  4042  	hw_stq/p p23, PT__STACK_PC(p_temp)		; store away nextpc
         7CF51068 [0046F4]  4043  	hw_stq/p p7, PT__NEW_A0(p_temp)			; save away exc sum
         7CB51070 [0046F8]  4044  	hw_stq/p p5, PT__NEW_A1(p_temp)			; save away reg mask
                  [0046FC]  4045  
         23DEFFD0 [0046FC]  4046  	lda	r30, <0-OSF_FRM__SIZE>(r30)		; allocate stack space
                  [004700]  4047  
         B69E0000 [004700]  4048  	stq	p20, OSF_FRM__PS(r30)			; save original ps
         B65E0028 [004704]  4049  	stq	r18, OSF_FRM__A2(r30)			; save a2
                  [004708]  4050  
         6E951060 [004708]  4051  	hw_ldq/p p20, PT__STACK_PC(p_temp)		; 1.39 get nextpc back
                  [00470C]  4052  
         B7BE0010 [00470C]  4053  	stq	r29, OSF_FRM__GP(r30)			; save gp
         B61E0018 [004710]  4054  	stq	r16, OSF_FRM__A0(r30)			; save a0
         B63E0020 [004714]  4055  	stq	r17, OSF_FRM__A1(r30)			; save a1
         B69E0008 [004718]  4056  	stq	p20, OSF_FRM__PC(r30)			; 1.39 save pc
                  [00471C]  4057  
         6EF51030 [00471C]  4058  	hw_ldq/p p23, PT__ENT_ARITH(p_temp)		; get entry point
         6FB51028 [004720]  4059  	hw_ldq/p r29, PT__KGP(p_temp)			; get kgp
         6E151068 [004724]  4060  	hw_ldq/p r16, PT__NEW_A0(p_temp)		; a0 <- exc sum
         6E351070 [004728]  4061  	hw_ldq/p r17, PT__NEW_A1(p_temp)		; a1 <- reg mask
                  [00472C]  4062  
         7BF78000 [00472C]  4063  	hw_ret	(p23)					; to os
                  [004730]  4064  
                  [004730]  4065  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [004730]    61M         GOTO_FREE_CODE
00000000 00000000 [004730]    67M     .align 6
00000000 00000000 [004738]
File: ev6_osf_pal.mar
                  [004740]  4066  
                  [004740]  4067  ;+
                  [004740]  4068  ; INTERRUPT - offset 680
                  [004740]  4069  ;
                  [004740]  4070  ; Entry:
                  [004740]  4071  ;	Vectored into via hardware trap on interrupt.
                  [004740]  4072  ;
                  [004740]  4073  ; Function:
                  [004740]  4074  ;
                  [004740]  4075  ; Note: If a new interrupt (hardware, serial line, crd or perf counter)
                  [004740]  4076  ;	occurs simultaneously with an mfpr isum, the isum read will return 0's.
                  [004740]  4077  ;	The interrupt would not be lost however. After a passive release in
                  [004740]  4078  ;	the PALcode, we would see the interrupt again. One way to
                  [004740]  4079  ;	minimize the number of passive releases is to read isum twice
                  [004740]  4080  ;	and OR the results.
                  [004740]  4081  ;-
                  [004740]  4082  
                  [004740]  4083  ipl_offset = <IPL_TABLE - trap__pal_base>
                  [004740]  4084  
                  [004740]  4085  	START_HW_VECTOR <INTERRUPT>
File: ev6_pal_macros.mar
                  [004740]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000680]    49i TRAP__INTERRUPT:
File: ev6_osf_pal.mar
                  [000680]  4086  
         66FF0600 [000680]  4087  	hw_mfpr	p23, EV6__EXC_ADDR		; (0L) get exc_addr
         649F0D00 [000684]  4088  	hw_mfpr	p4, EV6__ISUM			; (0L) get interrupt summary
         47FF041F [000688]  4089  	bis	r31, r31, r31
         47FF041F [00068C]  4090  	bis	r31, r31, r31
                  [000690]  4091  
         64BF0D00 [000690]  4092  	hw_mfpr	p5, EV6__ISUM			; (0L) read again
         44850404 [000694]  4093  	bis	p4, p5, p4			; OR the results
                  [000698]  4094  
         4883F685 [000698]  4095  	srl	p4, #EV6__ISUM__CR__S, p5	; check for cre (31)
         4883B686 [00069C]  4096  	srl	p4, #EV6__ISUM__PC__S, p6	; check for perf ctr (29)
         44C07006 [0006A0]  4097  	and	p6, #EV6__ISUM__PC__M, p6	; get just perf ctr bits
                  [0006A4]  4098  
         F0A01556 [0006A4]  4099  	blbs	p5, sys__crd			; branch if cre
         F4C01523 [0006A8]  4100  	bne	p6, sys__interrupt_pc		; branch if perf ctr
                  [0006AC]  4101  
         48843687 [0006AC]  4102  	srl	p4, #EV6__ISUM__EI__S, p7	; check for external int (20-23)
         44E7F007 [0006B0]  4103  	and	p7, #EV6__ISUM__EI__M, p7	; get just ei bits
                  [0006B4]  4104  
         E4E01022 [0006B4]  4105  	beq	p7, trap__interrupt_sl		; check sl if not ei
         C3E014DA [0006B8]  4106  	br	r31, sys__interrupt_ei		; handle ei
                  [0006BC]  4107  
                  [0006BC]  4108  	CONT_HW_VECTOR
File: ev6_pal_macros.mar
                  [0006BC]    76M     ASSUME <_pal_vec_cont> eq 0
                  [0006BC]    84M     ASSUME <.-_start_of_last_vec> le <^x80>
                  [0006BC]    86M     GOTO_FREE_CODE
                  [004740]    67M     .align 6
File: ev6_osf_pal.mar
                  [004740]  4109  ;+
                  [004740]  4110  ; Check for serial line interrupt.
                  [004740]  4111  ;-
                  [004740]  4112  trap__interrupt_sl:
         48841687 [004740]  4113  	srl	p4, #EV6__ISUM__SL__S, p7	; check for sl
         E4E00001 [004744]  4114  	beq	p7, trap__interrupt_dismiss	; dismiss if not
         C3E004F5 [004748]  4115  	br	r31, sys__interrupt_sl		; handle sl
                  [00474C]  4116  
                  [00474C]  4117  ;+
                  [00474C]  4118  ; Interrupts not being handled yet. ???
                  [00474C]  4119  ;-
                  [00474C]  4120  trap__interrupt_passive:
                  [00474C]  4121  
                  [00474C]  4122  ;+
                  [00474C]  4123  ; Dismiss interrupt.
                  [00474C]  4124  ;-
                  [00474C]  4125  trap__interrupt_dismiss:
                  [00474C]  4126  
                  [00474C]  4127  .if eq force_path2				; 1.44 force_path2 = 0
                  [00474C]  4128  
                  [00474C]  4129  	hw_ret_stall (p23)			; return to user
                  [00474C]  4130  
                  [00474C]  4131  .iff						; 1.44 force_path2 = 1
                  [00474C]  4132  ;
                  [00474C]  4133  ; We need to avoid the situation where a ldx_l has acquired a lock,
                  [00474C]  4134  ; another processor has taken it, and a bad path before a stx_c has
                  [00474C]  4135  ; a load which pulls the data back in and makes it look like the
                  [00474C]  4136  ; lock has succeeded. Hold up loads by writing to MM_STAT with
                  [00474C]  4137  ; scoreboard bit 2 (and 6 -- 6 is required or we hang).
                  [00474C]  4138  ;
                  [00474C]  4139  	mb					; make sure hw_ret goes
                  [00474C]  4140  
                  [00474C]  4141  	ALIGN_FETCH_BLOCK <^x47FF041F>
                  [00474C]  4142  	mulq	p6, #1, p6			; hold up loads
                  [00474C]  4143  	mulq	p6, #1, p6			; hols up loads
                  [00474C]  4144  	hw_mtpr p6, <EV6__MM_STAT ! ^x44>	; hold up loads
                  [00474C]  4145  	hw_ret_stall (p23)			; return
                  [00474C]  4146  
                  [00474C]  4147  .endc						; 1.44 force_path2
                  [00474C]  4128I 
         7BF7A000 [00474C]  4129I 	hw_ret_stall (p23)			; return to user
                  [004750]  4130I 
                  [004750]  4148  
                  [004750]  4149  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [004750]    61M         GOTO_FREE_CODE
00000000 00000000 [004750]    67M     .align 6
00000000 00000000 [004758]
00000000 00000000 [004760]
00000000 00000000 [004768]
00000000 00000000 [004770]
00000000 00000000 [004778]
File: ev6_osf_pal.mar
                  [004780]  4150  
                  [004780]  4151  ;+
                  [004780]  4152  ; MT_FPCR - offset 700
                  [004780]  4153  ;
                  [004780]  4154  ; Entry:
                  [004780]  4155  ;	Vectored into via hardware trap on issue of a MT_FPCR instruction.
                  [004780]  4156  ;	This is a sychronous trap.
                  [004780]  4157  ;
                  [004780]  4158  ; Function:
                  [004780]  4159  ;	The MT_FPCR instruction is issued from the floating point queue.
                  [004780]  4160  ;	This instruction is implemented as an explicit IPR write: the value
                  [004780]  4161  ;	is written into the "first" latch, and when the instruction retires,
                  [004780]  4162  ;	the value is written into the "second" latch. There is no IPR
                  [004780]  4163  ;	scoreboarding in the floating point queue. PALcode assistance is
                  [004780]  4164  ;	required to ensure that subsequent readers of the FPCR get the
                  [004780]  4165  ;	update value.
                  [004780]  4166  ;
                  [004780]  4167  ;	The PALcode can simply return using a HW_RET_STALL. This sequence
                  [004780]  4168  ;	ensures that the MT_FPCR instruction will be correctly ordered with
                  [004780]  4169  ;	respect to subsequent readers of the FPCR.
                  [004780]  4170  ;
                  [004780]  4171  ; Register use:
                  [004780]  4172  ;	p23		exc_addr
                  [004780]  4173  ;
                  [004780]  4174  ;-
                  [004780]  4175  	START_HW_VECTOR <MT_FPCR>
File: ev6_pal_macros.mar
                  [004780]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000700]    49i TRAP__MT_FPCR:
File: ev6_osf_pal.mar
                  [000700]  4176  
         66FF0600 [000700]  4177  	hw_mfpr	p23, EV6__EXC_ADDR		; (0L) save exc_addr
                  [000704]  4178  	NOP					; keep 1st fetch block free
File: ev6_pal_macros.mar
         47FF041F [000704]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [000708]  4179  	NOP					; 	of pvc violations
File: ev6_pal_macros.mar
         47FF041F [000708]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [00070C]  4180  	NOP
File: ev6_pal_macros.mar
         47FF041F [00070C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [000710]  4181  
         42E09417 [000710]  4182  	addq	p23, #4, p23			; adjust pc
         7BF7A000 [000714]  4183  	hw_ret_stall (p23)			; return to user
                  [000718]  4184  
                  [000718]  4185  	END_HW_VECTOR
File: ev6_pal_macros.mar
                  [000718]    57i         ASSUME <.-_start_of_last_vec> le <^x80>
                  [000718]    61M         GOTO_FREE_CODE
                  [004780]    67M     .align 6
File: ev6_osf_pal.mar
                  [004780]  4186  
                  [004780]  4187  ;+
                  [004780]  4188  ; Wakeup
                  [004780]  4189  ;
                  [004780]  4190  ; Entry:
                  [004780]  4191  ;	Vectored into via hardware trap on wakeup from sleep mode.
                  [004780]  4192  ;
                  [004780]  4193  ; Current state:
                  [004780]  4194  ; 	Register file		unitialized
                  [004780]  4195  ;	EV6__EXC_ADDR		undefined
                  [004780]  4196  ;	EV6__PAL_BASE		last written
                  [004780]  4197  ;	EV6__IER		last written
                  [004780]  4198  ;	Iprs			reset state
                  [004780]  4199  ;	Cbox write-once chain	last written
                  [004780]  4200  ;	Cbox write-many chain	reset state
                  [004780]  4201  ;	EV6__SIRR<28:14>	cpu number
                  [004780]  4202  ;
                  [004780]  4203  ;-
                  [004780]  4204  
                  [004780]  4205  ;+
                  [004780]  4206  ; Initialize 80 retirator "done" status bits and mapper.
                  [004780]  4207  ; The retirator and mapper must be initialized in the
                  [004780]  4208  ; manner and order below. NO SOURCES other than
                  [004780]  4209  ; x31 may be used until "mapper source enable" is
                  [004780]  4210  ; turned on with a EV6_ITB_IA.
                  [004780]  4211  ;-
                  [004780]  4212  
                  [004780]  4213  EV6__WAKEUP_ENTRY = ^x780
                  [004780]  4214  
                  [004780]  4215  	START_HW_VECTOR <WAKEUP>
File: ev6_pal_macros.mar
                  [004780]    36M     ASSUME <_pal_func_in_prog> eq 0
                  [000780]    49i TRAP__WAKEUP:
File: ev6_osf_pal.mar
                  [000780]  4216  
                  [000780]  4217  .if eq reference_platform
                  [000780]  4218  
                  [000780]  4219  	PVC_VIOLATE <1003>
                  [000780]  4220  .iff
                  [000780]  4221  
                  [000780]  4222      i = 0
                  [000780]  4223      .repeat 15
                  [000780]  4224  	addq	r31, r31, i
                  [000780]  4225  	addq	r31, r31, <i+1>
                  [000780]  4226  	.if eq <ev6_p1>
                  [000780]  4227  	addt	f31, f31, i
                  [000780]  4228  	mult	f31, f31, <i+1>
                  [000780]  4229  	.iff
                  [000780]  4230  	addq	r31, r31, i
                  [000780]  4231  	addq	r31, r31, <i+1>
                  [000780]  4232  	.endc
                  [000780]  4233  	i = i+2
                  [000780]  4234      .endr
                  [000780]  4235  
                  [000780]  4236  	addq	r31, r31, r30
                  [000780]  4237      .if eq <ev6_p1>
                  [000780]  4238  	addt	f31, f31, f30
                  [000780]  4239      .iff
                  [000780]  4240  	addq	r31, r31, r30
                  [000780]  4241      .endc
                  [000780]  4242  	addq	r31, r31, r0
                  [000780]  4243  	addq	r31, r31, r0
                  [000780]  4244  
                  [000780]  4245      .repeat 4
                  [000780]  4246  	addq	r31, r31, r0
                  [000780]  4247  	addq	r31, r31, r0
                  [000780]  4248  	addq	r31, r31, r0
                  [000780]  4249  	addq	r31, r31, r0
                  [000780]  4250      .endr
                  [000780]  4251  
                  [000780]  4252  ;
                  [000780]  4253  ; Now turn on mapper source enables.
                  [000780]  4254  ;
                  [000780]  4255  	ASSUME_FETCH_BLOCK
                  [000780]  4256  
                  [000780]  4257  	hw_mtpr	r31, EV6__ITB_IA	; (4,0L) Flush ITB, enable source map
                  [000780]  4258  	hw_mtpr	r31, EV6__DTB_IA	; (7,1L) Flush DTB
                  [000780]  4259  	addq	r31, r31, r0		; nop
                  [000780]  4260  	addq	r31, r31, r0		; nop
                  [000780]  4261  ;
                  [000780]  4262  ; Create a stall outside the IQ until the mtpr EV6__ITB_IA retires.
                  [000780]  4263  ;
                  [000780]  4264  	hw_mtpr	r31, <EV6__MM_STAT ! ^x90>
                  [000780]  4265  	addq	r31, r31, r0		; nop
                  [000780]  4266  	addq	r31, r31, r0		; nop
                  [000780]  4267  	addq	r31, r31, r0		; nop
                  [000780]  4268  ;
                  [000780]  4269  ; We need 2 buffer fetch blocks to produce desired stalls..
                  [000780]  4270  ;
                  [000780]  4271  	addq	r31, r31, r0		; 1st buffer fetch block. IMAP stall.
                  [000780]  4272  	addq	r31, r31, r0		; nop
                  [000780]  4273  	addq	r31, r31, r0		; nop
                  [000780]  4274  	addq	r31, r31, r0		; nop
                  [000780]  4275  
                  [000780]  4276  	addq	r31, r31, r0		; 2nd buffer fetch block. FMAP stall.
                  [000780]  4277  	addq	r31, r31, r0		; nop
                  [000780]  4278  	addq	r31, r31, r0		; nop
                  [000780]  4279  	addq	r31, r31, r0		; nop
                  [000780]  4280  
                  [000780]  4281  ;+
                  [000780]  4282  ; Now we must map the shadow registers.
                  [000780]  4283  ;
                  [000780]  4284  ; Current state:
                  [000780]  4285  ;	retirator initialized
                  [000780]  4286  ;	destinations mapped
                  [000780]  4287  ;	source mapping enabled
                  [000780]  4288  ;	itb, dtb flushed
                  [000780]  4289  ;
                  [000780]  4290  ; We need to ensure we are in the icache so we don't fetch junk that touches
                  [000780]  4291  ; the shadow sources before we write the destinations.
                  [000780]  4292  ;-
                  [000780]  4293  
                  [000780]  4294  EV6__I_CTL__SHADOW_INIT = -
                  [000780]  4295  	<<3@EV6__I_CTL__IC_EN__S> ! -
                  [000780]  4296  	 <2@EV6__I_CTL__SDE__S> ! -
                  [000780]  4297  	 <1@EV6__I_CTL__CALL_PAL_R23__S>>
                  [000780]  4298  
                  [000780]  4299  	GET_32CONS	r2, EV6__I_CTL__SHADOW_INIT, r31
                  [000780]  4300  	br	r31, trap__wakeup__touch0	; fetch in next block
                  [000780]  4301  
                  [000780]  4302  	ALIGN_FETCH_BLOCK <^x43FF0400>		; pad with addq r31, r31, r0
                  [000780]  4303  
                  [000780]  4304  trap__wakeup__next0:				;
                  [000780]  4305  	hw_mtpr	r2, EV6__I_CTL			; (4,0L) write I_CTL
                  [000780]  4306  	addq	r31, r31, r0			; nop
                  [000780]  4307  	br	r31, trap__wakeup__next1	; continue in next block
                  [000780]  4308  trap__wakeup__touch0:				;
                  [000780]  4309  	br	r31, trap__wakeup__touch1	; fetch next block
                  [000780]  4310  
                  [000780]  4311  trap__wakeup__next1:				;
                  [000780]  4312  	hw_mtpr	r31, <EV6__MM_STAT ! ^x10>	; (4,0L) stall outside IQ
                  [000780]  4313  	addq	r31, r31, r0			; nop
                  [000780]  4314  	br	r31, trap__wakeup__next2	; continue in next block
                  [000780]  4315  trap__wakeup__touch1:				;
                  [000780]  4316  	br	r31, trap__wakeup__touch2	; fetch next block
                  [000780]  4317  ;
                  [000780]  4318  ; We need 3 buffer fetch blocks to get the correct SDE bit for the
                  [000780]  4319  ; next fetch block. One for IMAP stall, one for FMAP stall, one more to allow
                  [000780]  4320  ; for the retire to proprogate for the fetch.
                  [000780]  4321  ;
                  [000780]  4322  trap__wakeup__next2:				;
                  [000780]  4323  	addq	r31, r31, r0			; 1st block. IMAP stall.
                  [000780]  4324  	addq	r31, r31, r0			; nop
                  [000780]  4325  	br	r31, trap__wakeup__next3	; continue in next block
                  [000780]  4326  trap__wakeup__touch2:				;
                  [000780]  4327  	br	r31, trap__wakeup__touch3	; fetch next block
                  [000780]  4328  
                  [000780]  4329  trap__wakeup__next3:				;
                  [000780]  4330  	addq	r31, r31, r0			; 2nd block. FMAP stall.
                  [000780]  4331  	addq	r31, r31, r0			; nop
                  [000780]  4332  	br	r31, trap__wakeup__next4	; continue in next block
                  [000780]  4333  trap__wakeup__touch3:				;
                  [000780]  4334  	br	r31, trap__wakeup__touch4	; fetch next block
                  [000780]  4335  
                  [000780]  4336  trap__wakeup__next4:				;
                  [000780]  4337  	addq	r31, r31, r0			; 3rd block. Propagate.
                  [000780]  4338  	addq	r31, r31, r0			; nop
                  [000780]  4339  	br	r31, trap__wakeup__next5	; continue in next block
                  [000780]  4340  trap__wakeup__touch4:				;
                  [000780]  4341  	br	r31, trap__wakeup__touch5	; fetch next block
                  [000780]  4342  ;
                  [000780]  4343  ; Now map the shadow registers
                  [000780]  4344  ;
                  [000780]  4345  trap__wakeup__next5:				;
                  [000780]  4346  	addq	r31, r31, r4			; map r4
                  [000780]  4347  	addq	r31, r31, r5			; mapr r5
                  [000780]  4348  	br	r31, trap__wakeup__next6	; continue in next block
                  [000780]  4349  trap__wakeup__touch5:				;
                  [000780]  4350  	br	r31, trap__wakeup__touch6	; fetch next block
                  [000780]  4351  
                  [000780]  4352  trap__wakeup__next6:				;
                  [000780]  4353  	addq	r31, r31, r6			; map r6
                  [000780]  4354  	addq	r31, r31, r7			; map r7
                  [000780]  4355  	br	r31, trap__wakeup__next7	; continue in next block
                  [000780]  4356  trap__wakeup__touch6:				;
                  [000780]  4357  	br	r31, trap__wakeup__touch7	; fetch next block
                  [000780]  4358  
                  [000780]  4359  trap__wakeup__next7:				;
                  [000780]  4360  	addq	r31, r31, r20			; map r20
                  [000780]  4361  	addq	r31, r31, r21			; map r21
                  [000780]  4362  	br	r31, trap__wakeup__next8	; continue in next block
                  [000780]  4363  trap__wakeup__touch7:				;
                  [000780]  4364  	br	r31, trap__wakeup__touch8	; fetch next block
                  [000780]  4365  
                  [000780]  4366  trap__wakeup__next8:				;
                  [000780]  4367  	addq	r31, r31, r22			; map r22
                  [000780]  4368  	addq	r31, r31, r23			; map r23
                  [000780]  4369  	br	r31, trap__wakeup__sde_done	; done
                  [000780]  4370  trap__wakeup__touch8:				;
                  [000780]  4371  	br	r31, trap__wakeup__next0	; go back and start executing
                  [000780]  4372  
                  [000780]  4373  trap__wakeup__sde_done:
                  [000780]  4374  	br	r31, sys__wakeup		; continue in system code
                  [000780]  4375  
                  [000780]  4376  .endc
                  [000780]  4221I 
                  [000780]  4222I     i = 0
                  [000780]  4223I     .repeat 15
                  [000780]  4224I 	addq	r31, r31, i
                  [000780]  4225I 	addq	r31, r31, <i+1>
                  [000780]  4226I 	.if eq <ev6_p1>
                  [000780]  4227I 	addt	f31, f31, i
                  [000780]  4228I 	mult	f31, f31, <i+1>
                  [000780]  4229I 	.iff
                  [000780]  4230I 	addq	r31, r31, i
                  [000780]  4231I 	addq	r31, r31, <i+1>
                  [000780]  4232I 	.endc
                  [000780]  4233I 	i = i+2
                  [000780]  4234I     .endr
         43FF0400 [000780]  4224R 	addq	r31, r31, i
         43FF0401 [000784]  4225R 	addq	r31, r31, <i+1>
         5BFF1400 [000788]  4227I 	addt	f31, f31, i
         5BFF1441 [00078C]  4228I 	mult	f31, f31, <i+1>
         43FF0402 [000790]  4224R     	addq	r31, r31, i
         43FF0403 [000794]  4225R 	addq	r31, r31, <i+1>
         5BFF1402 [000798]  4227I 	addt	f31, f31, i
         5BFF1443 [00079C]  4228I 	mult	f31, f31, <i+1>
         43FF0404 [0007A0]  4224R     	addq	r31, r31, i
         43FF0405 [0007A4]  4225R 	addq	r31, r31, <i+1>
         5BFF1404 [0007A8]  4227I 	addt	f31, f31, i
         5BFF1445 [0007AC]  4228I 	mult	f31, f31, <i+1>
         43FF0406 [0007B0]  4224R     	addq	r31, r31, i
         43FF0407 [0007B4]  4225R 	addq	r31, r31, <i+1>
         5BFF1406 [0007B8]  4227I 	addt	f31, f31, i
         5BFF1447 [0007BC]  4228I 	mult	f31, f31, <i+1>
         43FF0408 [0007C0]  4224R     	addq	r31, r31, i
         43FF0409 [0007C4]  4225R 	addq	r31, r31, <i+1>
         5BFF1408 [0007C8]  4227I 	addt	f31, f31, i
         5BFF1449 [0007CC]  4228I 	mult	f31, f31, <i+1>
         43FF040A [0007D0]  4224R     	addq	r31, r31, i
         43FF040B [0007D4]  4225R 	addq	r31, r31, <i+1>
         5BFF140A [0007D8]  4227I 	addt	f31, f31, i
         5BFF144B [0007DC]  4228I 	mult	f31, f31, <i+1>
         43FF040C [0007E0]  4224R     	addq	r31, r31, i
         43FF040D [0007E4]  4225R 	addq	r31, r31, <i+1>
         5BFF140C [0007E8]  4227I 	addt	f31, f31, i
         5BFF144D [0007EC]  4228I 	mult	f31, f31, <i+1>
         43FF040E [0007F0]  4224R     	addq	r31, r31, i
         43FF040F [0007F4]  4225R 	addq	r31, r31, <i+1>
         5BFF140E [0007F8]  4227I 	addt	f31, f31, i
         5BFF144F [0007FC]  4228I 	mult	f31, f31, <i+1>
         43FF0410 [000800]  4224R     	addq	r31, r31, i
         43FF0411 [000804]  4225R 	addq	r31, r31, <i+1>
         5BFF1410 [000808]  4227I 	addt	f31, f31, i
         5BFF1451 [00080C]  4228I 	mult	f31, f31, <i+1>
         43FF0412 [000810]  4224R     	addq	r31, r31, i
         43FF0413 [000814]  4225R 	addq	r31, r31, <i+1>
         5BFF1412 [000818]  4227I 	addt	f31, f31, i
         5BFF1453 [00081C]  4228I 	mult	f31, f31, <i+1>
         43FF0414 [000820]  4224R     	addq	r31, r31, i
         43FF0415 [000824]  4225R 	addq	r31, r31, <i+1>
         5BFF1414 [000828]  4227I 	addt	f31, f31, i
         5BFF1455 [00082C]  4228I 	mult	f31, f31, <i+1>
         43FF0416 [000830]  4224R     	addq	r31, r31, i
         43FF0417 [000834]  4225R 	addq	r31, r31, <i+1>
         5BFF1416 [000838]  4227I 	addt	f31, f31, i
         5BFF1457 [00083C]  4228I 	mult	f31, f31, <i+1>
         43FF0418 [000840]  4224R     	addq	r31, r31, i
         43FF0419 [000844]  4225R 	addq	r31, r31, <i+1>
         5BFF1418 [000848]  4227I 	addt	f31, f31, i
         5BFF1459 [00084C]  4228I 	mult	f31, f31, <i+1>
         43FF041A [000850]  4224R     	addq	r31, r31, i
         43FF041B [000854]  4225R 	addq	r31, r31, <i+1>
         5BFF141A [000858]  4227I 	addt	f31, f31, i
         5BFF145B [00085C]  4228I 	mult	f31, f31, <i+1>
         43FF041C [000860]  4224R     	addq	r31, r31, i
         43FF041D [000864]  4225R 	addq	r31, r31, <i+1>
         5BFF141C [000868]  4227I 	addt	f31, f31, i
         5BFF145D [00086C]  4228I 	mult	f31, f31, <i+1>
                  [000870]  4235I     
         43FF041E [000870]  4236I 	addq	r31, r31, r30
                  [000874]  4237I     .if eq <ev6_p1>
                  [000874]  4238I 	addt	f31, f31, f30
                  [000874]  4239I     .iff
                  [000874]  4240I 	addq	r31, r31, r30
                  [000874]  4241I     .endc
         5BFF141E [000874]  4238I 	addt	f31, f31, f30
         43FF0400 [000878]  4242I     	addq	r31, r31, r0
         43FF0400 [00087C]  4243I 	addq	r31, r31, r0
                  [000880]  4244I 
                  [000880]  4245I     .repeat 4
                  [000880]  4246I 	addq	r31, r31, r0
                  [000880]  4247I 	addq	r31, r31, r0
                  [000880]  4248I 	addq	r31, r31, r0
                  [000880]  4249I 	addq	r31, r31, r0
                  [000880]  4250I     .endr
         43FF0400 [000880]  4246R 	addq	r31, r31, r0
         43FF0400 [000884]  4247R 	addq	r31, r31, r0
         43FF0400 [000888]  4248R 	addq	r31, r31, r0
         43FF0400 [00088C]  4249R 	addq	r31, r31, r0
         43FF0400 [000890]  4246R     	addq	r31, r31, r0
         43FF0400 [000894]  4247R 	addq	r31, r31, r0
         43FF0400 [000898]  4248R 	addq	r31, r31, r0
         43FF0400 [00089C]  4249R 	addq	r31, r31, r0
         43FF0400 [0008A0]  4246R     	addq	r31, r31, r0
         43FF0400 [0008A4]  4247R 	addq	r31, r31, r0
         43FF0400 [0008A8]  4248R 	addq	r31, r31, r0
         43FF0400 [0008AC]  4249R 	addq	r31, r31, r0
         43FF0400 [0008B0]  4246R     	addq	r31, r31, r0
         43FF0400 [0008B4]  4247R 	addq	r31, r31, r0
         43FF0400 [0008B8]  4248R 	addq	r31, r31, r0
         43FF0400 [0008BC]  4249R 	addq	r31, r31, r0
                  [0008C0]  4251I     
                  [0008C0]  4252I ;
                  [0008C0]  4253I ; Now turn on mapper source enables.
                  [0008C0]  4254I ;
                  [0008C0]  4255I 	ASSUME_FETCH_BLOCK
                  [0008C0]  4256I 
         77FF0310 [0008C0]  4257I 	hw_mtpr	r31, EV6__ITB_IA	; (4,0L) Flush ITB, enable source map
         77FFA380 [0008C4]  4258I 	hw_mtpr	r31, EV6__DTB_IA	; (7,1L) Flush DTB
         43FF0400 [0008C8]  4259I 	addq	r31, r31, r0		; nop
         43FF0400 [0008CC]  4260I 	addq	r31, r31, r0		; nop
                  [0008D0]  4261I ;
                  [0008D0]  4262I ; Create a stall outside the IQ until the mtpr EV6__ITB_IA retires.
                  [0008D0]  4263I ;
         77FF2790 [0008D0]  4264I 	hw_mtpr	r31, <EV6__MM_STAT ! ^x90>
         43FF0400 [0008D4]  4265I 	addq	r31, r31, r0		; nop
         43FF0400 [0008D8]  4266I 	addq	r31, r31, r0		; nop
         43FF0400 [0008DC]  4267I 	addq	r31, r31, r0		; nop
                  [0008E0]  4268I ;
                  [0008E0]  4269I ; We need 2 buffer fetch blocks to produce desired stalls..
                  [0008E0]  4270I ;
         43FF0400 [0008E0]  4271I 	addq	r31, r31, r0		; 1st buffer fetch block. IMAP stall.
         43FF0400 [0008E4]  4272I 	addq	r31, r31, r0		; nop
         43FF0400 [0008E8]  4273I 	addq	r31, r31, r0		; nop
         43FF0400 [0008EC]  4274I 	addq	r31, r31, r0		; nop
                  [0008F0]  4275I 
         43FF0400 [0008F0]  4276I 	addq	r31, r31, r0		; 2nd buffer fetch block. FMAP stall.
         43FF0400 [0008F4]  4277I 	addq	r31, r31, r0		; nop
         43FF0400 [0008F8]  4278I 	addq	r31, r31, r0		; nop
         43FF0400 [0008FC]  4279I 	addq	r31, r31, r0		; nop
                  [000900]  4280I 
                  [000900]  4281I ;+
                  [000900]  4282I ; Now we must map the shadow registers.
                  [000900]  4283I ;
                  [000900]  4284I ; Current state:
                  [000900]  4285I ;	retirator initialized
                  [000900]  4286I ;	destinations mapped
                  [000900]  4287I ;	source mapping enabled
                  [000900]  4288I ;	itb, dtb flushed
                  [000900]  4289I ;
                  [000900]  4290I ; We need to ensure we are in the icache so we don't fetch junk that touches
                  [000900]  4291I ; the shadow sources before we write the destinations.
                  [000900]  4292I ;-
                  [000900]  4293I 
                  [000900]  4294I EV6__I_CTL__SHADOW_INIT = -
                  [000900]  4295I 	<<3@EV6__I_CTL__IC_EN__S> ! -
                  [000900]  4296I 	 <2@EV6__I_CTL__SDE__S> ! -
                  [000900]  4297I 	 <1@EV6__I_CTL__CALL_PAL_R23__S>>
                  [000900]  4298I 
                  [000900]  4299I 	GET_32CONS	r2, EV6__I_CTL__SHADOW_INIT, r31
File: ev6_pal_macros.mar
                  [000900]   239i  ASSUME <ev6__i_ctl__shadow_init> le  <^x7FFFFFFF>
         245F0010 [000900]   240i 	ldah	r2,<<ev6__i_ctl__shadow_init>+32768>@-16(r31); + xxx<31:16>
         20420086 [000904]   241i 	lda	r2,<<ev6__i_ctl__shadow_init> & ^XFFFF>(r2) ; r31+xxx<15:0>
File: ev6_osf_pal.mar
         C3E00004 [000908]  4300I 	br	r31, trap__wakeup__touch0	; fetch in next block
                  [00090C]  4301I 
                  [00090C]  4302I 	ALIGN_FETCH_BLOCK <^x43FF0400>		; pad with addq r31, r31, r0
File: ev6_pal_macros.mar
         43FF0400 [00090C]   265i 	.align 4, <^x43FF0400>
File: ev6_osf_pal.mar
                  [000910]  4303I 
                  [000910]  4304I trap__wakeup__next0:				;
         77E21110 [000910]  4305I 	hw_mtpr	r2, EV6__I_CTL			; (4,0L) write I_CTL
         43FF0400 [000914]  4306I 	addq	r31, r31, r0			; nop
         C3E00001 [000918]  4307I 	br	r31, trap__wakeup__next1	; continue in next block
                  [00091C]  4308I trap__wakeup__touch0:				;
         C3E00003 [00091C]  4309I 	br	r31, trap__wakeup__touch1	; fetch next block
                  [000920]  4310I 
                  [000920]  4311I trap__wakeup__next1:				;
         77FF2710 [000920]  4312I 	hw_mtpr	r31, <EV6__MM_STAT ! ^x10>	; (4,0L) stall outside IQ
         43FF0400 [000924]  4313I 	addq	r31, r31, r0			; nop
         C3E00001 [000928]  4314I 	br	r31, trap__wakeup__next2	; continue in next block
                  [00092C]  4315I trap__wakeup__touch1:				;
         C3E00003 [00092C]  4316I 	br	r31, trap__wakeup__touch2	; fetch next block
                  [000930]  4317I ;
                  [000930]  4318I ; We need 3 buffer fetch blocks to get the correct SDE bit for the
                  [000930]  4319I ; next fetch block. One for IMAP stall, one for FMAP stall, one more to allow
                  [000930]  4320I ; for the retire to proprogate for the fetch.
                  [000930]  4321I ;
                  [000930]  4322I trap__wakeup__next2:				;
         43FF0400 [000930]  4323I 	addq	r31, r31, r0			; 1st block. IMAP stall.
         43FF0400 [000934]  4324I 	addq	r31, r31, r0			; nop
         C3E00001 [000938]  4325I 	br	r31, trap__wakeup__next3	; continue in next block
                  [00093C]  4326I trap__wakeup__touch2:				;
         C3E00003 [00093C]  4327I 	br	r31, trap__wakeup__touch3	; fetch next block
                  [000940]  4328I 
                  [000940]  4329I trap__wakeup__next3:				;
         43FF0400 [000940]  4330I 	addq	r31, r31, r0			; 2nd block. FMAP stall.
         43FF0400 [000944]  4331I 	addq	r31, r31, r0			; nop
         C3E00001 [000948]  4332I 	br	r31, trap__wakeup__next4	; continue in next block
                  [00094C]  4333I trap__wakeup__touch3:				;
         C3E00003 [00094C]  4334I 	br	r31, trap__wakeup__touch4	; fetch next block
                  [000950]  4335I 
                  [000950]  4336I trap__wakeup__next4:				;
         43FF0400 [000950]  4337I 	addq	r31, r31, r0			; 3rd block. Propagate.
         43FF0400 [000954]  4338I 	addq	r31, r31, r0			; nop
         C3E00001 [000958]  4339I 	br	r31, trap__wakeup__next5	; continue in next block
                  [00095C]  4340I trap__wakeup__touch4:				;
         C3E00003 [00095C]  4341I 	br	r31, trap__wakeup__touch5	; fetch next block
                  [000960]  4342I ;
                  [000960]  4343I ; Now map the shadow registers
                  [000960]  4344I ;
                  [000960]  4345I trap__wakeup__next5:				;
         43FF0404 [000960]  4346I 	addq	r31, r31, r4			; map r4
         43FF0405 [000964]  4347I 	addq	r31, r31, r5			; mapr r5
         C3E00001 [000968]  4348I 	br	r31, trap__wakeup__next6	; continue in next block
                  [00096C]  4349I trap__wakeup__touch5:				;
         C3E00003 [00096C]  4350I 	br	r31, trap__wakeup__touch6	; fetch next block
                  [000970]  4351I 
                  [000970]  4352I trap__wakeup__next6:				;
         43FF0406 [000970]  4353I 	addq	r31, r31, r6			; map r6
         43FF0407 [000974]  4354I 	addq	r31, r31, r7			; map r7
         C3E00001 [000978]  4355I 	br	r31, trap__wakeup__next7	; continue in next block
                  [00097C]  4356I trap__wakeup__touch6:				;
         C3E00003 [00097C]  4357I 	br	r31, trap__wakeup__touch7	; fetch next block
                  [000980]  4358I 
                  [000980]  4359I trap__wakeup__next7:				;
         43FF0414 [000980]  4360I 	addq	r31, r31, r20			; map r20
         43FF0415 [000984]  4361I 	addq	r31, r31, r21			; map r21
         C3E00001 [000988]  4362I 	br	r31, trap__wakeup__next8	; continue in next block
                  [00098C]  4363I trap__wakeup__touch7:				;
         C3E00003 [00098C]  4364I 	br	r31, trap__wakeup__touch8	; fetch next block
                  [000990]  4365I 
                  [000990]  4366I trap__wakeup__next8:				;
         43FF0416 [000990]  4367I 	addq	r31, r31, r22			; map r22
         43FF0417 [000994]  4368I 	addq	r31, r31, r23			; map r23
         C3E00001 [000998]  4369I 	br	r31, trap__wakeup__sde_done	; done
                  [00099C]  4370I trap__wakeup__touch8:				;
         C3FFFFDC [00099C]  4371I 	br	r31, trap__wakeup__next0	; go back and start executing
                  [0009A0]  4372I 
                  [0009A0]  4373I trap__wakeup__sde_done:
         C3E01857 [0009A0]  4374I 	br	r31, sys__wakeup		; continue in system code
                  [0009A4]  4375I 
                  [0009A4]  4377  
                  [0009A4]  4378  	END_HW_VECTOR <^xC00 - TRAP__WAKEUP>
File: ev6_pal_macros.mar
                  [0009A4]    57i         ASSUME <.-_start_of_last_vec> le <^xC00 - TRAP__WAKEUP>
                  [0009A4]    61M         GOTO_FREE_CODE
                  [004780]    67M     .align 6
File: ev6_osf_pal.mar
                  [004780]  4379  
                  [004780]  4380  ;+
                  [004780]  4381  ; Other routines
                  [004780]  4382  ;-
                  [004780]  4383  	GOTO_FREE_CODE
File: ev6_pal_macros.mar
                  [004780]    67M     .align 6
File: ev6_osf_pal.mar
                  [004780]  4384  
                  [004780]  4385  ;+
                  [004780]  4386  ; trap__update_pcb_and_halt
                  [004780]  4387  ;
                  [004780]  4388  ; Entry:
                  [004780]  4389  ;	Branched to on halt conditions.
                  [004780]  4390  ;
                  [004780]  4391  ; Function:
                  [004780]  4392  ;	Update PCB and branch to sys__enter_console.
                  [004780]  4393  ;
                  [004780]  4394  ; Current state:
                  [004780]  4395  ;	p20		halt code
                  [004780]  4396  ;	p23		offending pc
                  [004780]  4397  ;
                  [004780]  4398  ;	PT__HALT_CODE	halt code
                  [004780]  4399  ;-
                  [004780]  4400  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
                  [004780]   275i 	.align 6
File: ev6_osf_pal.mar
                  [004780]  4401  trap__update_pcb_and_halt:
         6C951010 [004780]  4402  	hw_ldq/p p4, PT__PCBB(p_temp)			; get pcbb
         46C11007 [004784]  4403  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p7	; current mode
         F4E00002 [004788]  4404  	bne	p7, trap__update_pcb_from_user		; branch if user mode
                  [00478C]  4405  ;
                  [00478C]  4406  ; Fall through for kernel mode.
                  [00478C]  4407  ;
         7FC41000 [00478C]  4408  	hw_stq/p r30, OSF_PCB__KSP(p4)			; update PCB location
         C3E00002 [004790]  4409  	br	r31, trap__update_pcb_and_halt_cpc
                  [004794]  4410  ;
                  [004794]  4411  ; Updating from user mode.
                  [004794]  4412  ;
                  [004794]  4413  trap__update_pcb_from_user:
         7FD51020 [004794]  4414  	hw_stq/p r30, PT__USP(p_temp)		; update pt__usp
         7FC41008 [004798]  4415  	hw_stq/p r30, OSF_PCB__USP(p4)		; update PCB location
                  [00479C]  4416  ;
                  [00479C]  4417  ; Merge to update cpc.
                  [00479C]  4418  ;
                  [00479C]  4419  trap__update_pcb_and_halt_cpc:
         60BFC000 [00479C]  4420  	rpcc	p5				; get cycle counter
         48A41686 [0047A0]  4421  	srl	p5, #32, p6			; shift offset in cc<63:32>
         40A60006 [0047A4]  4422  	addl	p5, p6, p6			; cc<31:0> + cc<63:32>
         7CC40018 [0047A8]  4423  	hw_stl/p p6, OSF_PCB__CPC(p4)		; store cc
                  [0047AC]  4424  
         C3E00774 [0047AC]  4425  	br	r31, sys__enter_console
                  [0047B0]  4426  
                  [0047B0]  4427  
                  [0047B0]  4428  ;+
                  [0047B0]  4429  ; pal__save_state
                  [0047B0]  4430  ;
                  [0047B0]  4431  ; The shadow registers, except of course p_misc and p_temp, are pretty much
                  [0047B0]  4432  ; scratch, so we don't worry about stepping on them.
                  [0047B0]  4433  ;
                  [0047B0]  4434  ; Current state:
                  [0047B0]  4435  ;	p7		return address
                  [0047B0]  4436  ;	p20		halt code
                  [0047B0]  4437  ;	p23		exc_addr
                  [0047B0]  4438  ;
                  [0047B0]  4439  ;	PT__HALT_CODE	halt code (do we need it there ??)
                  [0047B0]  4440  ;-
                  [0047B0]  4441  
                  [0047B0]  4442  EV6__I_CTL__SDE7__S = 7				; shadow mode bit
                  [0047B0]  4443  
                  [0047B0]  4444  	ALIGN_FETCH_BLOCK
File: ev6_pal_macros.mar
                  [0047B0]   267i 	.align 4
File: ev6_osf_pal.mar
                  [0047B0]  4445  
                  [0047B0]  4446  pal__save_state:
         6C951088 [0047B0]  4447  	hw_ldq/p p4, PT__IMPURE(p_temp)		; get base of impure area
         7FE41000 [0047B4]  4448  	hw_stq/p r31, CNS__FLAG(p4)		; clear dump flag
         7E841008 [0047B8]  4449  	hw_stq/p p20, CNS__HALT(p4)		; halt code
         47FF041F [0047BC]  4450  	bis	r31, r31, r31
                  [0047C0]  4451  
                  [0047C0]  4452  	STORE_REG 0, irn=p4			; save r0
File: ev6_pal_macros.mar
                  [0047C0]   463M     ASSUME <0+0+0> lt 2
         7C041010 [0047C0]   466i 	hw_stq/p r0, CNS__R0(p4)
File: ev6_osf_pal.mar
                  [0047C4]  4453  	STORE_REG 1, irn=p4			; save r1
File: ev6_pal_macros.mar
                  [0047C4]   463M     ASSUME <0+0+0> lt 2
         7C241018 [0047C4]   466i 	hw_stq/p r1, CNS__R1(p4)
File: ev6_osf_pal.mar
                  [0047C8]  4454  	STORE_REG 2, irn=p4			; save r2
File: ev6_pal_macros.mar
                  [0047C8]   463M     ASSUME <0+0+0> lt 2
         7C441020 [0047C8]   466i 	hw_stq/p r2, CNS__R2(p4)
File: ev6_osf_pal.mar
         641F1110 [0047CC]  4455  	hw_mfpr	r0, EV6__I_CTL			; (4,0L) get i_ctl
                  [0047D0]  4456  
         449F0401 [0047D0]  4457  	bis	p4, r31, r1			; base of impure area
         44101100 [0047D4]  4458  	bic	r0, #<1@EV6__I_CTL__SDE7__S>, r0; zap sde
                  [0047D8]  4459  	STORE_REG 3, irn=p4			; save r3
File: ev6_pal_macros.mar
                  [0047D8]   463M     ASSUME <0+0+0> lt 2
         7C641028 [0047D8]   466i 	hw_stq/p r3, CNS__R3(p4)
File: ev6_osf_pal.mar
                  [0047DC]  4460  	STORE_REG 8, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [0047DC]   463M     ASSUME <0+0+0> lt 2
         7D011050 [0047DC]   466i 	hw_stq/p r8, CNS__R8(r1)
File: ev6_osf_pal.mar
                  [0047E0]  4461  	
         77E01110 [0047E0]  4462  	hw_mtpr	r0, EV6__I_CTL			; (4,0L) write i_ctl
                  [0047E4]  4463  	STORE_REG 9, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [0047E4]   463M     ASSUME <0+0+0> lt 2
         7D211058 [0047E4]   466i 	hw_stq/p r9, CNS__R9(r1)
File: ev6_osf_pal.mar
                  [0047E8]  4464  	STORE_REG 10, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [0047E8]   463M     ASSUME <0+0+0> lt 2
         7D411060 [0047E8]   466i 	hw_stq/p r10, CNS__R10(r1)
File: ev6_osf_pal.mar
                  [0047EC]  4465  	STORE_REG 11, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [0047EC]   463M     ASSUME <0+0+0> lt 2
         7D611068 [0047EC]   466i 	hw_stq/p r11, CNS__R11(r1)
File: ev6_osf_pal.mar
                  [0047F0]  4466  
         77E01110 [0047F0]  4467  	hw_mtpr	r0, EV6__I_CTL			; (4,0L) stall outside IQ
                  [0047F4]  4468  	STORE_REG 12, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [0047F4]   463M     ASSUME <0+0+0> lt 2
         7D811070 [0047F4]   466i 	hw_stq/p r12, CNS__R12(r1)
File: ev6_osf_pal.mar
                  [0047F8]  4469  	STORE_REG 13, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [0047F8]   463M     ASSUME <0+0+0> lt 2
         7DA11078 [0047F8]   466i 	hw_stq/p r13, CNS__R13(r1)
File: ev6_osf_pal.mar
                  [0047FC]  4470  	STORE_REG 14, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [0047FC]   463M     ASSUME <0+0+0> lt 2
         7DC11080 [0047FC]   466i 	hw_stq/p r14, CNS__R14(r1)
File: ev6_osf_pal.mar
                  [004800]  4471  
                  [004800]  4472  	STORE_REG 15, irn=r1			; buffer block 1 -- save gpr
File: ev6_pal_macros.mar
                  [004800]   463M     ASSUME <0+0+0> lt 2
         7DE11088 [004800]   466i 	hw_stq/p r15, CNS__R15(r1)
File: ev6_osf_pal.mar
                  [004804]  4473  	STORE_REG 16, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [004804]   463M     ASSUME <0+0+0> lt 2
         7E011090 [004804]   466i 	hw_stq/p r16, CNS__R16(r1)
File: ev6_osf_pal.mar
                  [004808]  4474  	STORE_REG 17, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [004808]   463M     ASSUME <0+0+0> lt 2
         7E211098 [004808]   466i 	hw_stq/p r17, CNS__R17(r1)
File: ev6_osf_pal.mar
                  [00480C]  4475  	STORE_REG 18, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [00480C]   463M     ASSUME <0+0+0> lt 2
         7E4110A0 [00480C]   466i 	hw_stq/p r18, CNS__R18(r1)
File: ev6_osf_pal.mar
                  [004810]  4476  
                  [004810]  4477  	STORE_REG 19, irn=r1			; buffer block 2 --save gpr
File: ev6_pal_macros.mar
                  [004810]   463M     ASSUME <0+0+0> lt 2
         7E6110A8 [004810]   466i 	hw_stq/p r19, CNS__R19(r1)
File: ev6_osf_pal.mar
                  [004814]  4478  	STORE_REG 24, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [004814]   463M     ASSUME <0+0+0> lt 2
         7F0110D0 [004814]   466i 	hw_stq/p r24, CNS__R24(r1)
File: ev6_osf_pal.mar
                  [004818]  4479  	STORE_REG 25, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [004818]   463M     ASSUME <0+0+0> lt 2
         7F2110D8 [004818]   466i 	hw_stq/p r25, CNS__R25(r1)
File: ev6_osf_pal.mar
                  [00481C]  4480  	STORE_REG 26, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [00481C]   463M     ASSUME <0+0+0> lt 2
         7F4110E0 [00481C]   466i 	hw_stq/p r26, CNS__R26(r1)
File: ev6_osf_pal.mar
                  [004820]  4481  
                  [004820]  4482  	STORE_REG 27, irn=r1			; buffer block 3 --save gpr
File: ev6_pal_macros.mar
                  [004820]   463M     ASSUME <0+0+0> lt 2
         7F6110E8 [004820]   466i 	hw_stq/p r27, CNS__R27(r1)
File: ev6_osf_pal.mar
                  [004824]  4483  	STORE_REG 28, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [004824]   463M     ASSUME <0+0+0> lt 2
         7F8110F0 [004824]   466i 	hw_stq/p r28, CNS__R28(r1)
File: ev6_osf_pal.mar
                  [004828]  4484  	STORE_REG 29, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [004828]   463M     ASSUME <0+0+0> lt 2
         7FA110F8 [004828]   466i 	hw_stq/p r29, CNS__R29(r1)
File: ev6_osf_pal.mar
                  [00482C]  4485  	STORE_REG 30, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [00482C]   463M     ASSUME <0+0+0> lt 2
         7FC11100 [00482C]   466i 	hw_stq/p r30, CNS__R30(r1)
File: ev6_osf_pal.mar
                  [004830]  4486  
                  [004830]  4487  	STORE_REG 4, irn=r1			; now store the un-shadowed gprs
File: ev6_pal_macros.mar
                  [004830]   463M     ASSUME <0+0+0> lt 2
         7C811030 [004830]   466i 	hw_stq/p r4, CNS__R4(r1)
File: ev6_osf_pal.mar
                  [004834]  4488  	STORE_REG 5, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [004834]   463M     ASSUME <0+0+0> lt 2
         7CA11038 [004834]   466i 	hw_stq/p r5, CNS__R5(r1)
File: ev6_osf_pal.mar
                  [004838]  4489  	STORE_REG 6, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [004838]   463M     ASSUME <0+0+0> lt 2
         7CC11040 [004838]   466i 	hw_stq/p r6, CNS__R6(r1)
File: ev6_osf_pal.mar
                  [00483C]  4490  	STORE_REG 7, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [00483C]   463M     ASSUME <0+0+0> lt 2
         7CE11048 [00483C]   466i 	hw_stq/p r7, CNS__R7(r1)
File: ev6_osf_pal.mar
                  [004840]  4491  
                  [004840]  4492  	STORE_REG 20, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [004840]   463M     ASSUME <0+0+0> lt 2
         7E8110B0 [004840]   466i 	hw_stq/p r20, CNS__R20(r1)
File: ev6_osf_pal.mar
                  [004844]  4493  	STORE_REG 21, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [004844]   463M     ASSUME <0+0+0> lt 2
         7EA110B8 [004844]   466i 	hw_stq/p r21, CNS__R21(r1)
File: ev6_osf_pal.mar
                  [004848]  4494  	STORE_REG 22, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [004848]   463M     ASSUME <0+0+0> lt 2
         7EC110C0 [004848]   466i 	hw_stq/p r22, CNS__R22(r1)
File: ev6_osf_pal.mar
                  [00484C]  4495  	STORE_REG 23, irn=r1			; save gpr
File: ev6_pal_macros.mar
                  [00484C]   463M     ASSUME <0+0+0> lt 2
         7EE110C8 [00484C]   466i 	hw_stq/p r23, CNS__R23(r1)
File: ev6_osf_pal.mar
                  [004850]  4496  ;
                  [004850]  4497  ; Now turn shadow registers back on.
                  [004850]  4498  ;
         44101400 [004850]  4499  	bis	r0, #<1@EV6__I_CTL__SDE7__S>, r0; or in sde
         77E01110 [004854]  4500  	hw_mtpr	r0, EV6__I_CTL			; (4,0L) write i_ctl
         47FF041F [004858]  4501  	bis	r31, r31, r31
         47FF041F [00485C]  4502  	bis	r31, r31, r31
                  [004860]  4503  
         77E01110 [004860]  4504  	hw_mtpr	r0, EV6__I_CTL			; (4,0L) stall outside IQ
         47FF041F [004864]  4505  	bis	r31, r31, r31
         47FF041F [004868]  4506  	bis	r31, r31, r31
         47FF041F [00486C]  4507  	bis	r31, r31, r31
                  [004870]  4508  
         44000400 [004870]  4509  	bis	r0, r0, r0			; buffer block 1
         47FF041F [004874]  4510  	bis	r31, r31, r31
         47FF041F [004878]  4511  	bis	r31, r31, r31
         47FF041F [00487C]  4512  	bis	r31, r31, r31
                  [004880]  4513  
         44000400 [004880]  4514  	bis	r0, r0, r0			; buffer block 2
         47FF041F [004884]  4515  	bis	r31, r31, r31
         47FF041F [004888]  4516  	bis	r31, r31, r31
         47FF041F [00488C]  4517  	bis	r31, r31, r31
                  [004890]  4518  
         44000400 [004890]  4519  	bis	r0, r0, r0			; buffer block 3
         47FF041F [004894]  4520  	bis	r31, r31, r31
         47FF041F [004898]  4521  	bis	r31, r31, r31
         47FF041F [00489C]  4522  	bis	r31, r31, r31
                  [0048A0]  4523  ;
                  [0048A0]  4524  ; Now save pal shadows. Registers p_temp and p_misc are really the
                  [0048A0]  4525  ; only important ones.
                  [0048A0]  4526  ;
                  [0048A0]  4527  ; Current state:
                  [0048A0]  4528  ;	p4	base of impure area
                  [0048A0]  4529  ;
                  [0048A0]  4530  pal__save_shadow:
         7C8412D8 [0048A0]  4531  	hw_stq/p p4, CNS__P4(p4)
         7CA412E0 [0048A4]  4532  	hw_stq/p p5, CNS__P5(p4)
         7CC412E8 [0048A8]  4533  	hw_stq/p p6, CNS__P6(p4)
         7CE412F0 [0048AC]  4534  	hw_stq/p p7, CNS__P7(p4)
         7E8412F8 [0048B0]  4535  	hw_stq/p p20, CNS__P20(p4)
         7EA41300 [0048B4]  4536  	hw_stq/p p_temp, CNS__P_TEMP(p4)
         7EC41308 [0048B8]  4537  	hw_stq/p p_misc, CNS__P_MISC(p4)
         7EE41310 [0048BC]  4538  	hw_stq/p p23, CNS__P23(p4)
                  [0048C0]  4539  
                  [0048C0]  4540  .if eq ev6_p1				; no float in pass1
                  [0048C0]  4541  
                  [0048C0]  4542  ;
                  [0048C0]  4543  ; Now save the floating point registers and FPCR.
                  [0048C0]  4544  ; First make sure FEN is on.
                  [0048C0]  4545  ;
                  [0048C0]  4546  	GET_16CONS	r0, <1@EV6__PROCESS_CONTEXT__FPE__S>, r31
                  [0048C0]  4547  	hw_mtpr	r0, EV6__FPE			; (4,0L) write new fpe
                  [0048C0]  4548  
                  [0048C0]  4549  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align with nops
                  [0048C0]  4550  
                  [0048C0]  4551  	hw_mtpr	r0, EV6__FPE			; (4,0L) force retire
                  [0048C0]  4552  	bis	r31, r31, r31
                  [0048C0]  4553  	bis	r31, r31, r31
                  [0048C0]  4554  	bis	r31, r31, r31
                  [0048C0]  4555  
                  [0048C0]  4556  	bis	r0, r0, r0			; buffer block 1
                  [0048C0]  4557  	bis	r31, r31, r31
                  [0048C0]  4558  	bis	r31, r31, r31
                  [0048C0]  4559  	bis	r31, r31, r31
                  [0048C0]  4560  
                  [0048C0]  4561  	bis	r0, r0, r0			; buffer block 2
                  [0048C0]  4562  	bis	r31, r31, r31
                  [0048C0]  4563  	bis	r31, r31, r31
                  [0048C0]  4564  	bis	r31, r31, r31
                  [0048C0]  4565  
                  [0048C0]  4566  	bis	r0, r0, r0			; buffer block 3
                  [0048C0]  4567  	bis	r31, r31, r31
                  [0048C0]  4568  	bis	r31, r31, r31
                  [0048C0]  4569  	bis	r31, r31, r31
                  [0048C0]  4570  
                  [0048C0]  4571  	t = 0
                  [0048C0]  4572  	.repeat 32
                  [0048C0]  4573  	STORE_REG \t, srn=p5, irn=p4, fpu=1
                  [0048C0]  4574  	t=t+1
                  [0048C0]  4575  	.endr
                  [0048C0]  4576  
                  [0048C0]  4577  	mf_fpcr	f0				; get current FPCR
                  [0048C0]  4578  	ftoit	f0, p5				; convert to integer
                  [0048C0]  4579  	hw_stq/p p5, CNS__FPCR(p4)		; save
                  [0048C0]  4580  
                  [0048C0]  4581  .endc
                  [0048C0]  4541I 
                  [0048C0]  4542I ;
                  [0048C0]  4543I ; Now save the floating point registers and FPCR.
                  [0048C0]  4544I ; First make sure FEN is on.
                  [0048C0]  4545I ;
                  [0048C0]  4546I 	GET_16CONS	r0, <1@EV6__PROCESS_CONTEXT__FPE__S>, r31
File: ev6_pal_macros.mar
                  [0048C0]   249i 	ASSUME <<1@EV6__PROCESS_CONTEXT__FPE__S>> le  <^x7FFF>
         201F0004 [0048C0]   250i 	lda	r0,<1@EV6__PROCESS_CONTEXT__FPE__S>(r31) ; r31+xxx<15:0>
File: ev6_osf_pal.mar
         77E05010 [0048C4]  4547I 	hw_mtpr	r0, EV6__FPE			; (4,0L) write new fpe
                  [0048C8]  4548I 
                  [0048C8]  4549I 	ALIGN_FETCH_BLOCK <^x47FF041F>		; align with nops
File: ev6_pal_macros.mar
47FF041F 47FF041F [0048C8]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
                  [0048D0]  4550I 
         77E05010 [0048D0]  4551I 	hw_mtpr	r0, EV6__FPE			; (4,0L) force retire
         47FF041F [0048D4]  4552I 	bis	r31, r31, r31
         47FF041F [0048D8]  4553I 	bis	r31, r31, r31
         47FF041F [0048DC]  4554I 	bis	r31, r31, r31
                  [0048E0]  4555I 
         44000400 [0048E0]  4556I 	bis	r0, r0, r0			; buffer block 1
         47FF041F [0048E4]  4557I 	bis	r31, r31, r31
         47FF041F [0048E8]  4558I 	bis	r31, r31, r31
         47FF041F [0048EC]  4559I 	bis	r31, r31, r31
                  [0048F0]  4560I 
         44000400 [0048F0]  4561I 	bis	r0, r0, r0			; buffer block 2
         47FF041F [0048F4]  4562I 	bis	r31, r31, r31
         47FF041F [0048F8]  4563I 	bis	r31, r31, r31
         47FF041F [0048FC]  4564I 	bis	r31, r31, r31
                  [004900]  4565I 
         44000400 [004900]  4566I 	bis	r0, r0, r0			; buffer block 3
         47FF041F [004904]  4567I 	bis	r31, r31, r31
         47FF041F [004908]  4568I 	bis	r31, r31, r31
         47FF041F [00490C]  4569I 	bis	r31, r31, r31
                  [004910]  4570I 
                  [004910]  4571I 	t = 0
                  [004910]  4572I 	.repeat 32
                  [004910]  4573I 	STORE_REG \t, srn=p5, irn=p4, fpu=1
                  [004910]  4574I 	t=t+1
                  [004910]  4575I 	.endr
                  [004910]  4573R 	STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004910]   463r     ASSUME <1+0+0> lt 2
         701F0E05 [004910]   470i 	ftoit	f0, p5
         7CA41110 [004914]   471i 	hw_stq/p p5, CNS__F0(p4)
File: ev6_osf_pal.mar
                  [004918]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004918]   463r     ASSUME <1+0+0> lt 2
         703F0E05 [004918]   470i 	ftoit	f1, p5
         7CA41118 [00491C]   471i 	hw_stq/p p5, CNS__F1(p4)
File: ev6_osf_pal.mar
                  [004920]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004920]   463r     ASSUME <1+0+0> lt 2
         705F0E05 [004920]   470i 	ftoit	f2, p5
         7CA41120 [004924]   471i 	hw_stq/p p5, CNS__F2(p4)
File: ev6_osf_pal.mar
                  [004928]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004928]   463r     ASSUME <1+0+0> lt 2
         707F0E05 [004928]   470i 	ftoit	f3, p5
         7CA41128 [00492C]   471i 	hw_stq/p p5, CNS__F3(p4)
File: ev6_osf_pal.mar
                  [004930]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004930]   463r     ASSUME <1+0+0> lt 2
         709F0E05 [004930]   470i 	ftoit	f4, p5
         7CA41130 [004934]   471i 	hw_stq/p p5, CNS__F4(p4)
File: ev6_osf_pal.mar
                  [004938]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004938]   463r     ASSUME <1+0+0> lt 2
         70BF0E05 [004938]   470i 	ftoit	f5, p5
         7CA41138 [00493C]   471i 	hw_stq/p p5, CNS__F5(p4)
File: ev6_osf_pal.mar
                  [004940]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004940]   463r     ASSUME <1+0+0> lt 2
         70DF0E05 [004940]   470i 	ftoit	f6, p5
         7CA41140 [004944]   471i 	hw_stq/p p5, CNS__F6(p4)
File: ev6_osf_pal.mar
                  [004948]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004948]   463r     ASSUME <1+0+0> lt 2
         70FF0E05 [004948]   470i 	ftoit	f7, p5
         7CA41148 [00494C]   471i 	hw_stq/p p5, CNS__F7(p4)
File: ev6_osf_pal.mar
                  [004950]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004950]   463r     ASSUME <1+0+0> lt 2
         711F0E05 [004950]   470i 	ftoit	f8, p5
         7CA41150 [004954]   471i 	hw_stq/p p5, CNS__F8(p4)
File: ev6_osf_pal.mar
                  [004958]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004958]   463r     ASSUME <1+0+0> lt 2
         713F0E05 [004958]   470i 	ftoit	f9, p5
         7CA41158 [00495C]   471i 	hw_stq/p p5, CNS__F9(p4)
File: ev6_osf_pal.mar
                  [004960]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004960]   463r     ASSUME <1+0+0> lt 2
         715F0E05 [004960]   470i 	ftoit	f10, p5
         7CA41160 [004964]   471i 	hw_stq/p p5, CNS__F10(p4)
File: ev6_osf_pal.mar
                  [004968]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004968]   463r     ASSUME <1+0+0> lt 2
         717F0E05 [004968]   470i 	ftoit	f11, p5
         7CA41168 [00496C]   471i 	hw_stq/p p5, CNS__F11(p4)
File: ev6_osf_pal.mar
                  [004970]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004970]   463r     ASSUME <1+0+0> lt 2
         719F0E05 [004970]   470i 	ftoit	f12, p5
         7CA41170 [004974]   471i 	hw_stq/p p5, CNS__F12(p4)
File: ev6_osf_pal.mar
                  [004978]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004978]   463r     ASSUME <1+0+0> lt 2
         71BF0E05 [004978]   470i 	ftoit	f13, p5
         7CA41178 [00497C]   471i 	hw_stq/p p5, CNS__F13(p4)
File: ev6_osf_pal.mar
                  [004980]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004980]   463r     ASSUME <1+0+0> lt 2
         71DF0E05 [004980]   470i 	ftoit	f14, p5
         7CA41180 [004984]   471i 	hw_stq/p p5, CNS__F14(p4)
File: ev6_osf_pal.mar
                  [004988]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004988]   463r     ASSUME <1+0+0> lt 2
         71FF0E05 [004988]   470i 	ftoit	f15, p5
         7CA41188 [00498C]   471i 	hw_stq/p p5, CNS__F15(p4)
File: ev6_osf_pal.mar
                  [004990]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004990]   463r     ASSUME <1+0+0> lt 2
         721F0E05 [004990]   470i 	ftoit	f16, p5
         7CA41190 [004994]   471i 	hw_stq/p p5, CNS__F16(p4)
File: ev6_osf_pal.mar
                  [004998]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004998]   463r     ASSUME <1+0+0> lt 2
         723F0E05 [004998]   470i 	ftoit	f17, p5
         7CA41198 [00499C]   471i 	hw_stq/p p5, CNS__F17(p4)
File: ev6_osf_pal.mar
                  [0049A0]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049A0]   463r     ASSUME <1+0+0> lt 2
         725F0E05 [0049A0]   470i 	ftoit	f18, p5
         7CA411A0 [0049A4]   471i 	hw_stq/p p5, CNS__F18(p4)
File: ev6_osf_pal.mar
                  [0049A8]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049A8]   463r     ASSUME <1+0+0> lt 2
         727F0E05 [0049A8]   470i 	ftoit	f19, p5
         7CA411A8 [0049AC]   471i 	hw_stq/p p5, CNS__F19(p4)
File: ev6_osf_pal.mar
                  [0049B0]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049B0]   463r     ASSUME <1+0+0> lt 2
         729F0E05 [0049B0]   470i 	ftoit	f20, p5
         7CA411B0 [0049B4]   471i 	hw_stq/p p5, CNS__F20(p4)
File: ev6_osf_pal.mar
                  [0049B8]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049B8]   463r     ASSUME <1+0+0> lt 2
         72BF0E05 [0049B8]   470i 	ftoit	f21, p5
         7CA411B8 [0049BC]   471i 	hw_stq/p p5, CNS__F21(p4)
File: ev6_osf_pal.mar
                  [0049C0]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049C0]   463r     ASSUME <1+0+0> lt 2
         72DF0E05 [0049C0]   470i 	ftoit	f22, p5
         7CA411C0 [0049C4]   471i 	hw_stq/p p5, CNS__F22(p4)
File: ev6_osf_pal.mar
                  [0049C8]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049C8]   463r     ASSUME <1+0+0> lt 2
         72FF0E05 [0049C8]   470i 	ftoit	f23, p5
         7CA411C8 [0049CC]   471i 	hw_stq/p p5, CNS__F23(p4)
File: ev6_osf_pal.mar
                  [0049D0]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049D0]   463r     ASSUME <1+0+0> lt 2
         731F0E05 [0049D0]   470i 	ftoit	f24, p5
         7CA411D0 [0049D4]   471i 	hw_stq/p p5, CNS__F24(p4)
File: ev6_osf_pal.mar
                  [0049D8]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049D8]   463r     ASSUME <1+0+0> lt 2
         733F0E05 [0049D8]   470i 	ftoit	f25, p5
         7CA411D8 [0049DC]   471i 	hw_stq/p p5, CNS__F25(p4)
File: ev6_osf_pal.mar
                  [0049E0]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049E0]   463r     ASSUME <1+0+0> lt 2
         735F0E05 [0049E0]   470i 	ftoit	f26, p5
         7CA411E0 [0049E4]   471i 	hw_stq/p p5, CNS__F26(p4)
File: ev6_osf_pal.mar
                  [0049E8]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049E8]   463r     ASSUME <1+0+0> lt 2
         737F0E05 [0049E8]   470i 	ftoit	f27, p5
         7CA411E8 [0049EC]   471i 	hw_stq/p p5, CNS__F27(p4)
File: ev6_osf_pal.mar
                  [0049F0]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049F0]   463r     ASSUME <1+0+0> lt 2
         739F0E05 [0049F0]   470i 	ftoit	f28, p5
         7CA411F0 [0049F4]   471i 	hw_stq/p p5, CNS__F28(p4)
File: ev6_osf_pal.mar
                  [0049F8]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [0049F8]   463r     ASSUME <1+0+0> lt 2
         73BF0E05 [0049F8]   470i 	ftoit	f29, p5
         7CA411F8 [0049FC]   471i 	hw_stq/p p5, CNS__F29(p4)
File: ev6_osf_pal.mar
                  [004A00]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004A00]   463r     ASSUME <1+0+0> lt 2
         73DF0E05 [004A00]   470i 	ftoit	f30, p5
         7CA41200 [004A04]   471i 	hw_stq/p p5, CNS__F30(p4)
File: ev6_osf_pal.mar
                  [004A08]  4573R 		STORE_REG \t, srn=p5, irn=p4, fpu=1
File: ev6_pal_macros.mar
                  [004A08]   463r     ASSUME <1+0+0> lt 2
         73FF0E05 [004A08]   470i 	ftoit	f31, p5
         7CA41208 [004A0C]   471i 	hw_stq/p p5, CNS__F31(p4)
File: ev6_osf_pal.mar
                  [004A10]  4576I 	
         5C0004A0 [004A10]  4577I 	mf_fpcr	f0				; get current FPCR
         701F0E05 [004A14]  4578I 	ftoit	f0, p5				; convert to integer
         7CA41318 [004A18]  4579I 	hw_stq/p p5, CNS__FPCR(p4)		; save
                  [004A1C]  4580I 
                  [004A1C]  4582  
                  [004A1C]  4583  ;
                  [004A1C]  4584  ; Now save the important PALtemps
                  [004A1C]  4585  ;
                  [004A1C]  4586  	STORE_REG <IMPURE>, srn=p5, irn=p4, pal=1
File: ev6_pal_macros.mar
                  [004A1C]   463M     ASSUME <0+1+0> lt 2
         6CB51088 [004A1C]   475i 	hw_ldq/p p5, PT__IMPURE(p_temp)
         7CA41218 [004A20]   476i 	hw_stq/p p5, CNS__IMPURE(p4)
File: ev6_osf_pal.mar
                  [004A24]  4587  	STORE_REG <WHAMI>, srn=p5, irn=p4, pal=1
File: ev6_pal_macros.mar
                  [004A24]   463M     ASSUME <0+1+0> lt 2
         6CB51098 [004A24]   475i 	hw_ldq/p p5, PT__WHAMI(p_temp)
         7CA41220 [004A28]   476i 	hw_stq/p p5, CNS__WHAMI(p4)
File: ev6_osf_pal.mar
                  [004A2C]  4588  	STORE_REG <SCC>, srn=p5, irn=p4, pal=1
File: ev6_pal_macros.mar
                  [004A2C]   463M     ASSUME <0+1+0> lt 2
         6CB510A0 [004A2C]   475i 	hw_ldq/p p5, PT__SCC(p_temp)
         7CA41228 [004A30]   476i 	hw_stq/p p5, CNS__SCC(p4)
File: ev6_osf_pal.mar
                  [004A34]  4589  	STORE_REG <PRBR>, srn=p5, irn=p4, pal=1
File: ev6_pal_macros.mar
                  [004A34]   463M     ASSUME <0+1+0> lt 2
         6CB510A8 [004A34]   475i 	hw_ldq/p p5, PT__PRBR(p_temp)
         7CA41230 [004A38]   476i 	hw_stq/p p5, CNS__PRBR(p4)
File: ev6_osf_pal.mar
                  [004A3C]  4590  	STORE_REG <PTBR>, srn=p5, irn=p4, pal=1
File: ev6_pal_macros.mar
                  [004A3C]   463M     ASSUME <0+1+0> lt 2
         6CB51008 [004A3C]   475i 	hw_ldq/p p5, PT__PTBR(p_temp)
         7CA41238 [004A40]   476i 	hw_stq/p p5, CNS__PTBR(p4)
File: ev6_osf_pal.mar
                  [004A44]  4591  	STORE_REG <TRAP>, srn=p5, irn=p4, pal=1
File: ev6_pal_macros.mar
                  [004A44]   463M     ASSUME <0+1+0> lt 2
         6CB510B0 [004A44]   475i 	hw_ldq/p p5, PT__TRAP(p_temp)
         7CA41240 [004A48]   476i 	hw_stq/p p5, CNS__TRAP(p4)
File: ev6_osf_pal.mar
                  [004A4C]  4592  	STORE_REG <HALT_CODE>, srn=p5, irn=p4, pal=1	; Do I need this?
File: ev6_pal_macros.mar
                  [004A4C]   463M     ASSUME <0+1+0> lt 2
         6CB510C8 [004A4C]   475i 	hw_ldq/p p5, PT__HALT_CODE(p_temp)
         7CA41248 [004A50]   476i 	hw_stq/p p5, CNS__HALT_CODE(p4)
File: ev6_osf_pal.mar
                  [004A54]  4593  	STORE_REG <KSP>, srn=p5, irn=p4, pal=1
File: ev6_pal_macros.mar
                  [004A54]   463M     ASSUME <0+1+0> lt 2
         6CB51018 [004A54]   475i 	hw_ldq/p p5, PT__KSP(p_temp)
         7CA41250 [004A58]   476i 	hw_stq/p p5, CNS__KSP(p4)
File: ev6_osf_pal.mar
                  [004A5C]  4594  	STORE_REG <SCBB>, srn=p5, irn=p4, pal=1
File: ev6_pal_macros.mar
                  [004A5C]   463M     ASSUME <0+1+0> lt 2
         6CB51170 [004A5C]   475i 	hw_ldq/p p5, PT__SCBB(p_temp)
         7CA41258 [004A60]   476i 	hw_stq/p p5, CNS__SCBB(p4)
File: ev6_osf_pal.mar
                  [004A64]  4595  	STORE_REG <PCBB>, srn=p5, irn=p4, pal=1
File: ev6_pal_macros.mar
                  [004A64]   463M     ASSUME <0+1+0> lt 2
         6CB51010 [004A64]   475i 	hw_ldq/p p5, PT__PCBB(p_temp)
         7CA41260 [004A68]   476i 	hw_stq/p p5, CNS__PCBB(p4)
File: ev6_osf_pal.mar
                  [004A6C]  4596  	STORE_REG <VPTB>, srn=p5, irn=p4, pal=1
File: ev6_pal_macros.mar
                  [004A6C]   463M     ASSUME <0+1+0> lt 2
         6CB51000 [004A6C]   475i 	hw_ldq/p p5, PT__VPTB(p_temp)
         7CA41268 [004A70]   476i 	hw_stq/p p5, CNS__VPTB(p4)
File: ev6_osf_pal.mar
                  [004A74]  4597  	STORE_REG <M_CTL>, srn=p5, irn=p4, pal=1
File: ev6_pal_macros.mar
                  [004A74]   463M     ASSUME <0+1+0> lt 2
         6CB510C0 [004A74]   475i 	hw_ldq/p p5, PT__M_CTL(p_temp)
         7CA41390 [004A78]   476i 	hw_stq/p p5, CNS__M_CTL(p4)
File: ev6_osf_pal.mar
                  [004A7C]  4598  ;
                  [004A7C]  4599  ; Now save the IPRs that are restorable with some informational sandwiched in.
                  [004A7C]  4600  ;
         6CB510B8 [004A7C]  4601  	hw_ldq/p p5, PT__VA_CTL(p_temp)			; control part
         6CD51000 [004A80]  4602  	hw_ldq/p p6, PT__VPTB(p_temp)			; vtpb part
         44A60405 [004A84]  4603  	bis	p5, p6, p5				; combine
         7CA41328 [004A88]  4604  	hw_stq/p p5, CNS__VA_CTL(p4)
                  [004A8C]  4605  
         7EE41330 [004A8C]  4606  	hw_stq/p p23, CNS__EXC_ADDR(p4)
                  [004A90]  4607  
                  [004A90]  4608  	STORE_REG <IER_CM>, srn=p5, irn=p4, ipr=1		; (4,0L)
File: ev6_pal_macros.mar
                  [004A90]   463M     ASSUME <0+0+1> lt 2
         64BF0B10 [004A90]   480i 	hw_mfpr	p5, EV6__IER_CM
         7CA41338 [004A94]   481i 	hw_stq/p p5, CNS__IER_CM(p4)
File: ev6_osf_pal.mar
                  [004A98]  4609  	STORE_REG <I_STAT>, srn=p5, irn=p4, ipr=1		; (0L) info only
File: ev6_pal_macros.mar
                  [004A98]   463M     ASSUME <0+0+1> lt 2
         64BF1610 [004A98]   480i 	hw_mfpr	p5, EV6__I_STAT
         7CA41378 [004A9C]   481i 	hw_stq/p p5, CNS__I_STAT(p4)
File: ev6_osf_pal.mar
                  [004AA0]  4610  	STORE_REG <SIRR>, srn=p5, irn=p4, ipr=1			; (4,0L)
File: ev6_pal_macros.mar
                  [004AA0]   463M     ASSUME <0+0+1> lt 2
         64BF0C10 [004AA0]   480i 	hw_mfpr	p5, EV6__SIRR
         7CA41340 [004AA4]   481i 	hw_stq/p p5, CNS__SIRR(p4)
File: ev6_osf_pal.mar
                  [004AA8]  4611  	STORE_REG <MM_STAT>, srn=p5, irn=p4, ipr=1		; (0L) info only
File: ev6_pal_macros.mar
                  [004AA8]   463M     ASSUME <0+0+1> lt 2
         64BF2700 [004AA8]   480i 	hw_mfpr	p5, EV6__MM_STAT
         7CA41388 [004AAC]   481i 	hw_stq/p p5, CNS__MM_STAT(p4)
File: ev6_osf_pal.mar
                  [004AB0]  4612  	STORE_REG <PAL_BASE>, srn=p5, irn=p4, ipr=1		; (4,0L)
File: ev6_pal_macros.mar
                  [004AB0]   463M     ASSUME <0+0+1> lt 2
         64BF1010 [004AB0]   480i 	hw_mfpr	p5, EV6__PAL_BASE
         7CA41358 [004AB4]   481i 	hw_stq/p p5, CNS__PAL_BASE(p4)
File: ev6_osf_pal.mar
                  [004AB8]  4613  	STORE_REG <DTB_ALT_MODE>, srn=p5, irn=p4, pal=1		; (6,0L)
File: ev6_pal_macros.mar
                  [004AB8]   463M     ASSUME <0+1+0> lt 2
         6CB51148 [004AB8]   475i 	hw_ldq/p p5, PT__DTB_ALT_MODE(p_temp)
         7CA41380 [004ABC]   476i 	hw_stq/p p5, CNS__DTB_ALT_MODE(p4)
File: ev6_osf_pal.mar
                  [004AC0]  4614  ;	STORE_REG <I_CTL>, srn=p5, irn=p4, ipr=1		; (4,0L)
                  [004AC0]  4615  ; isp bug workaround
                  [004AC0]  4616  ;
         64BF1110 [004AC0]  4617  	hw_mfpr	p5, EV6__I_CTL
                  [004AC4]  4618  	GET_32CONS p6, <^x804000>, r31
File: ev6_pal_macros.mar
                  [004AC4]   239i  ASSUME <^x804000> le  <^x7FFFFFFF>
         24DF0080 [004AC4]   240M 	ldah	p6,<<^x804000>+32768>@-16(r31); + xxx<31:16>
         20C64000 [004AC8]   241M 	lda	p6,<<^x804000> & ^XFFFF>(p6) ; r31+xxx<15:0>
File: ev6_osf_pal.mar
         44A60105 [004ACC]  4619  	bic	p5, p6, p5			; clear unpredicatables
         7CA41360 [004AD0]  4620  	hw_stq/p p5, CNS__I_CTL(p4)
                  [004AD4]  4621  ; End of hack
                  [004AD4]  4622  	NOP
File: ev6_pal_macros.mar
         47FF041F [004AD4]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004AD8]  4623  	NOP
File: ev6_pal_macros.mar
         47FF041F [004AD8]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004ADC]  4624  	NOP					; don't save PCTR_CTL
File: ev6_pal_macros.mar
         47FF041F [004ADC]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004AE0]  4625  	NOP
File: ev6_pal_macros.mar
         47FF041F [004AE0]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004AE4]  4626  	NOP
File: ev6_pal_macros.mar
         47FF041F [004AE4]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004AE8]  4627  	STORE_REG <PROCESS_CONTEXT>, srn=p5, irn=p4, ipr=1	; (4,0L)
File: ev6_pal_macros.mar
                  [004AE8]   463M     ASSUME <0+0+1> lt 2
         64BF5F10 [004AE8]   480i 	hw_mfpr	p5, EV6__PROCESS_CONTEXT
         7CA41370 [004AEC]   481i 	hw_stq/p p5, CNS__PROCESS_CONTEXT(p4)
File: ev6_osf_pal.mar
                  [004AF0]  4628  ;
                  [004AF0]  4629  ; Now save the rest of the informational IPRs. For now, we don't bother
                  [004AF0]  4630  ; with the CBOX chain. ??
                  [004AF0]  4631  ;
                  [004AF0]  4632  	STORE_REG <DC_STAT>, srn=p5, irn=p4, ipr=1	; (6,0L)
File: ev6_pal_macros.mar
                  [004AF0]   463M     ASSUME <0+0+1> lt 2
         64BF2A40 [004AF0]   480i 	hw_mfpr	p5, EV6__DC_STAT
         7CA413A0 [004AF4]   481i 	hw_stq/p p5, CNS__DC_STAT(p4)
File: ev6_osf_pal.mar
                  [004AF8]  4633  	STORE_REG <VA>, srn=p5, irn=p4, ipr=1		; (4-7,1L)
File: ev6_pal_macros.mar
                  [004AF8]   463M     ASSUME <0+0+1> lt 2
         64BFC2F0 [004AF8]   480i 	hw_mfpr	p5, EV6__VA
         7CA41320 [004AFC]   481i 	hw_stq/p p5, CNS__VA(p4)
File: ev6_osf_pal.mar
                  [004B00]  4634  	STORE_REG <ISUM>, srn=p5, irn=p4, ipr=1		; (0L)
File: ev6_pal_macros.mar
                  [004B00]   463M     ASSUME <0+0+1> lt 2
         64BF0D00 [004B00]   480i 	hw_mfpr	p5, EV6__ISUM
         7CA41348 [004B04]   481i 	hw_stq/p p5, CNS__ISUM(p4)
File: ev6_osf_pal.mar
         7FE41350 [004B08]  4635  	hw_stq/p 31, CNS__EXC_SUM(p4)			; just zero exc_sum
                  [004B0C]  4636  							; since not useful
                  [004B0C]  4637  ;
                  [004B0C]  4638  ; For some reason, previous implementations have computed the size of the
                  [004B0C]  4639  ; impure area taken up by a mchkflag quadword, the pal_temps, shadows, and
                  [004B0C]  4640  ; iprs. That size is written to the mchkflag quadword. I will do that
                  [004B0C]  4641  ; for now in case the console wants that information. Everything is quad,
                  [004B0C]  4642  ; so I'm not bothering with rounding.
                  [004B0C]  4643  ;
                  [004B0C]  4644  	GET_16CONS	r0, <CNS__SIZE>, r31
File: ev6_pal_macros.mar
                  [004B0C]   249M 	ASSUME <<CNS__SIZE>> le  <^x7FFF>
         201F03B0 [004B0C]   250M 	lda	r0,<CNS__SIZE>(r31) ; r31+xxx<15:0>
File: ev6_osf_pal.mar
                  [004B10]  4645  	GET_16CONS	r1, <CNS__MCHKFLAG>, r31
File: ev6_pal_macros.mar
                  [004B10]   249M 	ASSUME <<CNS__MCHKFLAG>> le  <^x7FFF>
         203F0210 [004B10]   250M 	lda	r1,<CNS__MCHKFLAG>(r31) ; r31+xxx<15:0>
File: ev6_osf_pal.mar
         40010520 [004B14]  4646  	subq	r0, r1, r0			; size - mchkflag location
         7C041210 [004B18]  4647  	hw_stq/p r0, CNS__MCHKFLAG(p4)		; save the computation
                  [004B1C]  4648  ;
                  [004B1C]  4649  ; Now write the dump flag. 
                  [004B1C]  4650  ;
         47E03400 [004B1C]  4651  	bis	r31, #1, r0
         7C041000 [004B20]  4652  	hw_stq/p r0, CNS__FLAG(p4)		; set dump area flag
                  [004B24]  4653  ;
                  [004B24]  4654  ; Now return to caller
                  [004B24]  4655  ;
         44E03407 [004B24]  4656  	bis	p7, #1, p7			; return in pal mode
                  [004B28]  4657  	PVC_JSR save_state, bsr=1, dest=1
File: ev6_pal_macros.mar
                  [004B28]   534i  pvc_lbl \pcv_index, \pcv_jsr_save_state0, osf, \pcv_jsr_save_state0_inst
File: ev6_osf_pal.mar
         7BE7A000 [004B28]  4658  	hw_ret_stall (p7)			; stall for pvc
                  [004B2C]  4659  
                  [004B2C]  4660  ;+
                  [004B2C]  4661  ; pal__restore_state
                  [004B2C]  4662  ;
                  [004B2C]  4663  ; The shadow registers, except of course p_misc and p_temp, are pretty much
                  [004B2C]  4664  ; scratch, so we don't worry about stepping on them.
                  [004B2C]  4665  ;
                  [004B2C]  4666  ; Current state:
                  [004B2C]  4667  ;	Shadow mode on
                  [004B2C]  4668  ;
                  [004B2C]  4669  ;	p7		return address
                  [004B2C]  4670  ;
                  [004B2C]  4671  ;	p_temp		valid
                  [004B2C]  4672  ;	PT__IMPURE	valid
                  [004B2C]  4673  ;	PT__WHAMI	valid
                  [004B2C]  4674  ;
                  [004B2C]  4675  ; The assumptions here are that shadow mode is on, that p_temp is valid,
                  [004B2C]  4676  ; and that PT__IMPURE and PT__WHAMI have not been written over.
                  [004B2C]  4677  ; If these assumptions are not valid (i.e, if we are switching between other
                  [004B2C]  4678  ; than our VMS and UNIX PALcodes, the exit_console platform-dependent code
                  [004B2C]  4679  ; will have to figure out how to set these up.
                  [004B2C]  4680  ;
                  [004B2C]  4681  ; Exit state:
                  [004B2C]  4682  ;	p23		exc_addr
                  [004B2C]  4683  ;-
                  [004B2C]  4684  
                  [004B2C]  4685  pal__restore_state:
         6C351088 [004B2C]  4686  	hw_ldq/p	r1, PT__IMPURE(p_temp)	; get base of impure area
                  [004B30]  4687  
                  [004B30]  4688  .if eq ev6_p1
                  [004B30]  4689  
                  [004B30]  4690  ;
                  [004B30]  4691  ; Restore floating point registers. First make sure FEN is on.
                  [004B30]  4692  ;
                  [004B30]  4693  	GET_16CONS	r0, <1@EV6__PROCESS_CONTEXT__FPE__S>, r31
                  [004B30]  4694  	hw_mtpr	r0, EV6__FPE			; (4,0L) write new fpe
                  [004B30]  4695  
                  [004B30]  4696  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align with nops
                  [004B30]  4697  
                  [004B30]  4698  	hw_mtpr	r0, EV6__FPE			; (4,0L) force retire
                  [004B30]  4699  	bis	r31, r31, r31
                  [004B30]  4700  	bis	r31, r31, r31
                  [004B30]  4701  	bis	r31, r31, r31
                  [004B30]  4702  
                  [004B30]  4703  	bis	r0, r0, r0			; buffer block 1
                  [004B30]  4704  	bis	r31, r31, r31
                  [004B30]  4705  	bis	r31, r31, r31
                  [004B30]  4706  	bis	r31, r31, r31
                  [004B30]  4707  
                  [004B30]  4708  	bis	r0, r0, r0			; buffer block 2
                  [004B30]  4709  	bis	r31, r31, r31
                  [004B30]  4710  	bis	r31, r31, r31
                  [004B30]  4711  	bis	r31, r31, r31
                  [004B30]  4712  
                  [004B30]  4713  	bis	r0, r0, r0			; buffer block 3
                  [004B30]  4714  	bis	r0, r0, r0			; for pvc #7
                  [004B30]  4715  	bis	r0, r0, r0
                  [004B30]  4716  	bis	r0, r0, r0
                  [004B30]  4717  
                  [004B30]  4718  	hw_ldq/p r0, CNS__FPCR(r1)		; get FPCR
                  [004B30]  4719  	itoft	r0, f0				; convert to float
                  [004B30]  4720  
                  [004B30]  4721  restore_fpcr_offset = < pal__restore_fpcr_done - pal__restore_fpcr>
                  [004B30]  4722  
                  [004B30]  4723  	br	r2, pal__restore_fpcr
                  [004B30]  4724  pal__restore_fpcr:
                  [004B30]  4725  	addq	r2, #<restore_fpcr_offset+1>, r2	; past stall in palmode
                  [004B30]  4726  	mt_fpcr	f0					; restore FPCR
                  [004B30]  4727  	bsr	r31, .					; push prediction stack
                  [004B30]  4728  	PVC_JSR restore_fpcr
                  [004B30]  4729  	hw_ret_stall (r2)				; pop prediction stack
                  [004B30]  4730  	PVC_JSR restore_fpcr, dest=1
                  [004B30]  4731  pal__restore_fpcr_done:
                  [004B30]  4732  
                  [004B30]  4733  	t=0
                  [004B30]  4734  	.repeat 31
                  [004B30]  4735  	RESTORE_REG \t, srn=r0, irn=r1, fpu=1
                  [004B30]  4736  	t=t+1
                  [004B30]  4737  	.endr
                  [004B30]  4738  
                  [004B30]  4739  .endc
                  [004B30]  4689I 
                  [004B30]  4690I ;
                  [004B30]  4691I ; Restore floating point registers. First make sure FEN is on.
                  [004B30]  4692I ;
                  [004B30]  4693I 	GET_16CONS	r0, <1@EV6__PROCESS_CONTEXT__FPE__S>, r31
File: ev6_pal_macros.mar
                  [004B30]   249i 	ASSUME <<1@EV6__PROCESS_CONTEXT__FPE__S>> le  <^x7FFF>
         201F0004 [004B30]   250i 	lda	r0,<1@EV6__PROCESS_CONTEXT__FPE__S>(r31) ; r31+xxx<15:0>
File: ev6_osf_pal.mar
         77E05010 [004B34]  4694I 	hw_mtpr	r0, EV6__FPE			; (4,0L) write new fpe
                  [004B38]  4695I 
                  [004B38]  4696I 	ALIGN_FETCH_BLOCK <^x47FF041F>		; align with nops
File: ev6_pal_macros.mar
47FF041F 47FF041F [004B38]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
                  [004B40]  4697I 
         77E05010 [004B40]  4698I 	hw_mtpr	r0, EV6__FPE			; (4,0L) force retire
         47FF041F [004B44]  4699I 	bis	r31, r31, r31
         47FF041F [004B48]  4700I 	bis	r31, r31, r31
         47FF041F [004B4C]  4701I 	bis	r31, r31, r31
                  [004B50]  4702I 
         44000400 [004B50]  4703I 	bis	r0, r0, r0			; buffer block 1
         47FF041F [004B54]  4704I 	bis	r31, r31, r31
         47FF041F [004B58]  4705I 	bis	r31, r31, r31
         47FF041F [004B5C]  4706I 	bis	r31, r31, r31
                  [004B60]  4707I 
         44000400 [004B60]  4708I 	bis	r0, r0, r0			; buffer block 2
         47FF041F [004B64]  4709I 	bis	r31, r31, r31
         47FF041F [004B68]  4710I 	bis	r31, r31, r31
         47FF041F [004B6C]  4711I 	bis	r31, r31, r31
                  [004B70]  4712I 
         44000400 [004B70]  4713I 	bis	r0, r0, r0			; buffer block 3
         44000400 [004B74]  4714I 	bis	r0, r0, r0			; for pvc #7
         44000400 [004B78]  4715I 	bis	r0, r0, r0
         44000400 [004B7C]  4716I 	bis	r0, r0, r0
                  [004B80]  4717I 
         6C011318 [004B80]  4718I 	hw_ldq/p r0, CNS__FPCR(r1)		; get FPCR
         501F0480 [004B84]  4719I 	itoft	r0, f0				; convert to float
                  [004B88]  4720I 
                  [004B88]  4721I restore_fpcr_offset = < pal__restore_fpcr_done - pal__restore_fpcr>
                  [004B88]  4722I 
         C0400000 [004B88]  4723I 	br	r2, pal__restore_fpcr
                  [004B8C]  4724I pal__restore_fpcr:
         40423402 [004B8C]  4725I 	addq	r2, #<restore_fpcr_offset+1>, r2	; past stall in palmode
         5C000480 [004B90]  4726I 	mt_fpcr	f0					; restore FPCR
         D3E00000 [004B94]  4727I 	bsr	r31, .					; push prediction stack
                  [004B98]  4728I 	PVC_JSR restore_fpcr
File: ev6_pal_macros.mar
                  [004B98]   531i  pvc_lbl \pcv_index, \pcv_jsr_restore_fpcr0, osf
File: ev6_osf_pal.mar
         7BE2A000 [004B98]  4729I 	hw_ret_stall (r2)				; pop prediction stack
                  [004B9C]  4730I 	PVC_JSR restore_fpcr, dest=1
File: ev6_pal_macros.mar
                  [004B9C]   534i  pvc_lbl \pcv_index, \pcv_jsr_restore_fpcr0, osf, \pcv_jsr_restore_fpcr0_inst
File: ev6_osf_pal.mar
                  [004B9C]  4731I pal__restore_fpcr_done:
                  [004B9C]  4732I 
                  [004B9C]  4733I 	t=0
                  [004B9C]  4734I 	.repeat 31
                  [004B9C]  4735I 	RESTORE_REG \t, srn=r0, irn=r1, fpu=1
                  [004B9C]  4736I 	t=t+1
                  [004B9C]  4737I 	.endr
                  [004B9C]  4735R 	RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004B9C]   491r     ASSUME <1+0+0> lt 2
         6C011110 [004B9C]   498i 	hw_ldq/p r0, CNS__F0(r1)
         501F0480 [004BA0]   499i 	itoft	r0, f0
File: ev6_osf_pal.mar
                  [004BA4]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BA4]   491r     ASSUME <1+0+0> lt 2
         6C011118 [004BA4]   498i 	hw_ldq/p r0, CNS__F1(r1)
         501F0481 [004BA8]   499i 	itoft	r0, f1
File: ev6_osf_pal.mar
                  [004BAC]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BAC]   491r     ASSUME <1+0+0> lt 2
         6C011120 [004BAC]   498i 	hw_ldq/p r0, CNS__F2(r1)
         501F0482 [004BB0]   499i 	itoft	r0, f2
File: ev6_osf_pal.mar
                  [004BB4]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BB4]   491r     ASSUME <1+0+0> lt 2
         6C011128 [004BB4]   498i 	hw_ldq/p r0, CNS__F3(r1)
         501F0483 [004BB8]   499i 	itoft	r0, f3
File: ev6_osf_pal.mar
                  [004BBC]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BBC]   491r     ASSUME <1+0+0> lt 2
         6C011130 [004BBC]   498i 	hw_ldq/p r0, CNS__F4(r1)
         501F0484 [004BC0]   499i 	itoft	r0, f4
File: ev6_osf_pal.mar
                  [004BC4]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BC4]   491r     ASSUME <1+0+0> lt 2
         6C011138 [004BC4]   498i 	hw_ldq/p r0, CNS__F5(r1)
         501F0485 [004BC8]   499i 	itoft	r0, f5
File: ev6_osf_pal.mar
                  [004BCC]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BCC]   491r     ASSUME <1+0+0> lt 2
         6C011140 [004BCC]   498i 	hw_ldq/p r0, CNS__F6(r1)
         501F0486 [004BD0]   499i 	itoft	r0, f6
File: ev6_osf_pal.mar
                  [004BD4]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BD4]   491r     ASSUME <1+0+0> lt 2
         6C011148 [004BD4]   498i 	hw_ldq/p r0, CNS__F7(r1)
         501F0487 [004BD8]   499i 	itoft	r0, f7
File: ev6_osf_pal.mar
                  [004BDC]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BDC]   491r     ASSUME <1+0+0> lt 2
         6C011150 [004BDC]   498i 	hw_ldq/p r0, CNS__F8(r1)
         501F0488 [004BE0]   499i 	itoft	r0, f8
File: ev6_osf_pal.mar
                  [004BE4]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BE4]   491r     ASSUME <1+0+0> lt 2
         6C011158 [004BE4]   498i 	hw_ldq/p r0, CNS__F9(r1)
         501F0489 [004BE8]   499i 	itoft	r0, f9
File: ev6_osf_pal.mar
                  [004BEC]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BEC]   491r     ASSUME <1+0+0> lt 2
         6C011160 [004BEC]   498i 	hw_ldq/p r0, CNS__F10(r1)
         501F048A [004BF0]   499i 	itoft	r0, f10
File: ev6_osf_pal.mar
                  [004BF4]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BF4]   491r     ASSUME <1+0+0> lt 2
         6C011168 [004BF4]   498i 	hw_ldq/p r0, CNS__F11(r1)
         501F048B [004BF8]   499i 	itoft	r0, f11
File: ev6_osf_pal.mar
                  [004BFC]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004BFC]   491r     ASSUME <1+0+0> lt 2
         6C011170 [004BFC]   498i 	hw_ldq/p r0, CNS__F12(r1)
         501F048C [004C00]   499i 	itoft	r0, f12
File: ev6_osf_pal.mar
                  [004C04]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C04]   491r     ASSUME <1+0+0> lt 2
         6C011178 [004C04]   498i 	hw_ldq/p r0, CNS__F13(r1)
         501F048D [004C08]   499i 	itoft	r0, f13
File: ev6_osf_pal.mar
                  [004C0C]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C0C]   491r     ASSUME <1+0+0> lt 2
         6C011180 [004C0C]   498i 	hw_ldq/p r0, CNS__F14(r1)
         501F048E [004C10]   499i 	itoft	r0, f14
File: ev6_osf_pal.mar
                  [004C14]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C14]   491r     ASSUME <1+0+0> lt 2
         6C011188 [004C14]   498i 	hw_ldq/p r0, CNS__F15(r1)
         501F048F [004C18]   499i 	itoft	r0, f15
File: ev6_osf_pal.mar
                  [004C1C]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C1C]   491r     ASSUME <1+0+0> lt 2
         6C011190 [004C1C]   498i 	hw_ldq/p r0, CNS__F16(r1)
         501F0490 [004C20]   499i 	itoft	r0, f16
File: ev6_osf_pal.mar
                  [004C24]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C24]   491r     ASSUME <1+0+0> lt 2
         6C011198 [004C24]   498i 	hw_ldq/p r0, CNS__F17(r1)
         501F0491 [004C28]   499i 	itoft	r0, f17
File: ev6_osf_pal.mar
                  [004C2C]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C2C]   491r     ASSUME <1+0+0> lt 2
         6C0111A0 [004C2C]   498i 	hw_ldq/p r0, CNS__F18(r1)
         501F0492 [004C30]   499i 	itoft	r0, f18
File: ev6_osf_pal.mar
                  [004C34]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C34]   491r     ASSUME <1+0+0> lt 2
         6C0111A8 [004C34]   498i 	hw_ldq/p r0, CNS__F19(r1)
         501F0493 [004C38]   499i 	itoft	r0, f19
File: ev6_osf_pal.mar
                  [004C3C]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C3C]   491r     ASSUME <1+0+0> lt 2
         6C0111B0 [004C3C]   498i 	hw_ldq/p r0, CNS__F20(r1)
         501F0494 [004C40]   499i 	itoft	r0, f20
File: ev6_osf_pal.mar
                  [004C44]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C44]   491r     ASSUME <1+0+0> lt 2
         6C0111B8 [004C44]   498i 	hw_ldq/p r0, CNS__F21(r1)
         501F0495 [004C48]   499i 	itoft	r0, f21
File: ev6_osf_pal.mar
                  [004C4C]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C4C]   491r     ASSUME <1+0+0> lt 2
         6C0111C0 [004C4C]   498i 	hw_ldq/p r0, CNS__F22(r1)
         501F0496 [004C50]   499i 	itoft	r0, f22
File: ev6_osf_pal.mar
                  [004C54]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C54]   491r     ASSUME <1+0+0> lt 2
         6C0111C8 [004C54]   498i 	hw_ldq/p r0, CNS__F23(r1)
         501F0497 [004C58]   499i 	itoft	r0, f23
File: ev6_osf_pal.mar
                  [004C5C]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C5C]   491r     ASSUME <1+0+0> lt 2
         6C0111D0 [004C5C]   498i 	hw_ldq/p r0, CNS__F24(r1)
         501F0498 [004C60]   499i 	itoft	r0, f24
File: ev6_osf_pal.mar
                  [004C64]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C64]   491r     ASSUME <1+0+0> lt 2
         6C0111D8 [004C64]   498i 	hw_ldq/p r0, CNS__F25(r1)
         501F0499 [004C68]   499i 	itoft	r0, f25
File: ev6_osf_pal.mar
                  [004C6C]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C6C]   491r     ASSUME <1+0+0> lt 2
         6C0111E0 [004C6C]   498i 	hw_ldq/p r0, CNS__F26(r1)
         501F049A [004C70]   499i 	itoft	r0, f26
File: ev6_osf_pal.mar
                  [004C74]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C74]   491r     ASSUME <1+0+0> lt 2
         6C0111E8 [004C74]   498i 	hw_ldq/p r0, CNS__F27(r1)
         501F049B [004C78]   499i 	itoft	r0, f27
File: ev6_osf_pal.mar
                  [004C7C]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C7C]   491r     ASSUME <1+0+0> lt 2
         6C0111F0 [004C7C]   498i 	hw_ldq/p r0, CNS__F28(r1)
         501F049C [004C80]   499i 	itoft	r0, f28
File: ev6_osf_pal.mar
                  [004C84]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C84]   491r     ASSUME <1+0+0> lt 2
         6C0111F8 [004C84]   498i 	hw_ldq/p r0, CNS__F29(r1)
         501F049D [004C88]   499i 	itoft	r0, f29
File: ev6_osf_pal.mar
                  [004C8C]  4735R 		RESTORE_REG \t, srn=r0, irn=r1, fpu=1
File: ev6_pal_macros.mar
                  [004C8C]   491r     ASSUME <1+0+0> lt 2
         6C011200 [004C8C]   498i 	hw_ldq/p r0, CNS__F30(r1)
         501F049E [004C90]   499i 	itoft	r0, f30
File: ev6_osf_pal.mar
                  [004C94]  4738I 	
                  [004C94]  4740  
                  [004C94]  4741  ;
                  [004C94]  4742  ; Now restore the important PALtemps.
                  [004C94]  4743  ; We assume the following did not change or were restored by exit_console
                  [004C94]  4744  ;	p_temp
                  [004C94]  4745  ;	PT__IMPURE
                  [004C94]  4746  ;	PT__WHAMI
                  [004C94]  4747  ;
                  [004C94]  4748  	RESTORE_REG <SCC>, srn=r0, irn=r1, pal=1
File: ev6_pal_macros.mar
                  [004C94]   491M     ASSUME <0+1+0> lt 2
         6C011228 [004C94]   503i 	hw_ldq/p r0, CNS__SCC(r1)
         7C1510A0 [004C98]   504i 	hw_stq/p r0, PT__SCC(p_temp)
File: ev6_osf_pal.mar
                  [004C9C]  4749  	RESTORE_REG <PRBR>, srn=r0, irn=r1, pal=1
File: ev6_pal_macros.mar
                  [004C9C]   491M     ASSUME <0+1+0> lt 2
         6C011230 [004C9C]   503i 	hw_ldq/p r0, CNS__PRBR(r1)
         7C1510A8 [004CA0]   504i 	hw_stq/p r0, PT__PRBR(p_temp)
File: ev6_osf_pal.mar
                  [004CA4]  4750  	RESTORE_REG <PTBR>, srn=r0, irn=r1, pal=1
File: ev6_pal_macros.mar
                  [004CA4]   491M     ASSUME <0+1+0> lt 2
         6C011238 [004CA4]   503i 	hw_ldq/p r0, CNS__PTBR(r1)
         7C151008 [004CA8]   504i 	hw_stq/p r0, PT__PTBR(p_temp)
File: ev6_osf_pal.mar
                  [004CAC]  4751  	RESTORE_REG <KSP>, srn=r0, irn=r1, pal=1
File: ev6_pal_macros.mar
                  [004CAC]   491M     ASSUME <0+1+0> lt 2
         6C011250 [004CAC]   503i 	hw_ldq/p r0, CNS__KSP(r1)
         7C151018 [004CB0]   504i 	hw_stq/p r0, PT__KSP(p_temp)
File: ev6_osf_pal.mar
                  [004CB4]  4752  	RESTORE_REG <SCBB>, srn=r0, irn=r1, pal=1
File: ev6_pal_macros.mar
                  [004CB4]   491M     ASSUME <0+1+0> lt 2
         6C011258 [004CB4]   503i 	hw_ldq/p r0, CNS__SCBB(r1)
         7C151170 [004CB8]   504i 	hw_stq/p r0, PT__SCBB(p_temp)
File: ev6_osf_pal.mar
                  [004CBC]  4753  	RESTORE_REG <PCBB>, srn=r0, irn=r1, pal=1
File: ev6_pal_macros.mar
                  [004CBC]   491M     ASSUME <0+1+0> lt 2
         6C011260 [004CBC]   503i 	hw_ldq/p r0, CNS__PCBB(r1)
         7C151010 [004CC0]   504i 	hw_stq/p r0, PT__PCBB(p_temp)
File: ev6_osf_pal.mar
                  [004CC4]  4754  	RESTORE_REG <VPTB>, srn=r0, irn=r1, pal=1
File: ev6_pal_macros.mar
                  [004CC4]   491M     ASSUME <0+1+0> lt 2
         6C011268 [004CC4]   503i 	hw_ldq/p r0, CNS__VPTB(r1)
         7C151000 [004CC8]   504i 	hw_stq/p r0, PT__VPTB(p_temp)
File: ev6_osf_pal.mar
                  [004CCC]  4755  
                  [004CCC]  4756  .if ne kseg_hack					; kseg hack
                  [004CCC]  4757  	hw_stq/p r31, PT__M_CTL(p_temp)
                  [004CCC]  4758  .iff
                  [004CCC]  4759  	RESTORE_REG <M_CTL>, srn=r0, irn=r1, pal=1
                  [004CCC]  4760  .endc
                  [004CCC]  4759I 	RESTORE_REG <M_CTL>, srn=r0, irn=r1, pal=1
File: ev6_pal_macros.mar
                  [004CCC]   491i     ASSUME <0+1+0> lt 2
         6C011390 [004CCC]   503i 	hw_ldq/p r0, CNS__M_CTL(r1)
         7C1510C0 [004CD0]   504i 	hw_stq/p r0, PT__M_CTL(p_temp)
File: ev6_osf_pal.mar
                  [004CD4]  4761  
                  [004CD4]  4762  ;
                  [004CD4]  4763  ; Now restore the IPRs.
                  [004CD4]  4764  ;
                  [004CD4]  4765  ; Don't do I_CTL until we are ready to turn shadow registers off.
                  [004CD4]  4766  ;
                  [004CD4]  4767  ; Don't restore DC_CTL. The code has to assume this register has not
                  [004CD4]  4768  ; changed. It wouldn't do to fool with the set enables.
                  [004CD4]  4769  ;
                  [004CD4]  4770  ; Restore the VPTB portion of VA_CTL from CNS__VPTB, the generic spot
                  [004CD4]  4771  ; the firmware wants to use when it's modifying VPTB. Also restore the
                  [004CD4]  4772  ; control part to PT__VA_CTL.
                  [004CD4]  4773  ;
         6C011328 [004CD4]  4774  	hw_ldq/p r0, CNS__VA_CTL(r1)			; get va_ctl
         6C411268 [004CD8]  4775  	hw_ldq/p r2, CNS__VPTB(r1)			; get vptb
         4807B720 [004CDC]  4776  	sll	r0, #<64-EV6__VA_CTL__RSV1__S>, r0	; clean control part
         4807B680 [004CE0]  4777  	srl	r0, #<64-EV6__VA_CTL__RSV1__S>, r0
         7C1510B8 [004CE4]  4778  	hw_stq/p r0, PT__VA_CTL(p_temp)			; store control part
         4843D682 [004CE8]  4779  	srl	r2, #<EV6__VA_CTL__VPTB__S>, r2		; clean vptb part
         4843D722 [004CEC]  4780  	sll	r2, #<EV6__VA_CTL__VPTB__S>, r2
         44020400 [004CF0]  4781  	bis	r0, r2, r0				; combine
         77E0C420 [004CF4]  4782  	hw_mtpr	r0, EV6__VA_CTL				; (5,1L)
                  [004CF8]  4783  
                  [004CF8]  4784  	RESTORE_REG <IER_CM>, srn=r0, irn=r1, ipr=1		; (4,0L)
File: ev6_pal_macros.mar
                  [004CF8]   491M     ASSUME <0+0+1> lt 2
         6C011338 [004CF8]   508i 	hw_ldq/p r0, CNS__IER_CM(r1)
         77E00B10 [004CFC]   509i 	hw_mtpr	r0, EV6__IER_CM
File: ev6_osf_pal.mar
                  [004D00]  4785  	RESTORE_REG <DTB_ALT_MODE>, srn=r0, irn=r1, ipr=1	; (6,0L)
File: ev6_pal_macros.mar
                  [004D00]   491M     ASSUME <0+0+1> lt 2
         6C011380 [004D00]   508i 	hw_ldq/p r0, CNS__DTB_ALT_MODE(r1)
         77E02640 [004D04]   509i 	hw_mtpr	r0, EV6__DTB_ALT_MODE
File: ev6_osf_pal.mar
                  [004D08]  4786  	RESTORE_REG <SIRR>, srn=r0, irn=r1, ipr=1		; (4,0L)
File: ev6_pal_macros.mar
                  [004D08]   491M     ASSUME <0+0+1> lt 2
         6C011340 [004D08]   508i 	hw_ldq/p r0, CNS__SIRR(r1)
         77E00C10 [004D0C]   509i 	hw_mtpr	r0, EV6__SIRR
File: ev6_osf_pal.mar
                  [004D10]  4787  
                  [004D10]  4788  .if ne kseg_hack						; kseg hack
                  [004D10]  4789  	hw_stq/p r31, CNS__M_CTL(r1)
                  [004D10]  4790  	hw_stq/p r31, PT__M_CTL(p_temp)	
                  [004D10]  4791  	hw_mtpr	r31, EV6__M_CTL
                  [004D10]  4792  .iff
                  [004D10]  4793  	RESTORE_REG <M_CTL>, srn=r0, irn=r1, ipr=1		; (6,0L)
                  [004D10]  4794  .endc
                  [004D10]  4793I 	RESTORE_REG <M_CTL>, srn=r0, irn=r1, ipr=1		; (6,0L)
File: ev6_pal_macros.mar
                  [004D10]   491i     ASSUME <0+0+1> lt 2
         6C011390 [004D10]   508i 	hw_ldq/p r0, CNS__M_CTL(r1)
         77E02840 [004D14]   509i 	hw_mtpr	r0, EV6__M_CTL
File: ev6_osf_pal.mar
                  [004D18]  4795  
                  [004D18]  4796  	RESTORE_REG <PAL_BASE>, srn=r0, irn=r1, ipr=1		; (4,0L)
File: ev6_pal_macros.mar
                  [004D18]   491M     ASSUME <0+0+1> lt 2
         6C011358 [004D18]   508i 	hw_ldq/p r0, CNS__PAL_BASE(r1)
         77E01010 [004D1C]   509i 	hw_mtpr	r0, EV6__PAL_BASE
File: ev6_osf_pal.mar
                  [004D20]  4797  	NOP
File: ev6_pal_macros.mar
         47FF041F [004D20]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004D24]  4798  	NOP
File: ev6_pal_macros.mar
         47FF041F [004D24]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004D28]  4799  	NOP				; don't restore PCTR_CTL
File: ev6_pal_macros.mar
         47FF041F [004D28]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004D2C]  4800  	NOP
File: ev6_pal_macros.mar
         47FF041F [004D2C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004D30]  4801  	NOP
File: ev6_pal_macros.mar
         47FF041F [004D30]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004D34]  4802  	RESTORE_REG <PROCESS_CONTEXT>, srn=r0, irn=r1, ipr=1	; (4,0L)
File: ev6_pal_macros.mar
                  [004D34]   491M     ASSUME <0+0+1> lt 2
         6C011370 [004D34]   508i 	hw_ldq/p r0, CNS__PROCESS_CONTEXT(r1)
         77E05F10 [004D38]   509i 	hw_mtpr	r0, EV6__PROCESS_CONTEXT
File: ev6_osf_pal.mar
                  [004D3C]  4803  
                  [004D3C]  4804  .if ne ev6_p1
                  [004D3C]  4805  	srl	r0, #EV6__FPE__FPE__S, r2		; shift into position
                  [004D3C]  4806  	and	r2, #1, r2				; clean
                  [004D3C]  4807  	hw_stq/p r2, CNS__FPE_STATE(r1)			; restore 'fpe' state
                  [004D3C]  4808  .endc							; 	from pctx
                  [004D3C]  4809  
                  [004D3C]  4810  ;
                  [004D3C]  4811  ; Current state:
                  [004D3C]  4812  ;	r0		process context
                  [004D3C]  4813  ;
                  [004D3C]  4814  ; Grab ASN and write it to DTB_ASNx
                  [004D3C]  4815  ;
         4804F680 [004D3C]  4816  	srl	r0, #EV6__ASN__ASN__S, r0	; shift down
         441FF000 [004D40]  4817  	and	r0, #EV6__ASN__ASN__M, r0	; clean it
         48071720 [004D44]  4818  	sll	r0, #EV6__DTB_ASN0__ASN__S,r0 	; ASN into mbox spot
                  [004D48]  4819  ;
                  [004D48]  4820  ; There must be a scoreboard bit -> register dependency chain to prevent
                  [004D48]  4821  ; hw_mtpr DTB_ASx from issuing while ANY of scoreboard bits <7:4> are set.
                  [004D48]  4822  ;
         645F10F0 [004D48]  4823  	hw_mfpr	r2, <EV6__PAL_BASE ! ^xF0>	; (4-7,0L)
         44420802 [004D4C]  4824  	xor	r2, r2, r2			; zap r2
         44400400 [004D50]  4825  	bis	r2, r0, r0			; force register dependency
                  [004D54]  4826  	NOP					; force fetch block
File: ev6_pal_macros.mar
         47FF041F [004D54]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004D58]  4827  
         77E02510 [004D58]  4828  	hw_mtpr	r0, EV6__DTB_ASN0		; (4,0L)
         77E0A580 [004D5C]  4829  	hw_mtpr	r0, EV6__DTB_ASN1		; (7,1L)
                  [004D60]  4830  ;
                  [004D60]  4831  ; Now restore shadows as needed.
                  [004D60]  4832  ; Analysis:
                  [004D60]  4833  ;	p4		not necessary
                  [004D60]  4834  ;	p5		not necessary
                  [004D60]  4835  ;	p6		not necessary
                  [004D60]  4836  ;	p7		return address. Do not touch.
                  [004D60]  4837  ;	p20		not necessary
                  [004D60]  4838  ;	p_temp		valid. Do not touch.
                  [004D60]  4839  ;	p_misc		restore
                  [004D60]  4840  ;	p23		restore from CNS__EXC_ADDR (or CNS__P23)
                  [004D60]  4841  ;
         6EC11308 [004D60]  4842  	hw_ldq/p p_misc, CNS__P_MISC(r1)
         6EE11330 [004D64]  4843  	hw_ldq/p p23, CNS__EXC_ADDR(r1)
                  [004D68]  4844  ;
                  [004D68]  4845  ; Now restore integer registers. Restore I_CTL with
                  [004D68]  4846  ; sde clear. After restoring integer registers, rewrite I_CTL
                  [004D68]  4847  ; with sde set. Assumption: PALcode is running with sde set!!
                  [004D68]  4848  ;
                  [004D68]  4849  ; We need to write I_CTL twice in case we are toggling the VA_48 bit
                  [004D68]  4850  ; in order to stall the pipe during the change.
                  [004D68]  4851  ;
                  [004D68]  4852  ; Restore the VPTB portion of the I_CTL from CNS__VPTB, the generic spot
                  [004D68]  4853  ; the firmware wants to use when it's modifying VPTB.
                  [004D68]  4854  ;
         6C011360 [004D68]  4855  	hw_ldq/p r0, CNS__I_CTL(r1)
         6C411268 [004D6C]  4856  	hw_ldq/p r2, CNS__VPTB(r1)			; get vptb
         48051720 [004D70]  4857  	sll	r0, #<64-EV6__I_CTL__CHIP_ID__S>, r0	; clean control part
         48051680 [004D74]  4858  	srl	r0, #<64-EV6__I_CTL__CHIP_ID__S>, r0
         4843D682 [004D78]  4859  	srl	r2, #<EV6__I_CTL__VPTB__S>, r2		; clean vptb part
         4843D722 [004D7C]  4860  	sll	r2, #<EV6__I_CTL__VPTB__S>, r2
                  [004D80]  4861  
                  [004D80]  4862  	ALIGN_FETCH_BLOCK <^x47FF041F>
File: ev6_pal_macros.mar
                  [004D80]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
                  [004D80]  4863  
         44020400 [004D80]  4864  	bis	r0, r2, r0			; combine
         44101100 [004D84]  4865  	bic	r0, #<1@EV6__I_CTL__SDE7__S>, r0; zap sde
                  [004D88]  4866  	RESTORE_REG 8, irn=r1
File: ev6_pal_macros.mar
                  [004D88]   491M     ASSUME <0+0+0> lt 2
         6D011050 [004D88]   494i 	hw_ldq/p r8, CNS__R8(r1)
File: ev6_osf_pal.mar
                  [004D8C]  4867  	RESTORE_REG 9, irn=r1
File: ev6_pal_macros.mar
                  [004D8C]   491M     ASSUME <0+0+0> lt 2
         6D211058 [004D8C]   494i 	hw_ldq/p r9, CNS__R9(r1)
File: ev6_osf_pal.mar
                  [004D90]  4868  
         77E01110 [004D90]  4869  	hw_mtpr	r0, EV6__I_CTL			; (4,0L) write i_ctl
                  [004D94]  4870  	RESTORE_REG 10, irn=r1
File: ev6_pal_macros.mar
                  [004D94]   491M     ASSUME <0+0+0> lt 2
         6D411060 [004D94]   494i 	hw_ldq/p r10, CNS__R10(r1)
File: ev6_osf_pal.mar
                  [004D98]  4871  	RESTORE_REG 11, irn=r1
File: ev6_pal_macros.mar
                  [004D98]   491M     ASSUME <0+0+0> lt 2
         6D611068 [004D98]   494i 	hw_ldq/p r11, CNS__R11(r1)
File: ev6_osf_pal.mar
                  [004D9C]  4872  	RESTORE_REG 12, irn=r1
File: ev6_pal_macros.mar
                  [004D9C]   491M     ASSUME <0+0+0> lt 2
         6D811070 [004D9C]   494i 	hw_ldq/p r12, CNS__R12(r1)
File: ev6_osf_pal.mar
                  [004DA0]  4873  
         77E01110 [004DA0]  4874  	hw_mtpr	r0, EV6__I_CTL			; (4,0L) stall outside IQ
                  [004DA4]  4875  	RESTORE_REG 13, irn=r1
File: ev6_pal_macros.mar
                  [004DA4]   491M     ASSUME <0+0+0> lt 2
         6DA11078 [004DA4]   494i 	hw_ldq/p r13, CNS__R13(r1)
File: ev6_osf_pal.mar
                  [004DA8]  4876  	RESTORE_REG 14, irn=r1
File: ev6_pal_macros.mar
                  [004DA8]   491M     ASSUME <0+0+0> lt 2
         6DC11080 [004DA8]   494i 	hw_ldq/p r14, CNS__R14(r1)
File: ev6_osf_pal.mar
                  [004DAC]  4877  	RESTORE_REG 15, irn=r1
File: ev6_pal_macros.mar
                  [004DAC]   491M     ASSUME <0+0+0> lt 2
         6DE11088 [004DAC]   494i 	hw_ldq/p r15, CNS__R15(r1)
File: ev6_osf_pal.mar
                  [004DB0]  4878  
                  [004DB0]  4879  	RESTORE_REG 16, irn=r1			; buffer block 1
File: ev6_pal_macros.mar
                  [004DB0]   491M     ASSUME <0+0+0> lt 2
         6E011090 [004DB0]   494i 	hw_ldq/p r16, CNS__R16(r1)
File: ev6_osf_pal.mar
                  [004DB4]  4880  	RESTORE_REG 17, irn=r1
File: ev6_pal_macros.mar
                  [004DB4]   491M     ASSUME <0+0+0> lt 2
         6E211098 [004DB4]   494i 	hw_ldq/p r17, CNS__R17(r1)
File: ev6_osf_pal.mar
                  [004DB8]  4881  	RESTORE_REG 18, irn=r1
File: ev6_pal_macros.mar
                  [004DB8]   491M     ASSUME <0+0+0> lt 2
         6E4110A0 [004DB8]   494i 	hw_ldq/p r18, CNS__R18(r1)
File: ev6_osf_pal.mar
                  [004DBC]  4882  	RESTORE_REG 19, irn=r1
File: ev6_pal_macros.mar
                  [004DBC]   491M     ASSUME <0+0+0> lt 2
         6E6110A8 [004DBC]   494i 	hw_ldq/p r19, CNS__R19(r1)
File: ev6_osf_pal.mar
                  [004DC0]  4883  
                  [004DC0]  4884  	RESTORE_REG 24, irn=r1			; buffer block 2
File: ev6_pal_macros.mar
                  [004DC0]   491M     ASSUME <0+0+0> lt 2
         6F0110D0 [004DC0]   494i 	hw_ldq/p r24, CNS__R24(r1)
File: ev6_osf_pal.mar
                  [004DC4]  4885  	RESTORE_REG 25, irn=r1
File: ev6_pal_macros.mar
                  [004DC4]   491M     ASSUME <0+0+0> lt 2
         6F2110D8 [004DC4]   494i 	hw_ldq/p r25, CNS__R25(r1)
File: ev6_osf_pal.mar
                  [004DC8]  4886  	RESTORE_REG 26, irn=r1
File: ev6_pal_macros.mar
                  [004DC8]   491M     ASSUME <0+0+0> lt 2
         6F4110E0 [004DC8]   494i 	hw_ldq/p r26, CNS__R26(r1)
File: ev6_osf_pal.mar
                  [004DCC]  4887  	RESTORE_REG 27, irn=r1
File: ev6_pal_macros.mar
                  [004DCC]   491M     ASSUME <0+0+0> lt 2
         6F6110E8 [004DCC]   494i 	hw_ldq/p r27, CNS__R27(r1)
File: ev6_osf_pal.mar
                  [004DD0]  4888  
                  [004DD0]  4889  	RESTORE_REG 28, irn=r1			; buffer block 3
File: ev6_pal_macros.mar
                  [004DD0]   491M     ASSUME <0+0+0> lt 2
         6F8110F0 [004DD0]   494i 	hw_ldq/p r28, CNS__R28(r1)
File: ev6_osf_pal.mar
                  [004DD4]  4890  	RESTORE_REG 29, irn=r1
File: ev6_pal_macros.mar
                  [004DD4]   491M     ASSUME <0+0+0> lt 2
         6FA110F8 [004DD4]   494i 	hw_ldq/p r29, CNS__R29(r1)
File: ev6_osf_pal.mar
                  [004DD8]  4891  	RESTORE_REG 30, irn=r1
File: ev6_pal_macros.mar
                  [004DD8]   491M     ASSUME <0+0+0> lt 2
         6FC11100 [004DD8]   494i 	hw_ldq/p r30, CNS__R30(r1)
File: ev6_osf_pal.mar
         47FF041F [004DDC]  4892  	bis	r31, r31, r31
                  [004DE0]  4893  
                  [004DE0]  4894  	RESTORE_REG 4, irn=r1
File: ev6_pal_macros.mar
                  [004DE0]   491M     ASSUME <0+0+0> lt 2
         6C811030 [004DE0]   494i 	hw_ldq/p r4, CNS__R4(r1)
File: ev6_osf_pal.mar
                  [004DE4]  4895  	RESTORE_REG 5, irn=r1
File: ev6_pal_macros.mar
                  [004DE4]   491M     ASSUME <0+0+0> lt 2
         6CA11038 [004DE4]   494i 	hw_ldq/p r5, CNS__R5(r1)
File: ev6_osf_pal.mar
                  [004DE8]  4896  	RESTORE_REG 6, irn=r1
File: ev6_pal_macros.mar
                  [004DE8]   491M     ASSUME <0+0+0> lt 2
         6CC11040 [004DE8]   494i 	hw_ldq/p r6, CNS__R6(r1)
File: ev6_osf_pal.mar
                  [004DEC]  4897  	RESTORE_REG 7, irn=r1
File: ev6_pal_macros.mar
                  [004DEC]   491M     ASSUME <0+0+0> lt 2
         6CE11048 [004DEC]   494i 	hw_ldq/p r7, CNS__R7(r1)
File: ev6_osf_pal.mar
                  [004DF0]  4898  
                  [004DF0]  4899  	RESTORE_REG 20, irn=r1
File: ev6_pal_macros.mar
                  [004DF0]   491M     ASSUME <0+0+0> lt 2
         6E8110B0 [004DF0]   494i 	hw_ldq/p r20, CNS__R20(r1)
File: ev6_osf_pal.mar
                  [004DF4]  4900  	RESTORE_REG 21, irn=r1
File: ev6_pal_macros.mar
                  [004DF4]   491M     ASSUME <0+0+0> lt 2
         6EA110B8 [004DF4]   494i 	hw_ldq/p r21, CNS__R21(r1)
File: ev6_osf_pal.mar
                  [004DF8]  4901  	RESTORE_REG 22, irn=r1
File: ev6_pal_macros.mar
                  [004DF8]   491M     ASSUME <0+0+0> lt 2
         6EC110C0 [004DF8]   494i 	hw_ldq/p r22, CNS__R22(r1)
File: ev6_osf_pal.mar
                  [004DFC]  4902  	RESTORE_REG 23, irn=r1
File: ev6_pal_macros.mar
                  [004DFC]   491M     ASSUME <0+0+0> lt 2
         6EE110C8 [004DFC]   494i 	hw_ldq/p r23, CNS__R23(r1)
File: ev6_osf_pal.mar
                  [004E00]  4903  ;
                  [004E00]  4904  ; Now turn shadow registers back on.
                  [004E00]  4905  ;
         44101400 [004E00]  4906  	bis	r0, #<1@EV6__I_CTL__SDE7__S>, r0; or in sde
         77E01110 [004E04]  4907  	hw_mtpr	r0, EV6__I_CTL			; (4,0L) write i_ctl
         47FF041F [004E08]  4908  	bis 	r31, r31, r31
         47FF041F [004E0C]  4909  	bis 	r31, r31, r31
                  [004E10]  4910  
         77E01110 [004E10]  4911  	hw_mtpr	r0, EV6__I_CTL			; (4,0L) stall outside IQ
         47FF041F [004E14]  4912  	bis	r31, r31, r31
         47FF041F [004E18]  4913  	bis	r31, r31, r31
         47FF041F [004E1C]  4914  	bis	r31, r31, r31
                  [004E20]  4915  
         44000400 [004E20]  4916  	bis	r0, r0, r0			; buffer block 1
         47FF041F [004E24]  4917  	bis	r31, r31, r31
         47FF041F [004E28]  4918  	bis	r31, r31, r31
         47FF041F [004E2C]  4919  	bis	r31, r31, r31
                  [004E30]  4920  
         44000400 [004E30]  4921  	bis	r0, r0, r0			; buffer block 2
         47FF041F [004E34]  4922  	bis	r31, r31, r31
         47FF041F [004E38]  4923  	bis	r31, r31, r31
         47FF041F [004E3C]  4924  	bis	r31, r31, r31
                  [004E40]  4925  
         44000400 [004E40]  4926  	bis	r0, r0, r0			; buffer block 3
         47FF041F [004E44]  4927  	bis	r31, r31, r31
         47FF041F [004E48]  4928  	bis	r31, r31, r31
         47FF041F [004E4C]  4929  	bis	r31, r31, r31
                  [004E50]  4930  ;
                  [004E50]  4931  ; Now restore r0-r3.
                  [004E50]  4932  ;
         443F0404 [004E50]  4933  	bis	r1, r31, p4			; base of impure area
                  [004E54]  4934  
                  [004E54]  4935  	RESTORE_REG 0, irn=p4			; restore r0
File: ev6_pal_macros.mar
                  [004E54]   491M     ASSUME <0+0+0> lt 2
         6C041010 [004E54]   494i 	hw_ldq/p r0, CNS__R0(p4)
File: ev6_osf_pal.mar
                  [004E58]  4936  	RESTORE_REG 1, irn=p4			; restore r1
File: ev6_pal_macros.mar
                  [004E58]   491M     ASSUME <0+0+0> lt 2
         6C241018 [004E58]   494i 	hw_ldq/p r1, CNS__R1(p4)
File: ev6_osf_pal.mar
                  [004E5C]  4937  	RESTORE_REG 2, irn=p4			; restore r2
File: ev6_pal_macros.mar
                  [004E5C]   491M     ASSUME <0+0+0> lt 2
         6C441020 [004E5C]   494i 	hw_ldq/p r2, CNS__R2(p4)
File: ev6_osf_pal.mar
                  [004E60]  4938  	RESTORE_REG 3, irn=p4			; restore r3
File: ev6_pal_macros.mar
                  [004E60]   491M     ASSUME <0+0+0> lt 2
         6C641028 [004E60]   494i 	hw_ldq/p r3, CNS__R3(p4)
File: ev6_osf_pal.mar
                  [004E64]  4939  ;
                  [004E64]  4940  ; Clear dump flag and return.
                  [004E64]  4941  ;
         7FE41000 [004E64]  4942  	hw_stq/p r31, CNS__FLAG(p4)		; clear dump flag
                  [004E68]  4943  
         44E03407 [004E68]  4944  	bis	p7, #1, p7			; return in pal mode
                  [004E6C]  4945  	PVC_JSR restore_state, bsr=1, dest=1
File: ev6_pal_macros.mar
                  [004E6C]   534i  pvc_lbl \pcv_index, \pcv_jsr_restore_state0, osf, \pcv_jsr_restore_state0_inst
File: ev6_osf_pal.mar
         7BE7A000 [004E6C]  4946  	hw_ret_stall (p7)			; add stall for pvc
                  [004E70]  4947  
                  [004E70]  4948  	END_FREE_CODE
                  [004E70]  4949  
                  [000C00]  4950  	.=^xC00
                  [000C00]  4951  
                  [000C00]  4952  INITIAL_PCBB:
                  [000C00]  4953  	.repeat	8
                  [000C00]  4954  	    .quad 0
                  [000C00]  4955  	.endr
00000000 00000000 [000C00]  4954R 	    .quad 0
00000000 00000000 [000C08]  4954R 		    .quad 0
00000000 00000000 [000C10]  4954R 		    .quad 0
00000000 00000000 [000C18]  4954R 		    .quad 0
00000000 00000000 [000C20]  4954R 		    .quad 0
00000000 00000000 [000C28]  4954R 		    .quad 0
00000000 00000000 [000C30]  4954R 		    .quad 0
00000000 00000000 [000C38]  4954R 		    .quad 0
                  [000C40]  4956  	
                  [000C40]  4957  	ASSUME <.> le <^x0C88> 
                  [000C40]  4958  ;+
                  [000C40]  4959  ; Beginning of CALL_PAL instructions.
                  [000C40]  4960  ;-
                  [000C40]  4961  ;
                  [000C40]  4962  ; HACK ALERT!!!!!!!!!! ??? Bug in HAL!!!!!!! ???
                  [000C40]  4963  ; If this code contains a branch, HAL will later re-compute the branch and
                  [000C40]  4964  ; overwrite the code that was supposed to overwrite this code.
                  [000C40]  4965  ;
                  [000C40]  4966  ; This has been fixed, I think, but leave as is for now.
                  [000C40]  4967  ;
                  [000C40]  4968  ; We should probably also add check for pal mode. (??)
                  [000C40]  4969  ;-
                  [000C40]  4970  
                  [000C40]  4971  opcdec_offset = <<trap__opcdec_call_pal - trap__pal_base>>
                  [000C40]  4972  
                  [002000]  4973  	. = ^x2000
                  [002000]  4974  CALL_PAL__START:
                  [002000]  4975      .if eq add_extra_ret			; 1.47 add_extra_ret
                  [002000]  4976  	.repeat 128
                  [002000]  4977  	hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
                  [002000]  4978  	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
                  [002000]  4979  	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
                  [002000]  4980  	bis	p6, #1, p6			; pal mode
                  [002000]  4981  	bsr	r31, .				; push prediction stack
                  [002000]  4982  	PVC_VIOLATE <1007>
                  [002000]  4983  	hw_ret	(p6)				; pop prediction stack
                  [002000]  4984  						; post
                  [002000]  4985  	.align 6
                  [002000]  4986  	.endr
                  [002000]  4987      .iff					; 1.47 add_extra_ret
                  [002000]  4988  ;
                  [002000]  4989  ; Just delete the bsr to push the stack, and we're all set
                  [002000]  4990  ;
                  [002000]  4991  	.repeat 128
                  [002000]  4992  	hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
                  [002000]  4993  	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
                  [002000]  4994  	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
                  [002000]  4995  	bis	p6, #1, p6			; pal mode
                  [002000]  4996  	PVC_VIOLATE <1007>
                  [002000]  4997  	hw_ret	(p6)				; pop prediction stack
                  [002000]  4998  						; post
                  [002000]  4999  	.align 6
                  [002000]  5000  	.endr
                  [002000]  5001      .endc					; 1.47 add_extra_ret
                  [002000]  4976I 	.repeat 128
                  [002000]  4977I 	hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
                  [002000]  4978I 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
                  [002000]  4979I 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
                  [002000]  4980I 	bis	p6, #1, p6			; pal mode
                  [002000]  4981I 	bsr	r31, .				; push prediction stack
                  [002000]  4982I 	PVC_VIOLATE <1007>
                  [002000]  4983I 	hw_ret	(p6)				; pop prediction stack
                  [002000]  4984I 						; post
                  [002000]  4985I 	.align 6
                  [002000]  4986I 	.endr
         64DF1010 [002000]  4977R 	hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002004]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002008]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00200C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002010]  4981R 	bsr	r31, .				; push prediction stack
                  [002014]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002014]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002014]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002018]  4985R 	.align 6
00000000 00000000 [002020]
00000000 00000000 [002028]
00000000 00000000 [002030]
00000000 00000000 [002038]
         64DF1010 [002040]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002044]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002048]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00204C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002050]  4981R 	bsr	r31, .				; push prediction stack
                  [002054]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002054]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002054]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002058]  4985R 	.align 6
00000000 00000000 [002060]
00000000 00000000 [002068]
00000000 00000000 [002070]
00000000 00000000 [002078]
         64DF1010 [002080]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002084]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002088]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00208C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002090]  4981R 	bsr	r31, .				; push prediction stack
                  [002094]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002094]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002094]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002098]  4985R 	.align 6
00000000 00000000 [0020A0]
00000000 00000000 [0020A8]
00000000 00000000 [0020B0]
00000000 00000000 [0020B8]
         64DF1010 [0020C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0020C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0020C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0020CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0020D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0020D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0020D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0020D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0020D8]  4985R 	.align 6
00000000 00000000 [0020E0]
00000000 00000000 [0020E8]
00000000 00000000 [0020F0]
00000000 00000000 [0020F8]
         64DF1010 [002100]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002104]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002108]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00210C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002110]  4981R 	bsr	r31, .				; push prediction stack
                  [002114]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002114]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002114]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002118]  4985R 	.align 6
00000000 00000000 [002120]
00000000 00000000 [002128]
00000000 00000000 [002130]
00000000 00000000 [002138]
         64DF1010 [002140]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002144]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002148]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00214C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002150]  4981R 	bsr	r31, .				; push prediction stack
                  [002154]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002154]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002154]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002158]  4985R 	.align 6
00000000 00000000 [002160]
00000000 00000000 [002168]
00000000 00000000 [002170]
00000000 00000000 [002178]
         64DF1010 [002180]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002184]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002188]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00218C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002190]  4981R 	bsr	r31, .				; push prediction stack
                  [002194]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002194]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002194]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002198]  4985R 	.align 6
00000000 00000000 [0021A0]
00000000 00000000 [0021A8]
00000000 00000000 [0021B0]
00000000 00000000 [0021B8]
         64DF1010 [0021C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0021C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0021C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0021CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0021D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0021D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0021D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0021D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0021D8]  4985R 	.align 6
00000000 00000000 [0021E0]
00000000 00000000 [0021E8]
00000000 00000000 [0021F0]
00000000 00000000 [0021F8]
         64DF1010 [002200]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002204]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002208]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00220C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002210]  4981R 	bsr	r31, .				; push prediction stack
                  [002214]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002214]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002214]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002218]  4985R 	.align 6
00000000 00000000 [002220]
00000000 00000000 [002228]
00000000 00000000 [002230]
00000000 00000000 [002238]
         64DF1010 [002240]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002244]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002248]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00224C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002250]  4981R 	bsr	r31, .				; push prediction stack
                  [002254]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002254]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002254]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002258]  4985R 	.align 6
00000000 00000000 [002260]
00000000 00000000 [002268]
00000000 00000000 [002270]
00000000 00000000 [002278]
         64DF1010 [002280]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002284]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002288]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00228C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002290]  4981R 	bsr	r31, .				; push prediction stack
                  [002294]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002294]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002294]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002298]  4985R 	.align 6
00000000 00000000 [0022A0]
00000000 00000000 [0022A8]
00000000 00000000 [0022B0]
00000000 00000000 [0022B8]
         64DF1010 [0022C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0022C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0022C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0022CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0022D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0022D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0022D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0022D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0022D8]  4985R 	.align 6
00000000 00000000 [0022E0]
00000000 00000000 [0022E8]
00000000 00000000 [0022F0]
00000000 00000000 [0022F8]
         64DF1010 [002300]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002304]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002308]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00230C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002310]  4981R 	bsr	r31, .				; push prediction stack
                  [002314]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002314]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002314]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002318]  4985R 	.align 6
00000000 00000000 [002320]
00000000 00000000 [002328]
00000000 00000000 [002330]
00000000 00000000 [002338]
         64DF1010 [002340]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002344]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002348]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00234C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002350]  4981R 	bsr	r31, .				; push prediction stack
                  [002354]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002354]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002354]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002358]  4985R 	.align 6
00000000 00000000 [002360]
00000000 00000000 [002368]
00000000 00000000 [002370]
00000000 00000000 [002378]
         64DF1010 [002380]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002384]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002388]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00238C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002390]  4981R 	bsr	r31, .				; push prediction stack
                  [002394]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002394]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002394]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002398]  4985R 	.align 6
00000000 00000000 [0023A0]
00000000 00000000 [0023A8]
00000000 00000000 [0023B0]
00000000 00000000 [0023B8]
         64DF1010 [0023C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0023C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0023C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0023CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0023D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0023D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0023D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0023D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0023D8]  4985R 	.align 6
00000000 00000000 [0023E0]
00000000 00000000 [0023E8]
00000000 00000000 [0023F0]
00000000 00000000 [0023F8]
         64DF1010 [002400]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002404]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002408]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00240C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002410]  4981R 	bsr	r31, .				; push prediction stack
                  [002414]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002414]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002414]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002418]  4985R 	.align 6
00000000 00000000 [002420]
00000000 00000000 [002428]
00000000 00000000 [002430]
00000000 00000000 [002438]
         64DF1010 [002440]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002444]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002448]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00244C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002450]  4981R 	bsr	r31, .				; push prediction stack
                  [002454]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002454]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002454]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002458]  4985R 	.align 6
00000000 00000000 [002460]
00000000 00000000 [002468]
00000000 00000000 [002470]
00000000 00000000 [002478]
         64DF1010 [002480]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002484]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002488]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00248C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002490]  4981R 	bsr	r31, .				; push prediction stack
                  [002494]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002494]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002494]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002498]  4985R 	.align 6
00000000 00000000 [0024A0]
00000000 00000000 [0024A8]
00000000 00000000 [0024B0]
00000000 00000000 [0024B8]
         64DF1010 [0024C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0024C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0024C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0024CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0024D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0024D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0024D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0024D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0024D8]  4985R 	.align 6
00000000 00000000 [0024E0]
00000000 00000000 [0024E8]
00000000 00000000 [0024F0]
00000000 00000000 [0024F8]
         64DF1010 [002500]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002504]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002508]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00250C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002510]  4981R 	bsr	r31, .				; push prediction stack
                  [002514]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002514]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002514]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002518]  4985R 	.align 6
00000000 00000000 [002520]
00000000 00000000 [002528]
00000000 00000000 [002530]
00000000 00000000 [002538]
         64DF1010 [002540]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002544]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002548]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00254C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002550]  4981R 	bsr	r31, .				; push prediction stack
                  [002554]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002554]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002554]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002558]  4985R 	.align 6
00000000 00000000 [002560]
00000000 00000000 [002568]
00000000 00000000 [002570]
00000000 00000000 [002578]
         64DF1010 [002580]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002584]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002588]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00258C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002590]  4981R 	bsr	r31, .				; push prediction stack
                  [002594]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002594]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002594]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002598]  4985R 	.align 6
00000000 00000000 [0025A0]
00000000 00000000 [0025A8]
00000000 00000000 [0025B0]
00000000 00000000 [0025B8]
         64DF1010 [0025C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0025C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0025C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0025CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0025D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0025D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0025D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0025D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0025D8]  4985R 	.align 6
00000000 00000000 [0025E0]
00000000 00000000 [0025E8]
00000000 00000000 [0025F0]
00000000 00000000 [0025F8]
         64DF1010 [002600]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002604]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002608]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00260C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002610]  4981R 	bsr	r31, .				; push prediction stack
                  [002614]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002614]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002614]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002618]  4985R 	.align 6
00000000 00000000 [002620]
00000000 00000000 [002628]
00000000 00000000 [002630]
00000000 00000000 [002638]
         64DF1010 [002640]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002644]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002648]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00264C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002650]  4981R 	bsr	r31, .				; push prediction stack
                  [002654]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002654]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002654]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002658]  4985R 	.align 6
00000000 00000000 [002660]
00000000 00000000 [002668]
00000000 00000000 [002670]
00000000 00000000 [002678]
         64DF1010 [002680]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002684]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002688]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00268C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002690]  4981R 	bsr	r31, .				; push prediction stack
                  [002694]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002694]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002694]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002698]  4985R 	.align 6
00000000 00000000 [0026A0]
00000000 00000000 [0026A8]
00000000 00000000 [0026B0]
00000000 00000000 [0026B8]
         64DF1010 [0026C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0026C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0026C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0026CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0026D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0026D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0026D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0026D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0026D8]  4985R 	.align 6
00000000 00000000 [0026E0]
00000000 00000000 [0026E8]
00000000 00000000 [0026F0]
00000000 00000000 [0026F8]
         64DF1010 [002700]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002704]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002708]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00270C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002710]  4981R 	bsr	r31, .				; push prediction stack
                  [002714]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002714]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002714]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002718]  4985R 	.align 6
00000000 00000000 [002720]
00000000 00000000 [002728]
00000000 00000000 [002730]
00000000 00000000 [002738]
         64DF1010 [002740]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002744]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002748]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00274C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002750]  4981R 	bsr	r31, .				; push prediction stack
                  [002754]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002754]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002754]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002758]  4985R 	.align 6
00000000 00000000 [002760]
00000000 00000000 [002768]
00000000 00000000 [002770]
00000000 00000000 [002778]
         64DF1010 [002780]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002784]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002788]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00278C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002790]  4981R 	bsr	r31, .				; push prediction stack
                  [002794]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002794]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002794]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002798]  4985R 	.align 6
00000000 00000000 [0027A0]
00000000 00000000 [0027A8]
00000000 00000000 [0027B0]
00000000 00000000 [0027B8]
         64DF1010 [0027C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0027C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0027C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0027CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0027D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0027D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0027D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0027D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0027D8]  4985R 	.align 6
00000000 00000000 [0027E0]
00000000 00000000 [0027E8]
00000000 00000000 [0027F0]
00000000 00000000 [0027F8]
         64DF1010 [002800]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002804]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002808]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00280C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002810]  4981R 	bsr	r31, .				; push prediction stack
                  [002814]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002814]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002814]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002818]  4985R 	.align 6
00000000 00000000 [002820]
00000000 00000000 [002828]
00000000 00000000 [002830]
00000000 00000000 [002838]
         64DF1010 [002840]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002844]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002848]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00284C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002850]  4981R 	bsr	r31, .				; push prediction stack
                  [002854]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002854]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002854]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002858]  4985R 	.align 6
00000000 00000000 [002860]
00000000 00000000 [002868]
00000000 00000000 [002870]
00000000 00000000 [002878]
         64DF1010 [002880]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002884]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002888]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00288C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002890]  4981R 	bsr	r31, .				; push prediction stack
                  [002894]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002894]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002894]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002898]  4985R 	.align 6
00000000 00000000 [0028A0]
00000000 00000000 [0028A8]
00000000 00000000 [0028B0]
00000000 00000000 [0028B8]
         64DF1010 [0028C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0028C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0028C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0028CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0028D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0028D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0028D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0028D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0028D8]  4985R 	.align 6
00000000 00000000 [0028E0]
00000000 00000000 [0028E8]
00000000 00000000 [0028F0]
00000000 00000000 [0028F8]
         64DF1010 [002900]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002904]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002908]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00290C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002910]  4981R 	bsr	r31, .				; push prediction stack
                  [002914]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002914]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002914]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002918]  4985R 	.align 6
00000000 00000000 [002920]
00000000 00000000 [002928]
00000000 00000000 [002930]
00000000 00000000 [002938]
         64DF1010 [002940]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002944]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002948]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00294C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002950]  4981R 	bsr	r31, .				; push prediction stack
                  [002954]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002954]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002954]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002958]  4985R 	.align 6
00000000 00000000 [002960]
00000000 00000000 [002968]
00000000 00000000 [002970]
00000000 00000000 [002978]
         64DF1010 [002980]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002984]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002988]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00298C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002990]  4981R 	bsr	r31, .				; push prediction stack
                  [002994]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002994]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002994]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002998]  4985R 	.align 6
00000000 00000000 [0029A0]
00000000 00000000 [0029A8]
00000000 00000000 [0029B0]
00000000 00000000 [0029B8]
         64DF1010 [0029C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0029C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0029C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0029CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0029D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0029D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0029D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0029D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0029D8]  4985R 	.align 6
00000000 00000000 [0029E0]
00000000 00000000 [0029E8]
00000000 00000000 [0029F0]
00000000 00000000 [0029F8]
         64DF1010 [002A00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002A04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002A08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002A0C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002A10]  4981R 	bsr	r31, .				; push prediction stack
                  [002A14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002A14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002A14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002A18]  4985R 	.align 6
00000000 00000000 [002A20]
00000000 00000000 [002A28]
00000000 00000000 [002A30]
00000000 00000000 [002A38]
         64DF1010 [002A40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002A44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002A48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002A4C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002A50]  4981R 	bsr	r31, .				; push prediction stack
                  [002A54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002A54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002A54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002A58]  4985R 	.align 6
00000000 00000000 [002A60]
00000000 00000000 [002A68]
00000000 00000000 [002A70]
00000000 00000000 [002A78]
         64DF1010 [002A80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002A84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002A88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002A8C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002A90]  4981R 	bsr	r31, .				; push prediction stack
                  [002A94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002A94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002A94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002A98]  4985R 	.align 6
00000000 00000000 [002AA0]
00000000 00000000 [002AA8]
00000000 00000000 [002AB0]
00000000 00000000 [002AB8]
         64DF1010 [002AC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002AC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002AC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002ACC]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002AD0]  4981R 	bsr	r31, .				; push prediction stack
                  [002AD4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002AD4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002AD4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002AD8]  4985R 	.align 6
00000000 00000000 [002AE0]
00000000 00000000 [002AE8]
00000000 00000000 [002AF0]
00000000 00000000 [002AF8]
         64DF1010 [002B00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002B04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002B08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002B0C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002B10]  4981R 	bsr	r31, .				; push prediction stack
                  [002B14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002B14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002B14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002B18]  4985R 	.align 6
00000000 00000000 [002B20]
00000000 00000000 [002B28]
00000000 00000000 [002B30]
00000000 00000000 [002B38]
         64DF1010 [002B40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002B44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002B48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002B4C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002B50]  4981R 	bsr	r31, .				; push prediction stack
                  [002B54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002B54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002B54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002B58]  4985R 	.align 6
00000000 00000000 [002B60]
00000000 00000000 [002B68]
00000000 00000000 [002B70]
00000000 00000000 [002B78]
         64DF1010 [002B80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002B84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002B88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002B8C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002B90]  4981R 	bsr	r31, .				; push prediction stack
                  [002B94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002B94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002B94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002B98]  4985R 	.align 6
00000000 00000000 [002BA0]
00000000 00000000 [002BA8]
00000000 00000000 [002BB0]
00000000 00000000 [002BB8]
         64DF1010 [002BC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002BC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002BC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002BCC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002BD0]  4981R 	bsr	r31, .				; push prediction stack
                  [002BD4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002BD4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002BD4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002BD8]  4985R 	.align 6
00000000 00000000 [002BE0]
00000000 00000000 [002BE8]
00000000 00000000 [002BF0]
00000000 00000000 [002BF8]
         64DF1010 [002C00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002C04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002C08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002C0C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002C10]  4981R 	bsr	r31, .				; push prediction stack
                  [002C14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002C14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002C14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002C18]  4985R 	.align 6
00000000 00000000 [002C20]
00000000 00000000 [002C28]
00000000 00000000 [002C30]
00000000 00000000 [002C38]
         64DF1010 [002C40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002C44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002C48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002C4C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002C50]  4981R 	bsr	r31, .				; push prediction stack
                  [002C54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002C54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002C54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002C58]  4985R 	.align 6
00000000 00000000 [002C60]
00000000 00000000 [002C68]
00000000 00000000 [002C70]
00000000 00000000 [002C78]
         64DF1010 [002C80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002C84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002C88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002C8C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002C90]  4981R 	bsr	r31, .				; push prediction stack
                  [002C94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002C94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002C94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002C98]  4985R 	.align 6
00000000 00000000 [002CA0]
00000000 00000000 [002CA8]
00000000 00000000 [002CB0]
00000000 00000000 [002CB8]
         64DF1010 [002CC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002CC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002CC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002CCC]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002CD0]  4981R 	bsr	r31, .				; push prediction stack
                  [002CD4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002CD4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002CD4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002CD8]  4985R 	.align 6
00000000 00000000 [002CE0]
00000000 00000000 [002CE8]
00000000 00000000 [002CF0]
00000000 00000000 [002CF8]
         64DF1010 [002D00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002D04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002D08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002D0C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002D10]  4981R 	bsr	r31, .				; push prediction stack
                  [002D14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002D14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002D14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002D18]  4985R 	.align 6
00000000 00000000 [002D20]
00000000 00000000 [002D28]
00000000 00000000 [002D30]
00000000 00000000 [002D38]
         64DF1010 [002D40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002D44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002D48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002D4C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002D50]  4981R 	bsr	r31, .				; push prediction stack
                  [002D54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002D54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002D54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002D58]  4985R 	.align 6
00000000 00000000 [002D60]
00000000 00000000 [002D68]
00000000 00000000 [002D70]
00000000 00000000 [002D78]
         64DF1010 [002D80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002D84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002D88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002D8C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002D90]  4981R 	bsr	r31, .				; push prediction stack
                  [002D94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002D94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002D94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002D98]  4985R 	.align 6
00000000 00000000 [002DA0]
00000000 00000000 [002DA8]
00000000 00000000 [002DB0]
00000000 00000000 [002DB8]
         64DF1010 [002DC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002DC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002DC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002DCC]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002DD0]  4981R 	bsr	r31, .				; push prediction stack
                  [002DD4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002DD4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002DD4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002DD8]  4985R 	.align 6
00000000 00000000 [002DE0]
00000000 00000000 [002DE8]
00000000 00000000 [002DF0]
00000000 00000000 [002DF8]
         64DF1010 [002E00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002E04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002E08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002E0C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002E10]  4981R 	bsr	r31, .				; push prediction stack
                  [002E14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002E14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002E14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002E18]  4985R 	.align 6
00000000 00000000 [002E20]
00000000 00000000 [002E28]
00000000 00000000 [002E30]
00000000 00000000 [002E38]
         64DF1010 [002E40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002E44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002E48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002E4C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002E50]  4981R 	bsr	r31, .				; push prediction stack
                  [002E54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002E54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002E54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002E58]  4985R 	.align 6
00000000 00000000 [002E60]
00000000 00000000 [002E68]
00000000 00000000 [002E70]
00000000 00000000 [002E78]
         64DF1010 [002E80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002E84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002E88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002E8C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002E90]  4981R 	bsr	r31, .				; push prediction stack
                  [002E94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002E94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002E94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002E98]  4985R 	.align 6
00000000 00000000 [002EA0]
00000000 00000000 [002EA8]
00000000 00000000 [002EB0]
00000000 00000000 [002EB8]
         64DF1010 [002EC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002EC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002EC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002ECC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002ED0]  4981R 	bsr	r31, .				; push prediction stack
                  [002ED4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002ED4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002ED4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002ED8]  4985R 	.align 6
00000000 00000000 [002EE0]
00000000 00000000 [002EE8]
00000000 00000000 [002EF0]
00000000 00000000 [002EF8]
         64DF1010 [002F00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002F04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002F08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002F0C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002F10]  4981R 	bsr	r31, .				; push prediction stack
                  [002F14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002F14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002F14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002F18]  4985R 	.align 6
00000000 00000000 [002F20]
00000000 00000000 [002F28]
00000000 00000000 [002F30]
00000000 00000000 [002F38]
         64DF1010 [002F40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002F44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002F48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002F4C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002F50]  4981R 	bsr	r31, .				; push prediction stack
                  [002F54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002F54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002F54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002F58]  4985R 	.align 6
00000000 00000000 [002F60]
00000000 00000000 [002F68]
00000000 00000000 [002F70]
00000000 00000000 [002F78]
         64DF1010 [002F80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002F84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002F88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002F8C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [002F90]  4981R 	bsr	r31, .				; push prediction stack
                  [002F94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002F94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002F94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002F98]  4985R 	.align 6
00000000 00000000 [002FA0]
00000000 00000000 [002FA8]
00000000 00000000 [002FB0]
00000000 00000000 [002FB8]
         64DF1010 [002FC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [002FC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [002FC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [002FCC]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [002FD0]  4981R 	bsr	r31, .				; push prediction stack
                  [002FD4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [002FD4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [002FD4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [002FD8]  4985R 	.align 6
00000000 00000000 [002FE0]
00000000 00000000 [002FE8]
00000000 00000000 [002FF0]
00000000 00000000 [002FF8]
         64DF1010 [003000]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003004]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003008]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00300C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003010]  4981R 	bsr	r31, .				; push prediction stack
                  [003014]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003014]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003014]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003018]  4985R 	.align 6
00000000 00000000 [003020]
00000000 00000000 [003028]
00000000 00000000 [003030]
00000000 00000000 [003038]
         64DF1010 [003040]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003044]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003048]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00304C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003050]  4981R 	bsr	r31, .				; push prediction stack
                  [003054]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003054]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003054]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003058]  4985R 	.align 6
00000000 00000000 [003060]
00000000 00000000 [003068]
00000000 00000000 [003070]
00000000 00000000 [003078]
         64DF1010 [003080]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003084]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003088]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00308C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003090]  4981R 	bsr	r31, .				; push prediction stack
                  [003094]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003094]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003094]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003098]  4985R 	.align 6
00000000 00000000 [0030A0]
00000000 00000000 [0030A8]
00000000 00000000 [0030B0]
00000000 00000000 [0030B8]
         64DF1010 [0030C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0030C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0030C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0030CC]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [0030D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0030D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0030D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0030D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0030D8]  4985R 	.align 6
00000000 00000000 [0030E0]
00000000 00000000 [0030E8]
00000000 00000000 [0030F0]
00000000 00000000 [0030F8]
         64DF1010 [003100]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003104]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003108]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00310C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003110]  4981R 	bsr	r31, .				; push prediction stack
                  [003114]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003114]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003114]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003118]  4985R 	.align 6
00000000 00000000 [003120]
00000000 00000000 [003128]
00000000 00000000 [003130]
00000000 00000000 [003138]
         64DF1010 [003140]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003144]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003148]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00314C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003150]  4981R 	bsr	r31, .				; push prediction stack
                  [003154]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003154]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003154]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003158]  4985R 	.align 6
00000000 00000000 [003160]
00000000 00000000 [003168]
00000000 00000000 [003170]
00000000 00000000 [003178]
         64DF1010 [003180]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003184]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003188]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00318C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [003190]  4981R 	bsr	r31, .				; push prediction stack
                  [003194]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003194]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003194]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003198]  4985R 	.align 6
00000000 00000000 [0031A0]
00000000 00000000 [0031A8]
00000000 00000000 [0031B0]
00000000 00000000 [0031B8]
         64DF1010 [0031C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0031C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0031C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0031CC]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [0031D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0031D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0031D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0031D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0031D8]  4985R 	.align 6
00000000 00000000 [0031E0]
00000000 00000000 [0031E8]
00000000 00000000 [0031F0]
00000000 00000000 [0031F8]
         64DF1010 [003200]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003204]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003208]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00320C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003210]  4981R 	bsr	r31, .				; push prediction stack
                  [003214]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003214]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003214]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003218]  4985R 	.align 6
00000000 00000000 [003220]
00000000 00000000 [003228]
00000000 00000000 [003230]
00000000 00000000 [003238]
         64DF1010 [003240]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003244]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003248]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00324C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003250]  4981R 	bsr	r31, .				; push prediction stack
                  [003254]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003254]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003254]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003258]  4985R 	.align 6
00000000 00000000 [003260]
00000000 00000000 [003268]
00000000 00000000 [003270]
00000000 00000000 [003278]
         64DF1010 [003280]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003284]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003288]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00328C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003290]  4981R 	bsr	r31, .				; push prediction stack
                  [003294]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003294]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003294]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003298]  4985R 	.align 6
00000000 00000000 [0032A0]
00000000 00000000 [0032A8]
00000000 00000000 [0032B0]
00000000 00000000 [0032B8]
         64DF1010 [0032C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0032C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0032C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0032CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0032D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0032D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0032D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0032D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0032D8]  4985R 	.align 6
00000000 00000000 [0032E0]
00000000 00000000 [0032E8]
00000000 00000000 [0032F0]
00000000 00000000 [0032F8]
         64DF1010 [003300]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003304]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003308]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00330C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003310]  4981R 	bsr	r31, .				; push prediction stack
                  [003314]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003314]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003314]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003318]  4985R 	.align 6
00000000 00000000 [003320]
00000000 00000000 [003328]
00000000 00000000 [003330]
00000000 00000000 [003338]
         64DF1010 [003340]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003344]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003348]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00334C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003350]  4981R 	bsr	r31, .				; push prediction stack
                  [003354]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003354]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003354]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003358]  4985R 	.align 6
00000000 00000000 [003360]
00000000 00000000 [003368]
00000000 00000000 [003370]
00000000 00000000 [003378]
         64DF1010 [003380]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003384]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003388]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00338C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003390]  4981R 	bsr	r31, .				; push prediction stack
                  [003394]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003394]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003394]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003398]  4985R 	.align 6
00000000 00000000 [0033A0]
00000000 00000000 [0033A8]
00000000 00000000 [0033B0]
00000000 00000000 [0033B8]
         64DF1010 [0033C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0033C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0033C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0033CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0033D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0033D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0033D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0033D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0033D8]  4985R 	.align 6
00000000 00000000 [0033E0]
00000000 00000000 [0033E8]
00000000 00000000 [0033F0]
00000000 00000000 [0033F8]
         64DF1010 [003400]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003404]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003408]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00340C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003410]  4981R 	bsr	r31, .				; push prediction stack
                  [003414]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003414]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003414]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003418]  4985R 	.align 6
00000000 00000000 [003420]
00000000 00000000 [003428]
00000000 00000000 [003430]
00000000 00000000 [003438]
         64DF1010 [003440]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003444]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003448]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00344C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003450]  4981R 	bsr	r31, .				; push prediction stack
                  [003454]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003454]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003454]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003458]  4985R 	.align 6
00000000 00000000 [003460]
00000000 00000000 [003468]
00000000 00000000 [003470]
00000000 00000000 [003478]
         64DF1010 [003480]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003484]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003488]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00348C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [003490]  4981R 	bsr	r31, .				; push prediction stack
                  [003494]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003494]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003494]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003498]  4985R 	.align 6
00000000 00000000 [0034A0]
00000000 00000000 [0034A8]
00000000 00000000 [0034B0]
00000000 00000000 [0034B8]
         64DF1010 [0034C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0034C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0034C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0034CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0034D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0034D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0034D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0034D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0034D8]  4985R 	.align 6
00000000 00000000 [0034E0]
00000000 00000000 [0034E8]
00000000 00000000 [0034F0]
00000000 00000000 [0034F8]
         64DF1010 [003500]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003504]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003508]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00350C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003510]  4981R 	bsr	r31, .				; push prediction stack
                  [003514]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003514]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003514]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003518]  4985R 	.align 6
00000000 00000000 [003520]
00000000 00000000 [003528]
00000000 00000000 [003530]
00000000 00000000 [003538]
         64DF1010 [003540]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003544]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003548]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00354C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003550]  4981R 	bsr	r31, .				; push prediction stack
                  [003554]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003554]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003554]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003558]  4985R 	.align 6
00000000 00000000 [003560]
00000000 00000000 [003568]
00000000 00000000 [003570]
00000000 00000000 [003578]
         64DF1010 [003580]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003584]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003588]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00358C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003590]  4981R 	bsr	r31, .				; push prediction stack
                  [003594]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003594]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003594]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003598]  4985R 	.align 6
00000000 00000000 [0035A0]
00000000 00000000 [0035A8]
00000000 00000000 [0035B0]
00000000 00000000 [0035B8]
         64DF1010 [0035C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0035C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0035C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0035CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0035D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0035D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0035D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0035D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0035D8]  4985R 	.align 6
00000000 00000000 [0035E0]
00000000 00000000 [0035E8]
00000000 00000000 [0035F0]
00000000 00000000 [0035F8]
         64DF1010 [003600]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003604]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003608]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00360C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003610]  4981R 	bsr	r31, .				; push prediction stack
                  [003614]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003614]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003614]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003618]  4985R 	.align 6
00000000 00000000 [003620]
00000000 00000000 [003628]
00000000 00000000 [003630]
00000000 00000000 [003638]
         64DF1010 [003640]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003644]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003648]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00364C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003650]  4981R 	bsr	r31, .				; push prediction stack
                  [003654]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003654]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003654]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003658]  4985R 	.align 6
00000000 00000000 [003660]
00000000 00000000 [003668]
00000000 00000000 [003670]
00000000 00000000 [003678]
         64DF1010 [003680]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003684]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003688]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00368C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003690]  4981R 	bsr	r31, .				; push prediction stack
                  [003694]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003694]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003694]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003698]  4985R 	.align 6
00000000 00000000 [0036A0]
00000000 00000000 [0036A8]
00000000 00000000 [0036B0]
00000000 00000000 [0036B8]
         64DF1010 [0036C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0036C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0036C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0036CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0036D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0036D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0036D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0036D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0036D8]  4985R 	.align 6
00000000 00000000 [0036E0]
00000000 00000000 [0036E8]
00000000 00000000 [0036F0]
00000000 00000000 [0036F8]
         64DF1010 [003700]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003704]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003708]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00370C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003710]  4981R 	bsr	r31, .				; push prediction stack
                  [003714]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003714]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003714]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003718]  4985R 	.align 6
00000000 00000000 [003720]
00000000 00000000 [003728]
00000000 00000000 [003730]
00000000 00000000 [003738]
         64DF1010 [003740]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003744]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003748]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00374C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003750]  4981R 	bsr	r31, .				; push prediction stack
                  [003754]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003754]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003754]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003758]  4985R 	.align 6
00000000 00000000 [003760]
00000000 00000000 [003768]
00000000 00000000 [003770]
00000000 00000000 [003778]
         64DF1010 [003780]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003784]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003788]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00378C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [003790]  4981R 	bsr	r31, .				; push prediction stack
                  [003794]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003794]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003794]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003798]  4985R 	.align 6
00000000 00000000 [0037A0]
00000000 00000000 [0037A8]
00000000 00000000 [0037B0]
00000000 00000000 [0037B8]
         64DF1010 [0037C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0037C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0037C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0037CC]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [0037D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0037D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0037D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0037D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0037D8]  4985R 	.align 6
00000000 00000000 [0037E0]
00000000 00000000 [0037E8]
00000000 00000000 [0037F0]
00000000 00000000 [0037F8]
         64DF1010 [003800]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003804]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003808]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00380C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003810]  4981R 	bsr	r31, .				; push prediction stack
                  [003814]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003814]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003814]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003818]  4985R 	.align 6
00000000 00000000 [003820]
00000000 00000000 [003828]
00000000 00000000 [003830]
00000000 00000000 [003838]
         64DF1010 [003840]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003844]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003848]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00384C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003850]  4981R 	bsr	r31, .				; push prediction stack
                  [003854]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003854]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003854]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003858]  4985R 	.align 6
00000000 00000000 [003860]
00000000 00000000 [003868]
00000000 00000000 [003870]
00000000 00000000 [003878]
         64DF1010 [003880]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003884]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003888]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00388C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003890]  4981R 	bsr	r31, .				; push prediction stack
                  [003894]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003894]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003894]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003898]  4985R 	.align 6
00000000 00000000 [0038A0]
00000000 00000000 [0038A8]
00000000 00000000 [0038B0]
00000000 00000000 [0038B8]
         64DF1010 [0038C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0038C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0038C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0038CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0038D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0038D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0038D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0038D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0038D8]  4985R 	.align 6
00000000 00000000 [0038E0]
00000000 00000000 [0038E8]
00000000 00000000 [0038F0]
00000000 00000000 [0038F8]
         64DF1010 [003900]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003904]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003908]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00390C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003910]  4981R 	bsr	r31, .				; push prediction stack
                  [003914]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003914]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003914]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003918]  4985R 	.align 6
00000000 00000000 [003920]
00000000 00000000 [003928]
00000000 00000000 [003930]
00000000 00000000 [003938]
         64DF1010 [003940]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003944]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003948]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00394C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003950]  4981R 	bsr	r31, .				; push prediction stack
                  [003954]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003954]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003954]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003958]  4985R 	.align 6
00000000 00000000 [003960]
00000000 00000000 [003968]
00000000 00000000 [003970]
00000000 00000000 [003978]
         64DF1010 [003980]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003984]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003988]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [00398C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003990]  4981R 	bsr	r31, .				; push prediction stack
                  [003994]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003994]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003994]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003998]  4985R 	.align 6
00000000 00000000 [0039A0]
00000000 00000000 [0039A8]
00000000 00000000 [0039B0]
00000000 00000000 [0039B8]
         64DF1010 [0039C0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [0039C4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [0039C8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [0039CC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [0039D0]  4981R 	bsr	r31, .				; push prediction stack
                  [0039D4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0039D4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [0039D4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [0039D8]  4985R 	.align 6
00000000 00000000 [0039E0]
00000000 00000000 [0039E8]
00000000 00000000 [0039F0]
00000000 00000000 [0039F8]
         64DF1010 [003A00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003A04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003A08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003A0C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003A10]  4981R 	bsr	r31, .				; push prediction stack
                  [003A14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003A14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003A14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003A18]  4985R 	.align 6
00000000 00000000 [003A20]
00000000 00000000 [003A28]
00000000 00000000 [003A30]
00000000 00000000 [003A38]
         64DF1010 [003A40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003A44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003A48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003A4C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003A50]  4981R 	bsr	r31, .				; push prediction stack
                  [003A54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003A54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003A54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003A58]  4985R 	.align 6
00000000 00000000 [003A60]
00000000 00000000 [003A68]
00000000 00000000 [003A70]
00000000 00000000 [003A78]
         64DF1010 [003A80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003A84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003A88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003A8C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003A90]  4981R 	bsr	r31, .				; push prediction stack
                  [003A94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003A94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003A94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003A98]  4985R 	.align 6
00000000 00000000 [003AA0]
00000000 00000000 [003AA8]
00000000 00000000 [003AB0]
00000000 00000000 [003AB8]
         64DF1010 [003AC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003AC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003AC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003ACC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003AD0]  4981R 	bsr	r31, .				; push prediction stack
                  [003AD4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003AD4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003AD4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003AD8]  4985R 	.align 6
00000000 00000000 [003AE0]
00000000 00000000 [003AE8]
00000000 00000000 [003AF0]
00000000 00000000 [003AF8]
         64DF1010 [003B00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003B04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003B08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003B0C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003B10]  4981R 	bsr	r31, .				; push prediction stack
                  [003B14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003B14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003B14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003B18]  4985R 	.align 6
00000000 00000000 [003B20]
00000000 00000000 [003B28]
00000000 00000000 [003B30]
00000000 00000000 [003B38]
         64DF1010 [003B40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003B44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003B48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003B4C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003B50]  4981R 	bsr	r31, .				; push prediction stack
                  [003B54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003B54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003B54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003B58]  4985R 	.align 6
00000000 00000000 [003B60]
00000000 00000000 [003B68]
00000000 00000000 [003B70]
00000000 00000000 [003B78]
         64DF1010 [003B80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003B84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003B88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003B8C]  4980R 	bis	p6, #1, p6			; pal mode
         xxxxxxxx [003B90]  4981R 	bsr	r31, .				; push prediction stack
                  [003B94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003B94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003B94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003B98]  4985R 	.align 6
00000000 00000000 [003BA0]
00000000 00000000 [003BA8]
00000000 00000000 [003BB0]
00000000 00000000 [003BB8]
         64DF1010 [003BC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003BC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003BC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003BCC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003BD0]  4981R 	bsr	r31, .				; push prediction stack
                  [003BD4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003BD4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003BD4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003BD8]  4985R 	.align 6
00000000 00000000 [003BE0]
00000000 00000000 [003BE8]
00000000 00000000 [003BF0]
00000000 00000000 [003BF8]
         64DF1010 [003C00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003C04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003C08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003C0C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003C10]  4981R 	bsr	r31, .				; push prediction stack
                  [003C14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003C14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003C14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003C18]  4985R 	.align 6
00000000 00000000 [003C20]
00000000 00000000 [003C28]
00000000 00000000 [003C30]
00000000 00000000 [003C38]
         64DF1010 [003C40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003C44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003C48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003C4C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003C50]  4981R 	bsr	r31, .				; push prediction stack
                  [003C54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003C54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003C54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003C58]  4985R 	.align 6
00000000 00000000 [003C60]
00000000 00000000 [003C68]
00000000 00000000 [003C70]
00000000 00000000 [003C78]
         64DF1010 [003C80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003C84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003C88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003C8C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003C90]  4981R 	bsr	r31, .				; push prediction stack
                  [003C94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003C94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003C94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003C98]  4985R 	.align 6
00000000 00000000 [003CA0]
00000000 00000000 [003CA8]
00000000 00000000 [003CB0]
00000000 00000000 [003CB8]
         64DF1010 [003CC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003CC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003CC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003CCC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003CD0]  4981R 	bsr	r31, .				; push prediction stack
                  [003CD4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003CD4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003CD4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003CD8]  4985R 	.align 6
00000000 00000000 [003CE0]
00000000 00000000 [003CE8]
00000000 00000000 [003CF0]
00000000 00000000 [003CF8]
         64DF1010 [003D00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003D04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003D08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003D0C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003D10]  4981R 	bsr	r31, .				; push prediction stack
                  [003D14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003D14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003D14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003D18]  4985R 	.align 6
00000000 00000000 [003D20]
00000000 00000000 [003D28]
00000000 00000000 [003D30]
00000000 00000000 [003D38]
         64DF1010 [003D40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003D44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003D48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003D4C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003D50]  4981R 	bsr	r31, .				; push prediction stack
                  [003D54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003D54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003D54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003D58]  4985R 	.align 6
00000000 00000000 [003D60]
00000000 00000000 [003D68]
00000000 00000000 [003D70]
00000000 00000000 [003D78]
         64DF1010 [003D80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003D84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003D88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003D8C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003D90]  4981R 	bsr	r31, .				; push prediction stack
                  [003D94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003D94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003D94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003D98]  4985R 	.align 6
00000000 00000000 [003DA0]
00000000 00000000 [003DA8]
00000000 00000000 [003DB0]
00000000 00000000 [003DB8]
         64DF1010 [003DC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003DC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003DC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003DCC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003DD0]  4981R 	bsr	r31, .				; push prediction stack
                  [003DD4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003DD4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003DD4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003DD8]  4985R 	.align 6
00000000 00000000 [003DE0]
00000000 00000000 [003DE8]
00000000 00000000 [003DF0]
00000000 00000000 [003DF8]
         64DF1010 [003E00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003E04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003E08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003E0C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003E10]  4981R 	bsr	r31, .				; push prediction stack
                  [003E14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003E14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003E14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003E18]  4985R 	.align 6
00000000 00000000 [003E20]
00000000 00000000 [003E28]
00000000 00000000 [003E30]
00000000 00000000 [003E38]
         64DF1010 [003E40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003E44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003E48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003E4C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003E50]  4981R 	bsr	r31, .				; push prediction stack
                  [003E54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003E54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003E54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003E58]  4985R 	.align 6
00000000 00000000 [003E60]
00000000 00000000 [003E68]
00000000 00000000 [003E70]
00000000 00000000 [003E78]
         64DF1010 [003E80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003E84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003E88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003E8C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003E90]  4981R 	bsr	r31, .				; push prediction stack
                  [003E94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003E94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003E94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003E98]  4985R 	.align 6
00000000 00000000 [003EA0]
00000000 00000000 [003EA8]
00000000 00000000 [003EB0]
00000000 00000000 [003EB8]
         64DF1010 [003EC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003EC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003EC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003ECC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003ED0]  4981R 	bsr	r31, .				; push prediction stack
                  [003ED4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003ED4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003ED4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003ED8]  4985R 	.align 6
00000000 00000000 [003EE0]
00000000 00000000 [003EE8]
00000000 00000000 [003EF0]
00000000 00000000 [003EF8]
         64DF1010 [003F00]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003F04]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003F08]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003F0C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003F10]  4981R 	bsr	r31, .				; push prediction stack
                  [003F14]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003F14]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003F14]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003F18]  4985R 	.align 6
00000000 00000000 [003F20]
00000000 00000000 [003F28]
00000000 00000000 [003F30]
00000000 00000000 [003F38]
         64DF1010 [003F40]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003F44]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003F48]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003F4C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003F50]  4981R 	bsr	r31, .				; push prediction stack
                  [003F54]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003F54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003F54]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003F58]  4985R 	.align 6
00000000 00000000 [003F60]
00000000 00000000 [003F68]
00000000 00000000 [003F70]
00000000 00000000 [003F78]
         64DF1010 [003F80]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003F84]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003F88]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003F8C]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003F90]  4981R 	bsr	r31, .				; push prediction stack
                  [003F94]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003F94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003F94]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003F98]  4985R 	.align 6
00000000 00000000 [003FA0]
00000000 00000000 [003FA8]
00000000 00000000 [003FB0]
00000000 00000000 [003FB8]
         64DF1010 [003FC0]  4977R 		hw_mfpr	p6, EV6__PAL_BASE		; (4,0L) need pal base
         24C60000 [003FC4]  4978R 	ldah	p6,<<opcdec_offset>+32768>@-16(p6)
         20C60418 [003FC8]  4979R 	lda	p6,<<opcdec_offset> & ^xFFFF>(p6)
         44C03406 [003FCC]  4980R 	bis	p6, #1, p6			; pal mode
         D3E00000 [003FD0]  4981R 	bsr	r31, .				; push prediction stack
                  [003FD4]  4982R 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [003FD4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE68000 [003FD4]  4983R 	hw_ret	(p6)				; pop prediction stack
00000000 00000000 [003FD8]  4985R 	.align 6
00000000 00000000 [003FE0]
00000000 00000000 [003FE8]
00000000 00000000 [003FF0]
00000000 00000000 [003FF8]
                  [004000]  5002  	    
                  [004000]  5003  	GOTO_FREE_CODE
File: ev6_pal_macros.mar
00000000 00000000 [004E70]    67M     .align 6
00000000 00000000 [004E78]
File: ev6_osf_pal.mar
                  [004E80]  5004  
                  [004E80]  5005  ;+
                  [004E80]  5006  ; CALL_PAL__HALT -- PALcode for halt instruction
                  [004E80]  5007  ;
                  [004E80]  5008  ; Entry:
                  [004E80]  5009  ;	p23	pc of instruction following the call_pal instruction
                  [004E80]  5010  ;
                  [004E80]  5011  ; Function:
                  [004E80]  5012  ;	Set PT__HALT_CODE to HALT__SW_HALT. Decrement pc in p23,
                  [004E80]  5013  ;	and branch off to save PCB and enter console.
                  [004E80]  5014  ;
                  [004E80]  5015  ; Exit state:
                  [004E80]  5016  ;	PT__HALT_CODE	HALT__SW_HALT
                  [004E80]  5017  ;	p23		pc of halt instruction
                  [004E80]  5018  ;-
                  [004E80]  5019  	START_CALL_PAL <HALT>
File: ev6_pal_macros.mar
                  [004E80]   104i         ASSUME <<OSFPAL_FUNC__HALT> & <^x40>> eq 0
                  [004E80]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002000]   120i CALL_PAL__HALT::
File: ev6_osf_pal.mar
                  [002000]  5020  
         42E09537 [002000]  5021  	subq	p23, #4, p23			; adjust pc
         229F0005 [002004]  5022  	lda	p20, HALT__SW_HALT(r31)		; halt code
         7E9510C8 [002008]  5023  	hw_stq/p p20, PT__HALT_CODE(p_temp)	; store (??)
         C3E009DC [00200C]  5024  	br	r31, trap__update_pcb_and_halt
                  [002010]  5025  
                  [002010]  5026  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002010]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002010]   176M         GOTO_FREE_CODE
                  [004E80]    67M     .align 6
File: ev6_osf_pal.mar
                  [004E80]  5027  
                  [004E80]  5028  
                  [004E80]  5029  ;+
                  [004E80]  5030  ; CALL_PAL__CFLUSH
                  [004E80]  5031  ;
                  [004E80]  5032  ; Entry:
                  [004E80]  5033  ;	r16(a0)	page frame number (PFN) of page to be flushed
                  [004E80]  5034  ;	p23	pc of instruction following call_pal instruction
                  [004E80]  5035  ;
                  [004E80]  5036  ; Function:
                  [004E80]  5037  ;	Flush all dstream caches of 1 entire page.
                  [004E80]  5038  ;
                  [004E80]  5039  ; Note on implementation:
                  [004E80]  5040  ;	Since the dcache is two-way set associative, we need to
                  [004E80]  5041  ;	do two passes with different tags.
                  [004E80]  5042  ;-
                  [004E80]  5043  	START_CALL_PAL <CFLUSH>
File: ev6_pal_macros.mar
                  [004E80]   104i         ASSUME <<OSFPAL_FUNC__CFLUSH> & <^x40>> eq 0
                  [004E80]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002040]   120i CALL_PAL__CFLUSH::
File: ev6_osf_pal.mar
                  [002040]  5044  
         C3E00D9F [002040]  5045  	br	r31, sys__cflush		; handle in system module
                  [002044]  5046  
                  [002044]  5047  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002044]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002044]   176M         GOTO_FREE_CODE
                  [004E80]    67M     .align 6
File: ev6_osf_pal.mar
                  [004E80]  5048  
                  [004E80]  5049  
                  [004E80]  5050  ;+
                  [004E80]  5051  ; CALL_PAL__DRAINA
                  [004E80]  5052  ;
                  [004E80]  5053  ; Entry:
                  [004E80]  5054  ;	p23	pc of instruction following the call_pal instruction
                  [004E80]  5055  ;
                  [004E80]  5056  ; Function:
                  [004E80]  5057  ;	Stall instruction issuing until all prior instruction are
                  [004E80]  5058  ;	guaranteed to complete without incurring aborts.
                  [004E80]  5059  ;
                  [004E80]  5060  ; Note:
                  [004E80]  5061  ;	This call_pal is not all that useful, since it could incur
                  [004E80]  5062  ;	a machine_check_while_in_pal, which is not a very useful
                  [004E80]  5063  ;	state to get in to. However, as long as the machine check
                  [004E80]  5064  ;	flow does not write into p23, we could conceivably, in the
                  [004E80]  5065  ;	machine check flow, determine we were in a draina, and do a
                  [004E80]  5066  ;	recoverable machine check.
                  [004E80]  5067  ;
                  [004E80]  5068  ; Do an MB to drain all the queues, and a hw_ret_stall to synchronize
                  [004E80]  5069  ; retires.
                  [004E80]  5070  ;-
                  [004E80]  5071  	START_CALL_PAL <DRAINA>
File: ev6_pal_macros.mar
                  [004E80]   104i         ASSUME <<OSFPAL_FUNC__DRAINA> & <^x40>> eq 0
                  [004E80]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002080]   120i CALL_PAL__DRAINA::
File: ev6_osf_pal.mar
                  [002080]  5072  
         63FF4000 [002080]  5073  	mb
                  [002084]  5074  	NOP					; no hw_ret in 1st fetchblock
File: ev6_pal_macros.mar
         47FF041F [002084]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002088]  5075  	NOP
File: ev6_pal_macros.mar
         47FF041F [002088]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [00208C]  5076  	NOP
File: ev6_pal_macros.mar
         47FF041F [00208C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002090]  5077  
         7BF7A000 [002090]  5078  	hw_ret_stall (p23)			; return with stall
                  [002094]  5079  
                  [002094]  5080  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002094]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002094]   176M         GOTO_FREE_CODE
                  [004E80]    67M     .align 6
File: ev6_osf_pal.mar
                  [004E80]  5081  
                  [004E80]  5082  ;+
                  [004E80]  5083  ; CALL_PAL__CSERVE
                  [004E80]  5084  ;
                  [004E80]  5085  ; Entry:
                  [004E80]  5086  ;	p23		pc of instruction following the call_pal instruction
                  [004E80]  5087  ;
                  [004E80]  5088  ; Function:
                  [004E80]  5089  ;	Do an implementation specific console service.
                  [004E80]  5090  ;
                  [004E80]  5091  ; Exit state:
                  [004E80]  5092  ;	Exit to sys__cserve
                  [004E80]  5093  ;
                  [004E80]  5094  ;-
                  [004E80]  5095  	START_CALL_PAL <CSERVE>
File: ev6_pal_macros.mar
                  [004E80]   104i         ASSUME <<OSFPAL_FUNC__CSERVE> & <^x40>> eq 0
                  [004E80]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002240]   120i CALL_PAL__CSERVE::
File: ev6_osf_pal.mar
                  [002240]  5096  
         C3E010A5 [002240]  5097  	br	r31, sys__cserve		; handle in system code
                  [002244]  5098  
                  [002244]  5099  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002244]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002244]   176M         GOTO_FREE_CODE
                  [004E80]    67M     .align 6
File: ev6_osf_pal.mar
                  [004E80]  5100  
                  [004E80]  5101  ;+
                  [004E80]  5102  ; CALL_PAL__SWPPAL
                  [004E80]  5103  ;
                  [004E80]  5104  ; Entry:
                  [004E80]  5105  ;	p23		pc of instruction following the call_pal instruction
                  [004E80]  5106  ;
                  [004E80]  5107  ; Function:
                  [004E80]  5108  ;	Swap control to another PALcode.
                  [004E80]  5109  ;
                  [004E80]  5110  ; Register use:
                  [004E80]  5111  ;	r16(a0)	new PALcode identifier
                  [004E80]  5112  ;			0 	=> new PALcode at address 0
                  [004E80]  5113  ;			2 	=> OSFPAL
                  [004E80]  5114  ;			>255	=> new PALcode at address in r16
                  [004E80]  5115  ;	r17(a1)	new PC
                  [004E80]  5116  ;	r18(a2)	new PCBB
                  [004E80]  5117  ;	r19	new VPTB
                  [004E80]  5118  ;
                  [004E80]  5119  ; Exit state:
                  [004E80]  5120  ;	r0(v0)	0	success (PALcode was switched)
                  [004E80]  5121  ;		1	unknown PALcode variant
                  [004E80]  5122  ;		2	know PALcode variant, but not loaded
                  [004E80]  5123  ;-
                  [004E80]  5124  	START_CALL_PAL <SWPPAL>
File: ev6_pal_macros.mar
                  [004E80]   104i         ASSUME <<OSFPAL_FUNC__SWPPAL> & <^x40>> eq 0
                  [004E80]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002280]   120i CALL_PAL__SWPPAL::
File: ev6_osf_pal.mar
                  [002280]  5125  
         421FF7A0 [002280]  5126  	cmpule	r16, #255, r0			; see if a variant
         46100480 [002284]  5127  	cmoveq	r16, r16, r0			; r16 = 0 is a valid address
         461F0405 [002288]  5128  	bis	r16, r31, p5			; will jump through p5
         E0000B05 [00228C]  5129  	blbc	r0, call_pal__swppal_addr	; try as an address
                  [002290]  5130  
         420055A0 [002290]  5131  	cmpeq	r16, #2, r0			; see if our buddy OSFPAL
         E0000B08 [002294]  5132  	blbc	r0, call_pal__swppal_fail	; nope, don't know this fellow
                  [002298]  5133  
                  [002298]  5134  .iif eq <.&4>, NOP
                  [002298]  5134I  NOP
File: ev6_pal_macros.mar
         47FF041F [002298]   283i 	bis	r31, r31, r31
File: ev6_osf_pal.mar
         C0800002 [00229C]  5135  	br	p4, call_pal__swppal_osf
00000000 0000C100 [0022A0]  5136  	.quad	PAL__ENTER_OSF			; address must fit in a quadword
                  [0022A8]  5137  call_pal__swppal_osf:
         6C841000 [0022A8]  5138  	hw_ldq/p p4, 0(p4)			; fetch target address pointer
         6CA41000 [0022AC]  5139  	hw_ldq/p p5, 0(p4)			; fetch target address
                  [0022B0]  5140  
         ECA00B01 [0022B0]  5141  	ble	p5, call_pal__swppal_fail	; if not linked, say not loaded
         209F7FFF [0022B4]  5142  	lda	p4, ^x7FFF(r31)			; checker for pal base
         44A40004 [0022B8]  5143  	and	p5, p4, p4			; get low 15 bits
                  [0022BC]  5144  
                  [0022BC]  5145  	CONT_CALL_PAL <SWPPAL>
File: ev6_pal_macros.mar
                  [0022BC]   181M     ASSUME <_pal_func_cont> eq 0
         C3E00AF0 [0022BC]   186i 	br	r31, CALL_PAL__SWPPAL_CONT
                  [0022C0]   189M                 ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [0022C0]   191M     GOTO_FREE_CODE
                  [004E80]    67M     .align 6
                  [004E80]   196i CALL_PAL__SWPPAL_CONT:
File: ev6_osf_pal.mar
                  [004E80]  5146  
         408015A0 [004E80]  5147  	cmpeq	p4, #0, r0			; check for non-zero bits
         E000000C [004E84]  5148  	blbc	r0, call_pal__swppal_fail	; if not clear, say unknown
                  [004E88]  5149  ;
                  [004E88]  5150  ; Current state:
                  [004E88]  5151  ;	p5	address
                  [004E88]  5152  ;
         47E03404 [004E88]  5153  	bis	r31, #1, p4			; get a '1'
         4887D724 [004E8C]  5154  	sll	p4, #OSF_P_MISC__SWITCH__S,p4	; switch bit into position
         46C40416 [004E90]  5155  	bis	p_misc, p4, p_misc		; mark 'switch'
                  [004E94]  5156  
         47FF0400 [004E94]  5157  	bis	r31, r31, r0			; status to success
         44A03405 [004E98]  5158  	bis	p5, #1, p5			; set pal mode bit
         D3E00000 [004E9C]  5159  	bsr	r31, .				; push prediction stack
                  [004EA0]  5160  	PVC_VIOLATE <1007>			; go to it
File: ev6_pal_macros.mar
                  [004EA0]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_pal.mar
         7BE58000 [004EA0]  5161  	hw_ret	(p5)				; pop prediction stack
                  [004EA4]  5162  ;
                  [004EA4]  5163  ; Looks like an address, either 0 or > 255. Check low bits.
                  [004EA4]  5164  ; Current state:
                  [004EA4]  5165  ;	p5	address
                  [004EA4]  5166  ;
                  [004EA4]  5167  call_pal__swppal_addr:
         209F7FFF [004EA4]  5168  	lda	p4, ^x7FFF(r31)			; checker for pal base
         44A40004 [004EA8]  5169  	and	p5, p4, p4			; get low 15 bits
         408015A0 [004EAC]  5170  	cmpeq	p4, #0, r0			; check for non-zero bits
         E0000001 [004EB0]  5171  	blbc	r0, call_pal__swppal_fail	; if not clear, say unknown
         C3FFFFF2 [004EB4]  5172  	br	r31, call_pal__swppal_cont	; address ok, so continue
                  [004EB8]  5173  ;
                  [004EB8]  5174  ; We have failed.
                  [004EB8]  5175  ; Current state:
                  [004EB8]  5176  ;	r0	0	unknown variant or bad address
                  [004EB8]  5177  ;		1	osfpal, but not loaded
                  [004EB8]  5178  ; Exit state:
                  [004EB8]  5179  ;	r0	1	unknown variant or bad address
                  [004EB8]  5180  ;		2	osfpal, but not loaded
                  [004EB8]  5181  ;
                  [004EB8]  5182  call_pal__swppal_fail:
                  [004EB8]  5183  	
         40003400 [004EB8]  5184  	addq	r0, #1, r0			; affect r0
         7BF78000 [004EBC]  5185  	hw_ret	(p23)				; return
                  [004EC0]  5186  
                  [004EC0]  5187  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [004EC0]   176M         GOTO_FREE_CODE
                  [004EC0]    67M     .align 6
File: ev6_osf_pal.mar
                  [004EC0]  5188  
                  [004EC0]  5189  
                  [004EC0]  5190  ;+
                  [004EC0]  5191  ; CALL_PAL__WRIPIR
                  [004EC0]  5192  ;
                  [004EC0]  5193  ; Entry:
                  [004EC0]  5194  ;	p23		pc of instruction following the call_pal instruction
                  [004EC0]  5195  ;
                  [004EC0]  5196  ; Function:
                  [004EC0]  5197  ;	IPIR <- r16(a0)
                  [004EC0]  5198  ;	Handled in system-specific code.
                  [004EC0]  5199  ;-
                  [004EC0]  5200  	START_CALL_PAL <WRIPIR>
File: ev6_pal_macros.mar
                  [004EC0]   104i         ASSUME <<OSFPAL_FUNC__WRIPIR> & <^x40>> eq 0
                  [004EC0]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002340]   120i CALL_PAL__WRIPIR::
File: ev6_osf_pal.mar
                  [002340]  5201  
         C3E00D0F [002340]  5202  	br	r31, sys__wripir
                  [002344]  5203  
                  [002344]  5204  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002344]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002344]   176M         GOTO_FREE_CODE
                  [004EC0]    67M     .align 6
File: ev6_osf_pal.mar
                  [004EC0]  5205  
                  [004EC0]  5206  
                  [004EC0]  5207  ;+
                  [004EC0]  5208  ; CALL_PAL__RDMCES
                  [004EC0]  5209  ;
                  [004EC0]  5210  ; Entry:
                  [004EC0]  5211  ;	p23		pc of instruction following the call_pal instruction
                  [004EC0]  5212  ;
                  [004EC0]  5213  ; Function:
                  [004EC0]  5214  ;	Return in r0(v0) the MCES IPR.
                  [004EC0]  5215  ;	r0(v0) <- ZEXT(MCES)
                  [004EC0]  5216  ;
                  [004EC0]  5217  ; Exit state:
                  [004EC0]  5218  ;	r0(v0)		MCES
                  [004EC0]  5219  ;-
                  [004EC0]  5220  	START_CALL_PAL <RDMCES>
File: ev6_pal_macros.mar
                  [004EC0]   104i         ASSUME <<OSFPAL_FUNC__RDMCES> & <^x40>> eq 0
                  [004EC0]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002400]   120i CALL_PAL__RDMCES::
File: ev6_osf_pal.mar
                  [002400]  5221  
                  [002400]  5222  ASSUME OSF_P_MISC__MCES__MCHK__S eq 16
                  [002400]  5223  
         4AC050C0 [002400]  5224  	extbl	p_misc, #2, r0			; get mces from p_misc
                  [002404]  5225  	NOP					; no ret in 1st fetch block
File: ev6_pal_macros.mar
         47FF041F [002404]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002408]  5226  	NOP
File: ev6_pal_macros.mar
         47FF041F [002408]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [00240C]  5227  	NOP
File: ev6_pal_macros.mar
         47FF041F [00240C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002410]  5228  
         7BF78000 [002410]  5229  	hw_ret	(p23)				; return
                  [002414]  5230  
                  [002414]  5231  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002414]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002414]   176M         GOTO_FREE_CODE
                  [004EC0]    67M     .align 6
File: ev6_osf_pal.mar
                  [004EC0]  5232  
                  [004EC0]  5233  ;+
                  [004EC0]  5234  ; CALL_PAL__WRMCES
                  [004EC0]  5235  ;
                  [004EC0]  5236  ; Entry:
                  [004EC0]  5237  ;	p23		pc of instruction following the call_pal instruction
                  [004EC0]  5238  ;	r16(a0)		mces information
                  [004EC0]  5239  ;
                  [004EC0]  5240  ; Function:
                  [004EC0]  5241  ;	if (r16<0> eq 1) then MCES<0> <- 0	mchk
                  [004EC0]  5242  ;	if (r16<1> eq 1) then MCES<1> <- 0	system correctable -- sce
                  [004EC0]  5243  ;	if (r16<2> eq 1) then MCES<2> <- 0	processor correctable -- pce
                  [004EC0]  5244  ;	MCES<3> <- r16<3>			set <- disable pce -- dpc
                  [004EC0]  5245  ;	MCES<4> <- r16<4>			set <- disable sce -- dsc
                  [004EC0]  5246  ;
                  [004EC0]  5247  ;-
                  [004EC0]  5248  	START_CALL_PAL <WRMCES>
File: ev6_pal_macros.mar
                  [004EC0]   104i         ASSUME <<OSFPAL_FUNC__WRMCES> & <^x40>> eq 0
                  [004EC0]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002440]   120i CALL_PAL__WRMCES::
File: ev6_osf_pal.mar
                  [002440]  5249  
                  [002440]  5250  ASSUME OSF_P_MISC__MCES__MCHK__S eq 16
                  [002440]  5251  
                  [002440]  5252  mces_clear = <<1@MCES__MCHK__S> ! <1@MCES__SCE__S> ! <1@MCES__PCE__S>>
                  [002440]  5253  mces_dis = <<1@MCES__DPC__S> ! <1@MCES__DSC__S>>
                  [002440]  5254  
                  [002440]  5255  ASSUME mces_clear eq <^x7>
                  [002440]  5256  ASSUME mces_dis le <^x18>
                  [002440]  5257  
         4AC050C4 [002440]  5258  	extbl	p_misc, #2, p4		; get mces from p_misc
                  [002444]  5259  
         4600F006 [002444]  5260  	and	r16, #mces_clear, p6	; get mchk, sce, pce
         47E60506 [002448]  5261  	ornot	r31, p6, p6		; flip mchk, sce, pce bits
         46031007 [00244C]  5262  	and	r16, #mces_dis, p7	; get disable bits
                  [002450]  5263  
         44860004 [002450]  5264  	and	p4, p6, p4		; update mchk, sce, pce
         44831104 [002454]  5265  	bic	p4, #mces_dis, p4	; clear old dpc, dsc
         44870404 [002458]  5266  	or	p4, p7, p4		; update dpc, dsc
                  [00245C]  5267  
         4AC09616 [00245C]  5268  	zap	p_misc, #4, p_misc			; clear out old mces
         48821724 [002460]  5269  	sll	p4, #OSF_P_MISC__MCES__MCHK__S, p4	; move into position
         46C40416 [002464]  5270  	bis	p_misc, p4, p_misc			; or new mces in
                  [002468]  5271  
         7BF78000 [002468]  5272  	hw_ret	(p23)			; return to user
                  [00246C]  5273  
                  [00246C]  5274  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [00246C]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [00246C]   176M         GOTO_FREE_CODE
                  [004EC0]    67M     .align 6
File: ev6_osf_pal.mar
                  [004EC0]  5275  
                  [004EC0]  5276  ;+
                  [004EC0]  5277  ; CALL_PAL__WRFEN
                  [004EC0]  5278  ;
                  [004EC0]  5279  ; Entry:
                  [004EC0]  5280  ;	p23		pc of instruction following the call_pal instruction
                  [004EC0]  5281  ;	r16(a0)<0>	new fen bit
                  [004EC0]  5282  ;
                  [004EC0]  5283  ; Function:
                  [004EC0]  5284  ;	FEN 	   	<- R16<0>
                  [004EC0]  5285  ;	(PCB+40)<0>	<- FEN
                  [004EC0]  5286  ;	r16(a0)		unpredictable
                  [004EC0]  5287  ;-
                  [004EC0]  5288  	START_CALL_PAL <WRFEN>
File: ev6_pal_macros.mar
                  [004EC0]   104i         ASSUME <<OSFPAL_FUNC__WRFEN> & <^x40>> eq 0
                  [004EC0]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002AC0]   120i CALL_PAL__WRFEN::
File: ev6_osf_pal.mar
                  [002AC0]  5289  
         6C951010 [002AC0]  5290  	hw_ldq/p p4, PT__PCBB(p_temp)		; get PCBB
         46003010 [002AC4]  5291  	and	r16, #1, r16			; clean new fen
         4A005727 [002AC8]  5292  	sll	r16, #EV6__FPE__FPE__S, p7	; shift into position
         77E75010 [002ACC]  5293  	hw_mtpr	p7, EV6__FPE			; (4,0L) write new fpe
                  [002AD0]  5294  
         77E75010 [002AD0]  5295  	hw_mtpr p7, EV6__FPE			; (4,0L) force retire
         7E040028 [002AD4]  5296  	hw_stl/p r16, OSF_PCB__FEN(p4)		; store FEN in PCB
         47FF041F [002AD8]  5297  	bis	r31, r31, r31
         47FF041F [002ADC]  5298  	bis	r31, r31, r31
                  [002AE0]  5299  
         44000400 [002AE0]  5300  	bis	r0, r0, r0			; buffer block 1
         47FF041F [002AE4]  5301  	bis	r31, r31, r31
         47FF041F [002AE8]  5302  	bis	r31, r31, r31
         47FF041F [002AEC]  5303  	bis	r31, r31, r31
                  [002AF0]  5304  
         44000400 [002AF0]  5305  	bis	r0, r0, r0			; buffer block 2
         47FF041F [002AF4]  5306  	bis	r31, r31, r31
         47FF041F [002AF8]  5307  	bis	r31, r31, r31
                  [002AFC]  5308  	CONT_CALL_PAL <WRFEN>
File: ev6_pal_macros.mar
                  [002AFC]   181M     ASSUME <_pal_func_cont> eq 0
         C3E008F0 [002AFC]   186i 	br	r31, CALL_PAL__WRFEN_CONT
                  [002B00]   189M                 ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002B00]   191M     GOTO_FREE_CODE
                  [004EC0]    67M     .align 6
                  [004EC0]   196i CALL_PAL__WRFEN_CONT:
File: ev6_osf_pal.mar
                  [004EC0]  5309  
         44000400 [004EC0]  5310  	bis	r0, r0, r0			; buffer block 3
         47FF041F [004EC4]  5311  	bis	r31, r31, r31
         47FF041F [004EC8]  5312  	bis	r31, r31, r31
         47FF041F [004ECC]  5313  	bis	r31, r31, r31
                  [004ED0]  5314  
                  [004ED0]  5315  .if ne ev6_p1
                  [004ED0]  5316  	hw_ldq/p p5, PT__IMPURE(p_temp)		; get impure pointer
                  [004ED0]  5317  	hw_stq/p r16, CNS__FPE_STATE(p5)	; save 'fpe' state
                  [004ED0]  5318  .endc
                  [004ED0]  5319  
         7BF7A000 [004ED0]  5320  	hw_ret_stall (p23)			; stall for pvc
                  [004ED4]  5321  
                  [004ED4]  5322  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [004ED4]   176M         GOTO_FREE_CODE
00000000 00000000 [004ED4]    67M     .align 6
00000000 00000000 [004EDC]
00000000 00000000 [004EE4]
00000000 00000000 [004EEC]
00000000 00000000 [004EF4]
         00000000 [004EFC]
File: ev6_osf_pal.mar
                  [004F00]  5323  
                  [004F00]  5324  
                  [004F00]  5325  ;+
                  [004F00]  5326  ; CALL_PAL__WRVPTPTR
                  [004F00]  5327  ;
                  [004F00]  5328  ; Entry:
                  [004F00]  5329  ;	p23		pc of instruction following the call_pal instruction
                  [004F00]  5330  ;	r16(a0)		new VPTPTR
                  [004F00]  5331  ;
                  [004F00]  5332  ; Function:
                  [004F00]  5333  ;	VPTPTR <- r16
                  [004F00]  5334  ;	r16(a0)		unpredictable
                  [004F00]  5335  ;
                  [004F00]  5336  ; Note: We clean <29:0> before storing.
                  [004F00]  5337  ;-
                  [004F00]  5338  	START_CALL_PAL <WRVPTPTR>
File: ev6_pal_macros.mar
                  [004F00]   104i         ASSUME <<OSFPAL_FUNC__WRVPTPTR> & <^x40>> eq 0
                  [004F00]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002B40]   120i CALL_PAL__WRVPTPTR::
File: ev6_osf_pal.mar
                  [002B40]  5339  
                  [002B40]  5340  ASSUME EV6__I_CTL__VPTB__S eq EV6__VA_CTL__VPTB__S
                  [002B40]  5341  ;
                  [002B40]  5342  ; 1.48 Reorder code to force retire of va_ctl before hw_ret_stall.
                  [002B40]  5343  ;
                  [002B40]  5344  
         64DF1110 [002B40]  5345  	hw_mfpr	p6, EV6__I_CTL			; (4,0L) get i_ctl
         6CF510B8 [002B44]  5346  	hw_ldq/p p7, PT__VA_CTL(p_temp)		; get control part of va_ctl
                  [002B48]  5347  
         44F00407 [002B48]  5348  	bis	p7, r16, p7			; new va_ctl
         7E151000 [002B4C]  5349  	hw_stq/p r16, PT__VPTB(p_temp)		; new vptb
         77E7C420 [002B50]  5350  	hw_mtpr	p7, EV6__VA_CTL			; (5,0L)
                  [002B54]  5351  
         4A03D690 [002B54]  5352  	srl	r16, #EV6__I_CTL__VPTB__S, r16	; shift new vptb to clean
         4A03D730 [002B58]  5353  	sll	r16, #EV6__I_CTL__VPTB__S, r16	; shift back into position
                  [002B5C]  5354  
         48C45726 [002B5C]  5355  	sll	p6, #<64 - EV6__I_CTL__VPTB__S>, p6	; clean
         48C45686 [002B60]  5356  	srl	p6, #<64 - EV6__I_CTL__VPTB__S>, p6	; move back
         44D00406 [002B64]  5357  	bis	p6, r16, p6				; or new vptb
         77E61130 [002B68]  5358  	hw_mtpr	p6, <EV6__I_CTL ! ^x20>		; 1.48 (4&5,0L) write i_ctl
                  [002B6C]  5359  
                  [002B6C]  5360  	ALIGN_FETCH_BLOCK <^x47FF041F>		; 1.48
File: ev6_pal_macros.mar
         47FF041F [002B6C]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
         7BF7A000 [002B70]  5361  	hw_ret_stall (p23)			; return with stall
                  [002B74]  5362  
                  [002B74]  5363  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002B74]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002B74]   176M         GOTO_FREE_CODE
                  [004F00]    67M     .align 6
File: ev6_osf_pal.mar
                  [004F00]  5364  
                  [004F00]  5365  ;+
                  [004F00]  5366  ; CALL_PAL__SWPCTX
                  [004F00]  5367  ;
                  [004F00]  5368  ; Entry:
                  [004F00]  5369  ;	p23	pc of instruction following the call_pal instruction
                  [004F00]  5370  ;	r16(a0)	address of new PCB
                  [004F00]  5371  ;
                  [004F00]  5372  ; Function:
                  [004F00]  5373  ;	The swap process context instruction saves the current process
                  [004F00]  5374  ;	data in the current PCB. Then swpctx switches to the PCB passed in
                  [004F00]  5375  ;	a0 and loads the new process context. The old PCBB is returned in v0.
                  [004F00]  5376  ;
                  [004F00]  5377  ;-
                  [004F00]  5378  	START_CALL_PAL <SWPCTX>
File: ev6_pal_macros.mar
                  [004F00]   104i         ASSUME <<OSFPAL_FUNC__SWPCTX> & <^x40>> eq 0
                  [004F00]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002C00]   120i CALL_PAL__SWPCTX::
File: ev6_osf_pal.mar
                  [002C00]  5379  
         6C151010 [002C00]  5380  	hw_ldq/p r0, PT__PCBB(p_temp)		; get old PCBB
                  [002C04]  5381  
         609FC000 [002C04]  5382  	rpcc	p4				; get cycle counter
         48841686 [002C08]  5383  	srl	p4, #32, p6			; shift offset
         40860006 [002C0C]  5384  	addl	p4, p6, p6			; merge to compute cpc
                  [002C10]  5385  
         6CF51020 [002C10]  5386  	hw_ldq/p p7, PT__USP(p_temp)		; get usp
         7FC01000 [002C14]  5387  	hw_stq/p r30, OSF_PCB__KSP(r0)		; store ksp
         7CE01008 [002C18]  5388  	hw_stq/p p7, OSF_PCB__USP(r0)		; store usp
         7CC00018 [002C1C]  5389  	hw_stl/p p6, OSF_PCB__CPC(r0)		; store cpc
                  [002C20]  5390  
         6CD01018 [002C20]  5391  	hw_ldq/p p6, OSF_PCB__CPC(r16)		; get new cpc/asn
         6CB01028 [002C24]  5392  	hw_ldq/p p5, OSF_PCB__FEN(r16)		; get new fen/pme
         7E151010 [002C28]  5393  	hw_stq/p r16, PT__PCBB(p_temp)		; set new PCBB
                  [002C2C]  5394  ;
                  [002C2C]  5395  ; Compute new cc offset
                  [002C2C]  5396  ;
         40C40124 [002C2C]  5397  	subl	p6, p4, p4			; generate new cc offset
         48841724 [002C30]  5398  	sll	p4, #32, p4			; move into position
         77E4C020 [002C34]  5399  	hw_mtpr	p4, EV6__CC			; (5,1L) write it
                  [002C38]  5400  
                  [002C38]  5401  	CONT_CALL_PAL <SWPCTX>
File: ev6_pal_macros.mar
                  [002C38]   181M     ASSUME <_pal_func_cont> eq 0
         C3E008B1 [002C38]   186i 	br	r31, CALL_PAL__SWPCTX_CONT
                  [002C3C]   189M                 ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002C3C]   191M     GOTO_FREE_CODE
                  [004F00]    67M     .align 6
                  [004F00]   196i CALL_PAL__SWPCTX_CONT:
File: ev6_osf_pal.mar
                  [004F00]  5402  
         77E4C020 [004F00]  5403  	hw_mtpr	p4, EV6__CC			; 1.48 (5,1L) force retire
                  [004F04]  5404  ;
                  [004F04]  5405  ; Now write ASN to DTB_ASNx.
                  [004F04]  5406  ;
                  [004F04]  5407  ; Current state:
                  [004F04]  5408  ;	p5	fen/pme quadword
                  [004F04]  5409  ;	p6	cpc/asn quadword
                  [004F04]  5410  ;
                  [004F04]  5411  ASSUME OSF_PCB__ASN__M eq ^xFF
                  [004F04]  5412  
         48C41686 [004F04]  5413  	srl	p6, #OSF_PCB__ASN__S, p6	; shift down ASN
         44DFF006 [004F08]  5414  	and	p6, #OSF_PCB__ASN__M, p6	; clean ASN
         48C71726 [004F0C]  5415  	sll	p6, #EV6__DTB_ASN0__ASN__S, p6	; ASN into mbox spot
                  [004F10]  5416  ;
                  [004F10]  5417  ; There must be a scoreboard bit -> register dependency chain to prevent
                  [004F10]  5418  ; hw_mtpr DTB_ASx from issuing while ANY of scoreboard bits <7:4> are set.
                  [004F10]  5419  ;
         64FF10F0 [004F10]  5420  	hw_mfpr	p7, <EV6__PAL_BASE ! ^xF0>	; (4-7,0L)
         44E70807 [004F14]  5421  	xor	p7, p7, p7			; zap p7
         44E60406 [004F18]  5422  	bis	p7, p6, p6			; force register dependency
                  [004F1C]  5423  	NOP					; force fetch block
File: ev6_pal_macros.mar
         47FF041F [004F1C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004F20]  5424  
         77E62510 [004F20]  5425  	hw_mtpr	p6, EV6__DTB_ASN0		; (4,0L)
         77E6A580 [004F24]  5426  	hw_mtpr	p6, EV6__DTB_ASN1		; (7,1L)
                  [004F28]  5427  ;
                  [004F28]  5428  ; Create Ibox Process Context IPR, filling in ASN, FPE, PPCE
                  [004F28]  5429  ;
                  [004F28]  5430  ; Current state:
                  [004F28]  5431  ;	p5	fen/pme quadword
                  [004F28]  5432  ;	p6	asn in DTB_ASNx position
                  [004F28]  5433  ;
                  [004F28]  5434  ASSUME EV6__DTB_ASN0__ASN__S eq 56
                  [004F28]  5435  ASSUME EV6__ASN__ASN__S eq 39
                  [004F28]  5436  ASSUME EV6__FPE__FPE__S eq 2
                  [004F28]  5437  ASSUME EV6__PPCE__PPCE__S eq 1
                  [004F28]  5438  asn_shift = <EV6__DTB_ASN0__ASN__S - EV6__ASN__ASN__S>
                  [004F28]  5439  fpe_shift = <EV6__FPE__FPE__S - OSF_PCB__FEN__S>
                  [004F28]  5440  ppce_shift = <OSF_PCB__PME__S - EV6__PPCE__PPCE__S>
                  [004F28]  5441  
         48C23686 [004F28]  5442  	srl	p6, #<asn_shift>, p6		; ASN back into ibox position
         48A05724 [004F2C]  5443  	sll	p5, #fpe_shift, p4		; get FEN into position
         44809004 [004F30]  5444  	and	p4, #<1@EV6__FPE__FPE__S>, p4	; clean it
         44C40406 [004F34]  5445  	bis	p6, p4, p6			; or in FEN enable
                  [004F38]  5446  
                  [004F38]  5447  .if ne ev6_p1
                  [004F38]  5448  	hw_ldq/p p7, PT__IMPURE(p_temp)		; get impure pointer
                  [004F38]  5449  	and	p5, #1, p4			; clean PCB FEN bit
                  [004F38]  5450  	hw_stq/p p4, CNS__FPE_STATE(p7)		; write FPE_STATE
                  [004F38]  5451  .endc
                  [004F38]  5452  
                  [004F38]  5453  	ALIGN_FETCH_BLOCK <^x47FF041F>
File: ev6_pal_macros.mar
47FF041F 47FF041F [004F38]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
                  [004F40]  5454  
         48A7B684 [004F40]  5455  	srl	p5, #ppce_shift, p4		; get pme into position
         44805004 [004F44]  5456  	and	p4, #<1@EV6__PPCE__PPCE__S>, p4	; clean it
         44C40406 [004F48]  5457  	bis	p6, p4, p6			; or in ppce bit
         77E65F10 [004F4C]  5458  	hw_mtpr	p6, EV6__PROCESS_CONTEXT	; (4,0L) write it
                  [004F50]  5459  ;
                  [004F50]  5460  ; Write new PTBR, get new USP and SP, save USP.
                  [004F50]  5461  ;
         77E65F10 [004F50]  5462  	hw_mtpr	p6, EV6__PROCESS_CONTEXT	; (4,0L) force retire
         6C901010 [004F54]  5463  	hw_ldq/p p4, OSF_PCB__PTBR(r16)		; get new PTBR
         6CB01008 [004F58]  5464  	hw_ldq/p p5, OSF_PCB__USP(r16)		; get new USP
         6FD01000 [004F5C]  5465  	hw_ldq/p r30, OSF_PCB__KSP(r16)		; get new KSP
                  [004F60]  5466  
         4881B724 [004F60]  5467  	sll	p4, #page_offset_size_bits, p4	; convert PFN
         7C951008 [004F64]  5468  	hw_stq/p p4, PT__PTBR(p_temp)		; store new PTBR
         7CB51020 [004F68]  5469  	hw_stq/p p5, PT__USP(p_temp)		; save USP
         47FF041F [004F6C]  5470  	bis	r31, r31, r31			; buffer block 1
                  [004F70]  5471  
         44000400 [004F70]  5472  	bis	r0, r0, r0			; buffer block 2
         47FF041F [004F74]  5473  	bis	r31, r31, r31
         47FF041F [004F78]  5474  	bis	r31, r31, r31
         47FF041F [004F7C]  5475  	bis	r31, r31, r31
                  [004F80]  5476  
         44000400 [004F80]  5477  	bis	r0, r0, r0			; buffer block 3
         47FF041F [004F84]  5478  	bis	r31, r31, r31
         47FF041F [004F88]  5479  	bis	r31, r31, r31
         47FF041F [004F8C]  5480  	bis	r31, r31, r31
                  [004F90]  5481  
         7BF7A000 [004F90]  5482  	hw_ret_stall (p23)			; return
                  [004F94]  5483  
                  [004F94]  5484  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [004F94]   176M         GOTO_FREE_CODE
00000000 00000000 [004F94]    67M     .align 6
00000000 00000000 [004F9C]
00000000 00000000 [004FA4]
00000000 00000000 [004FAC]
00000000 00000000 [004FB4]
         00000000 [004FBC]
File: ev6_osf_pal.mar
                  [004FC0]  5485  
                  [004FC0]  5486  ;+
                  [004FC0]  5487  ; CALL_PAL__WRVAL
                  [004FC0]  5488  ;
                  [004FC0]  5489  ; Entry:
                  [004FC0]  5490  ;	p23		pc of instruction following the call_pal instruction
                  [004FC0]  5491  ;	r16(a0)		new sysvalue
                  [004FC0]  5492  ;
                  [004FC0]  5493  ; Function:
                  [004FC0]  5494  ;	sysvalue <- r16
                  [004FC0]  5495  ;	r16(a0)		unpredictable
                  [004FC0]  5496  ;
                  [004FC0]  5497  ;-
                  [004FC0]  5498  	START_CALL_PAL <WRVAL>
File: ev6_pal_macros.mar
                  [004FC0]   104i         ASSUME <<OSFPAL_FUNC__WRVAL> & <^x40>> eq 0
                  [004FC0]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002C40]   120i CALL_PAL__WRVAL::
File: ev6_osf_pal.mar
                  [002C40]  5499  
         7E151080 [002C40]  5500  	hw_stq/p r16, PT__SYSVAL(p_temp)	; write sysvalue
                  [002C44]  5501  	NOP					; no hw_ret in 1st fetch block
File: ev6_pal_macros.mar
         47FF041F [002C44]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002C48]  5502  	NOP
File: ev6_pal_macros.mar
         47FF041F [002C48]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002C4C]  5503  	NOP
File: ev6_pal_macros.mar
         47FF041F [002C4C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002C50]  5504  
         7BF78000 [002C50]  5505  	hw_ret	(p23)				; return to user
                  [002C54]  5506  
                  [002C54]  5507  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002C54]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002C54]   176M         GOTO_FREE_CODE
                  [004FC0]    67M     .align 6
File: ev6_osf_pal.mar
                  [004FC0]  5508  
                  [004FC0]  5509  ;+
                  [004FC0]  5510  ; CALL_PAL__RDVAL
                  [004FC0]  5511  ;
                  [004FC0]  5512  ; Entry:
                  [004FC0]  5513  ;	p23		pc of instruction following the call_pal instruction
                  [004FC0]  5514  ;
                  [004FC0]  5515  ; Function:
                  [004FC0]  5516  ;	r0(v0) <- sysvalue
                  [004FC0]  5517  ;
                  [004FC0]  5518  ;-
                  [004FC0]  5519  	START_CALL_PAL <RDVAL>
File: ev6_pal_macros.mar
                  [004FC0]   104i         ASSUME <<OSFPAL_FUNC__RDVAL> & <^x40>> eq 0
                  [004FC0]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002C80]   120i CALL_PAL__RDVAL::
File: ev6_osf_pal.mar
                  [002C80]  5520  
         6C151080 [002C80]  5521  	hw_ldq/p r0, PT__SYSVAL(p_temp)		; read sysvalue
                  [002C84]  5522  	NOP					; no hw_ret in 1st fetch block
File: ev6_pal_macros.mar
         47FF041F [002C84]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002C88]  5523  	NOP
File: ev6_pal_macros.mar
         47FF041F [002C88]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002C8C]  5524  	NOP
File: ev6_pal_macros.mar
         47FF041F [002C8C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002C90]  5525  
         7BF78000 [002C90]  5526  	hw_ret	(p23)				; return to user
                  [002C94]  5527  
                  [002C94]  5528  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002C94]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002C94]   176M         GOTO_FREE_CODE
                  [004FC0]    67M     .align 6
File: ev6_osf_pal.mar
                  [004FC0]  5529  
                  [004FC0]  5530  
                  [004FC0]  5531  ;+
                  [004FC0]  5532  ; CALL_PAL__TBI
                  [004FC0]  5533  ;
                  [004FC0]  5534  ; Entry:
                  [004FC0]  5535  ;	p23		pc of instruction following the call_pal instruction
                  [004FC0]  5536  ;
                  [004FC0]  5537  ; Function:
                  [004FC0]  5538  ;	case r16(a0) begin	
                  [004FC0]  5539  ;		 1:	! tbisi
                  [004FC0]  5540  ;			{invalidate ITB entry for va = r17(a1)}
                  [004FC0]  5541  ;			break;
                  [004FC0]  5542  ;		 2:	! tbisd
                  [004FC0]  5543  ;			{invalidate DTB entry for va = r17(a1)}
                  [004FC0]  5544  ;			break;
                  [004FC0]  5545  ;		 3:	! tbis
                  [004FC0]  5546  ;			{invalidate both TB entries for va = r17(a1)}
                  [004FC0]  5547  ;			break;
                  [004FC0]  5548  ;		-1:	! tbiap
                  [004FC0]  5549  ;			{invalidate all TB entries with ASM=0}
                  [004FC0]  5550  ;			break;
                  [004FC0]  5551  ;		-2:	! tbia
                  [004FC0]  5552  ;			{flush all TBs}
                  [004FC0]  5553  ;			break;
                  [004FC0]  5554  ;		other:
                  [004FC0]  5555  ;			break;
                  [004FC0]  5556  ;	endcase;
                  [004FC0]  5557  ;
                  [004FC0]  5558  ; Exit state:
                  [004FC0]  5559  ;	r16(a0)		unpredictable
                  [004FC0]  5560  ;	r17(a1)		unpredictable
                  [004FC0]  5561  ;-
                  [004FC0]  5562  	START_CALL_PAL <TBI>
File: ev6_pal_macros.mar
                  [004FC0]   104i         ASSUME <<OSFPAL_FUNC__TBI> & <^x40>> eq 0
                  [004FC0]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002CC0]   120i CALL_PAL__TBI::
File: ev6_osf_pal.mar
                  [002CC0]  5563  
                  [002CC0]  5564  TBI_FUNCTION_POWER = 6					; 64 bytes (16 inst)
                  [002CC0]  5565  
         42005410 [002CC0]  5566  	addq	r16, #2, r16				; create positive range
         C0800000 [002CC4]  5567  	br	p4, call_pal__tbi_addr
                  [002CC8]  5568  
                  [002CC8]  5569  call_pal__tbi_addr:
         4200D3A5 [002CC8]  5570  	cmpult	r16, #6, p5				; see if in range
         208422F8 [002CCC]  5571  	lda	p4, <tbi_tbl - call_pal__tbi_addr>(p4)	; base of table
         4A00D730 [002CD0]  5572  	sll	r16, #TBI_FUNCTION_POWER, r16		; function power
         E0A00004 [002CD4]  5573  	blbc	p5, call_pal__tbi_out			; branch if not in range
                  [002CD8]  5574  
         40900404 [002CD8]  5575  	addq	p4, r16, p4				; point to function
         44803404 [002CDC]  5576  	bis	p4, #1, p4				; make pal mode
         D3E00000 [002CE0]  5577  	bsr	r31, .					; push prediction stack
                  [002CE4]  5578  	PVC_JSR	tbi
File: ev6_pal_macros.mar
                  [002CE4]   531i  pvc_lbl \pcv_index, \pcv_jsr_tbi0, osf
File: ev6_osf_pal.mar
         7BE48000 [002CE4]  5579  	hw_ret	(p4)					; push prediction stack
                  [002CE8]  5580  							; go do it
                  [002CE8]  5581  call_pal__tbi_out:
         7BF78000 [002CE8]  5582  	hw_ret	(p23)					; out of range
                  [002CEC]  5583  
                  [002CEC]  5584  	CONT_CALL_PAL
File: ev6_pal_macros.mar
                  [002CEC]   181M     ASSUME <_pal_func_cont> eq 0
                  [002CEC]   189M     ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002CEC]   191M     GOTO_FREE_CODE
                  [004FC0]    67M     .align 6
File: ev6_osf_pal.mar
                  [004FC0]  5585  ;
                  [004FC0]  5586  ; tbi_tbl
                  [004FC0]  5587  ;
                  [004FC0]  5588  ; Table to do tbi instructions.
                  [004FC0]  5589  ;
                  [004FC0]  5590  ; ?? Should we do this differently, as the slot requirements are so
                  [004FC0]  5591  ; different??
                  [004FC0]  5592  ;
                  [004FC0]  5593  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
                  [004FC0]   275i 	.align 6
File: ev6_osf_pal.mar
                  [004FC0]  5594  tbi_tbl:
                  [004FC0]  5595  	; -2 tbia
                  [004FC0]  5596  	PVC_JSR tbi, dest=1
File: ev6_pal_macros.mar
                  [004FC0]   534i  pvc_lbl \pcv_index, \pcv_jsr_tbi0, osf, \pcv_jsr_tbi0_inst
File: ev6_osf_pal.mar
         77FF0310 [004FC0]  5597  	hw_mtpr r31, EV6__ITB_IA		; (4,0L)
         77FFA380 [004FC4]  5598  	hw_mtpr	r31, EV6__DTB_IA		; (7,0L)
                  [004FC8]  5599  	NOP
File: ev6_pal_macros.mar
         47FF041F [004FC8]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [004FCC]  5600  	NOP
File: ev6_pal_macros.mar
         47FF041F [004FCC]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
         77FF1310 [004FD0]  5601  	hw_mtpr	r31, EV6__IC_FLUSH		; (4,0L) flush icache
         F7E00000 [004FD4]  5602  	bne	r31, .				; pvc #24
         7BF7A000 [004FD8]  5603  	hw_ret_stall (p23)			; return with stall
                  [004FDC]  5604  
                  [004FDC]  5605  	; -1 tbiap
00000000 00000000 [004FDC]  5606  	.ALIGN TBI_FUNCTION_POWER
00000000 00000000 [004FE4]
00000000 00000000 [004FEC]
00000000 00000000 [004FF4]
         00000000 [004FFC]
                  [005000]  5607  	PVC_JSR tbi, dest=1
File: ev6_pal_macros.mar
                  [005000]   534i  pvc_lbl \pcv_index, \pcv_jsr_tbi0, osf, \pcv_jsr_tbi0_inst
File: ev6_osf_pal.mar
         77FF0210 [005000]  5608  	hw_mtpr r31, EV6__ITB_IAP		; (4,0L)
         77FFA280 [005004]  5609  	hw_mtpr r31, EV6__DTB_IAP		; (7,0L)
                  [005008]  5610  	NOP
File: ev6_pal_macros.mar
         47FF041F [005008]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [00500C]  5611  	NOP
File: ev6_pal_macros.mar
         47FF041F [00500C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
         77FF1210 [005010]  5612  	hw_mtpr	r31, EV6__IC_FLUSH_ASM		; (4,0L) flush icache
         F7E00000 [005014]  5613  	bne	r31, .				; pvc #24
         7BF7A000 [005018]  5614  	hw_ret_stall (p23)			; return with stall
                  [00501C]  5615  
                  [00501C]  5616  	; 0 unused
00000000 00000000 [00501C]  5617  	.ALIGN TBI_FUNCTION_POWER
00000000 00000000 [005024]
00000000 00000000 [00502C]
00000000 00000000 [005034]
         00000000 [00503C]
                  [005040]  5618  	PVC_JSR tbi, dest=1
File: ev6_pal_macros.mar
                  [005040]   534i  pvc_lbl \pcv_index, \pcv_jsr_tbi0, osf, \pcv_jsr_tbi0_inst
File: ev6_osf_pal.mar
         7BF78000 [005040]  5619  	hw_ret (p23)				; return
                  [005044]  5620  
                  [005044]  5621  	; 1 tbisi
00000000 00000000 [005044]  5622  	.ALIGN TBI_FUNCTION_POWER
00000000 00000000 [00504C]
00000000 00000000 [005054]
00000000 00000000 [00505C]
00000000 00000000 [005064]
00000000 00000000 [00506C]
00000000 00000000 [005074]
         00000000 [00507C]
                  [005080]  5623  	PVC_JSR tbi, dest=1
File: ev6_pal_macros.mar
                  [005080]   534i  pvc_lbl \pcv_index, \pcv_jsr_tbi0, osf, \pcv_jsr_tbi0_inst
File: ev6_osf_pal.mar
         77F10450 [005080]  5624  	hw_mtpr	r17, EV6__ITB_IS		; (4&6,0L)
         7BF7A000 [005084]  5625  	hw_ret_stall (p23)			; return with stall
                  [005088]  5626  
                  [005088]  5627  	; 2 tbisd
00000000 00000000 [005088]  5628  	.ALIGN TBI_FUNCTION_POWER
00000000 00000000 [005090]
00000000 00000000 [005098]
00000000 00000000 [0050A0]
00000000 00000000 [0050A8]
00000000 00000000 [0050B0]
00000000 00000000 [0050B8]
                  [0050C0]  5629  	PVC_JSR tbi, dest=1
File: ev6_pal_macros.mar
                  [0050C0]   534i  pvc_lbl \pcv_index, \pcv_jsr_tbi0, osf, \pcv_jsr_tbi0_inst
File: ev6_osf_pal.mar
                  [0050C0]  5630  ;
                  [0050C0]  5631  ; There must be a scoreboard bit -> register dependency chain to prevent
                  [0050C0]  5632  ; hw_mtpr DTB_ISx from issuing while ANY of scoreboard bits <7:4> are set.
                  [0050C0]  5633  ;
         64DF10F0 [0050C0]  5634  	hw_mfpr	p6, <EV6__PAL_BASE ! ^xF0>	; (4-7,0L)
         44C60806 [0050C4]  5635  	xor	p6, p6, p6			; zap p6
         44D10411 [0050C8]  5636  	bis	p6, r17, r17			; force register dependency
                  [0050CC]  5637  	NOP					; force fetch block
File: ev6_pal_macros.mar
         47FF041F [0050CC]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [0050D0]  5638  
         77F12440 [0050D0]  5639  	hw_mtpr	r17, EV6__DTB_IS0		; (6,0L)
         77F1A480 [0050D4]  5640  	hw_mtpr	r17, EV6__DTB_IS1		; (7,1L)
                  [0050D8]  5641  	NOP					; force fetch block
File: ev6_pal_macros.mar
         47FF041F [0050D8]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [0050DC]  5642  	NOP					; are these necessary?
File: ev6_pal_macros.mar
         47FF041F [0050DC]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [0050E0]  5643  
         7BF7A000 [0050E0]  5644  	hw_ret_stall (p23)			; return with stall
                  [0050E4]  5645  
                  [0050E4]  5646  	; 3 tbis
00000000 00000000 [0050E4]  5647  	.ALIGN TBI_FUNCTION_POWER
00000000 00000000 [0050EC]
00000000 00000000 [0050F4]
         00000000 [0050FC]
                  [005100]  5648  	PVC_JSR tbi, dest=1
File: ev6_pal_macros.mar
                  [005100]   534i  pvc_lbl \pcv_index, \pcv_jsr_tbi0, osf, \pcv_jsr_tbi0_inst
File: ev6_osf_pal.mar
                  [005100]  5649  ;
                  [005100]  5650  ; There must be a scoreboard bit -> register dependency chain to prevent
                  [005100]  5651  ; hw_mtpr DTB_ISx from issuing while ANY of scoreboard bits <7:4> are set.
                  [005100]  5652  ;
         64DF10F0 [005100]  5653  	hw_mfpr	p6, <EV6__PAL_BASE ! ^xF0>	; (4-7,0L)
         44C60806 [005104]  5654  	xor	p6, p6, p6			; zap p6
         44D10411 [005108]  5655  	bis	p6, r17, r17			; force register dependency
                  [00510C]  5656  	NOP					; force fetch block
File: ev6_pal_macros.mar
         47FF041F [00510C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [005110]  5657  
         77F12440 [005110]  5658  	hw_mtpr	r17, EV6__DTB_IS0		; (6,0L)
         77F1A480 [005114]  5659  	hw_mtpr	r17, EV6__DTB_IS1		; (7,1L)
                  [005118]  5660  	NOP					; force fetch block
File: ev6_pal_macros.mar
         47FF041F [005118]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [00511C]  5661  	NOP
File: ev6_pal_macros.mar
         47FF041F [00511C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [005120]  5662  
         77F10450 [005120]  5663  	hw_mtpr	r17, EV6__ITB_IS		; (4&6,0L)
         7BF7A000 [005124]  5664  	hw_ret_stall (p23)			; return with stall
                  [005128]  5665  
                  [005128]  5666  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [005128]   176M         GOTO_FREE_CODE
00000000 00000000 [005128]    67M     .align 6
00000000 00000000 [005130]
00000000 00000000 [005138]
File: ev6_osf_pal.mar
                  [005140]  5667  
                  [005140]  5668  ;+
                  [005140]  5669  ; CALL_PAL__WRENT
                  [005140]  5670  ;
                  [005140]  5671  ; Entry:
                  [005140]  5672  ;	p23		pc of instruction following the call_pal instruction
                  [005140]  5673  ;
                  [005140]  5674  ; Function:
                  [005140]  5675  ;	case r17(a1) begin
                  [005140]  5676  ;		0:	entInt	<- r16(a0); break;
                  [005140]  5677  ;		1:	entArith<- r16(a0); break;
                  [005140]  5678  ;		2:	entMM	<- r16(a0); break;
                  [005140]  5679  ;		3:	entIF	<- r16(a0); break;
                  [005140]  5680  ;		4:	entUna	<- r16(a0); break;
                  [005140]  5681  ;		5:	entSys	<- r16(a0); break;
                  [005140]  5682  ;	    other:	break;
                  [005140]  5683  ;	endcase;
                  [005140]  5684  ;
                  [005140]  5685  ; Exit state:
                  [005140]  5686  ;	r16(a0)		unpredictable
                  [005140]  5687  ;	r17(a1)		unpredictable
                  [005140]  5688  ;-
                  [005140]  5689  	START_CALL_PAL <WRENT>
File: ev6_pal_macros.mar
                  [005140]   104i         ASSUME <<OSFPAL_FUNC__WRENT> & <^x40>> eq 0
                  [005140]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002D00]   120i CALL_PAL__WRENT::
File: ev6_osf_pal.mar
                  [002D00]  5690  
         C0800000 [002D00]  5691  	br	p4, call_pal__wrent_addr
                  [002D04]  5692  call_pal__wrent_addr:
         4220D3A5 [002D04]  5693  	cmpult	r17, #6, p5				; see if in range
         2084243C [002D08]  5694  	lda	p4, <wrent_tbl-call_pal__wrent_addr>(p4); base of table
         4A207731 [002D0C]  5695  	sll	r17, #3, r17				; * 8
         E0A00005 [002D10]  5696  	blbc	p5, call_pal__wrent_out			; branch if not in range
                  [002D14]  5697  
         40910404 [002D14]  5698  	addq	p4, r17, p4				; point to function
         46007110 [002D18]  5699  	bic	r16, #3, r16				; clean pc
         44803404 [002D1C]  5700  	bis	p4, #1, p4				; make pal mode
         D3E00000 [002D20]  5701  	bsr	r31, .					; push prediction stack
                  [002D24]  5702  	PVC_JSR	wrent				
File: ev6_pal_macros.mar
                  [002D24]   531i  pvc_lbl \pcv_index, \pcv_jsr_wrent0, osf
File: ev6_osf_pal.mar
         7BE48000 [002D24]  5703  	hw_ret	(p4)					; pop prediction stack
                  [002D28]  5704  							; go do it
                  [002D28]  5705  call_pal__wrent_out:
         7BF78000 [002D28]  5706  	hw_ret	(p23)					; out of range
                  [002D2C]  5707  
                  [002D2C]  5708  	CONT_CALL_PAL
File: ev6_pal_macros.mar
                  [002D2C]   181M     ASSUME <_pal_func_cont> eq 0
                  [002D2C]   189M     ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002D2C]   191M     GOTO_FREE_CODE
                  [005140]    67M     .align 6
File: ev6_osf_pal.mar
                  [005140]  5709  ;
                  [005140]  5710  ; wrent table
                  [005140]  5711  ;
                  [005140]  5712  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
                  [005140]   275i 	.align 6
File: ev6_osf_pal.mar
                  [005140]  5713  wrent_tbl:
                  [005140]  5714  	; 0 entInt
                  [005140]  5715  	PVC_JSR wrent, dest=1
File: ev6_pal_macros.mar
                  [005140]   534i  pvc_lbl \pcv_index, \pcv_jsr_wrent0, osf, \pcv_jsr_wrent0_inst
File: ev6_osf_pal.mar
         7E151040 [005140]  5716  	hw_stq/p r16, PT__ENT_INT(p_temp)		; write it
         7BF78000 [005144]  5717  	hw_ret	(p23)					; return
                  [005148]  5718  
                  [005148]  5719  	; 1 entArith
                  [005148]  5720  	PVC_JSR wrent, dest=1
File: ev6_pal_macros.mar
                  [005148]   534i  pvc_lbl \pcv_index, \pcv_jsr_wrent0, osf, \pcv_jsr_wrent0_inst
File: ev6_osf_pal.mar
         7E151030 [005148]  5721  	hw_stq/p r16, PT__ENT_ARITH(p_temp)		; write it
         7BF78000 [00514C]  5722  	hw_ret	(p23)					; return
                  [005150]  5723  
                  [005150]  5724  	; 2 entMM
                  [005150]  5725  	PVC_JSR wrent, dest=1
File: ev6_pal_macros.mar
                  [005150]   534i  pvc_lbl \pcv_index, \pcv_jsr_wrent0, osf, \pcv_jsr_wrent0_inst
File: ev6_osf_pal.mar
         7E151048 [005150]  5726  	hw_stq/p r16, PT__ENT_MM(p_temp)		; write it
         7BF78000 [005154]  5727  	hw_ret	(p23)					; return
                  [005158]  5728  
                  [005158]  5729  	; 3 entIF
                  [005158]  5730  	PVC_JSR wrent, dest=1
File: ev6_pal_macros.mar
                  [005158]   534i  pvc_lbl \pcv_index, \pcv_jsr_wrent0, osf, \pcv_jsr_wrent0_inst
File: ev6_osf_pal.mar
         7E151038 [005158]  5731  	hw_stq/p r16, PT__ENT_IF(p_temp)		; write it
         7BF78000 [00515C]  5732  	hw_ret	(p23)					; return
                  [005160]  5733  
                  [005160]  5734  	; 4 entUna
                  [005160]  5735  	PVC_JSR wrent, dest=1
File: ev6_pal_macros.mar
                  [005160]   534i  pvc_lbl \pcv_index, \pcv_jsr_wrent0, osf, \pcv_jsr_wrent0_inst
File: ev6_osf_pal.mar
         7E151058 [005160]  5736  	hw_stq/p r16, PT__ENT_UNA(p_temp)		; write it
         7BF78000 [005164]  5737  	hw_ret	(p23)					; return
                  [005168]  5738  
                  [005168]  5739  	; 5 entSys
                  [005168]  5740  	PVC_JSR wrent, dest=1
File: ev6_pal_macros.mar
                  [005168]   534i  pvc_lbl \pcv_index, \pcv_jsr_wrent0, osf, \pcv_jsr_wrent0_inst
File: ev6_osf_pal.mar
         7E151050 [005168]  5741  	hw_stq/p r16, PT__ENT_SYS(p_temp)		; write it
         7BF78000 [00516C]  5742  	hw_ret	(p23)					; return
                  [005170]  5743  
                  [005170]  5744  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [005170]   176M         GOTO_FREE_CODE
00000000 00000000 [005170]    67M     .align 6
00000000 00000000 [005178]
File: ev6_osf_pal.mar
                  [005180]  5745  
                  [005180]  5746  ;+
                  [005180]  5747  ; CALL_PAL__SWPIPL
                  [005180]  5748  ;
                  [005180]  5749  ; Entry:
                  [005180]  5750  ;	p23		pc of instruction following the call_pal instruction
                  [005180]  5751  ;	r16(a0)<2:0>	new ipl
                  [005180]  5752  ;
                  [005180]  5753  ; Function:
                  [005180]  5754  ;	Return the current interrupt priority level in r0(v0), and set the
                  [005180]  5755  ;	interrupt priority level to the value in r16. The new ier bits
                  [005180]  5756  ;	are taken from an ipl-indexed table of quadwords.
                  [005180]  5757  ;
                  [005180]  5758  ; Exit state:
                  [005180]  5759  ;	r0(v0)		PS<IPL>
                  [005180]  5760  ;-
                  [005180]  5761  	START_CALL_PAL <SWPIPL>
File: ev6_pal_macros.mar
                  [005180]   104i         ASSUME <<OSFPAL_FUNC__SWPIPL> & <^x40>> eq 0
                  [005180]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002D40]   120i CALL_PAL__SWPIPL::
File: ev6_osf_pal.mar
                  [002D40]  5762  
                  [002D40]  5763  ASSUME OSF_P_MISC__IPL__S eq 0
                  [002D40]  5764  
         649F1010 [002D40]  5765  	hw_mfpr	p4, EV6__PAL_BASE		; (4,0L) get pal base
                  [002D44]  5766  
         4600F010 [002D44]  5767  	and	r16, #7, r16			; clean ipl
         42040644 [002D48]  5768  	s8addq	r16, p4, p4			; pal base + index
         20840D00 [002D4C]  5769  	lda	p4, ipl_offset(p4)		; pal base + table base + index
         6C841000 [002D50]  5770  	hw_ldq/p p4, (p4)			; get new ier
                  [002D54]  5771  
         46C0F000 [002D54]  5772  	and	p_misc, #<OSF_P_MISC__IPL__M>, r0	; old ipl to r0
         46C0F116 [002D58]  5773  	bic	p_misc, #<OSF_P_MISC__IPL__M>, p_misc	; clear out old ipl
         46D00416 [002D5C]  5774  	or	p_misc, r16, p_misc			; put new ipl in p_misc
                  [002D60]  5775  
         77E40A10 [002D60]  5776  	hw_mtpr	p4, EV6__IER			; (4,0L) write new ier
                  [002D64]  5777  
         7BF7A000 [002D64]  5778  	hw_ret_stall (p23)			; return with stall
                  [002D68]  5779  
                  [002D68]  5780  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002D68]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002D68]   176M         GOTO_FREE_CODE
                  [005180]    67M     .align 6
File: ev6_osf_pal.mar
                  [005180]  5781  
                  [005180]  5782  
                  [005180]  5783  ;+
                  [005180]  5784  ; CALL_PAL__RDPS
                  [005180]  5785  ;
                  [005180]  5786  ; Entry:
                  [005180]  5787  ;	p23		pc of instruction following the call_pal instruction
                  [005180]  5788  ;
                  [005180]  5789  ; Function:
                  [005180]  5790  ;	r0(v0) <- PS
                  [005180]  5791  ;
                  [005180]  5792  ; Exit state:
                  [005180]  5793  ;	r0(v0)		PS
                  [005180]  5794  ;-
                  [005180]  5795  ASSUME OSF_P_MISC__PS__S eq 0
                  [005180]  5796  
                  [005180]  5797  	START_CALL_PAL <RDPS>
File: ev6_pal_macros.mar
                  [005180]   104i         ASSUME <<OSFPAL_FUNC__RDPS> & <^x40>> eq 0
                  [005180]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002D80]   120i CALL_PAL__RDPS::
File: ev6_osf_pal.mar
                  [002D80]  5798  
         46C1F000 [002D80]  5799  	and	p_misc, #OSF_P_MISC__PS__M, r0	; just get PS
                  [002D84]  5800  	NOP					; no hw_ret in 1st fetch block
File: ev6_pal_macros.mar
         47FF041F [002D84]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002D88]  5801  	NOP
File: ev6_pal_macros.mar
         47FF041F [002D88]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002D8C]  5802  	NOP
File: ev6_pal_macros.mar
         47FF041F [002D8C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002D90]  5803  
         7BF78000 [002D90]  5804  	hw_ret	(p23)				; return
                  [002D94]  5805  
                  [002D94]  5806  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002D94]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002D94]   176M         GOTO_FREE_CODE
                  [005180]    67M     .align 6
File: ev6_osf_pal.mar
                  [005180]  5807  
                  [005180]  5808  ;+
                  [005180]  5809  ; CALL_PAL__WRKGP
                  [005180]  5810  ;
                  [005180]  5811  ; Entry:
                  [005180]  5812  ;	p23		pc of instruction following the call_pal instruction
                  [005180]  5813  ;
                  [005180]  5814  ; Function:
                  [005180]  5815  ;	KGP <- r16(a0)
                  [005180]  5816  ;-
                  [005180]  5817  	START_CALL_PAL <WRKGP>
File: ev6_pal_macros.mar
                  [005180]   104i         ASSUME <<OSFPAL_FUNC__WRKGP> & <^x40>> eq 0
                  [005180]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002DC0]   120i CALL_PAL__WRKGP::
File: ev6_osf_pal.mar
                  [002DC0]  5818  
         7E151028 [002DC0]  5819  	hw_stq/p r16, PT__KGP(p_temp)		; write kgp
                  [002DC4]  5820  	NOP					; no hw_ret in 1st fetch block
File: ev6_pal_macros.mar
         47FF041F [002DC4]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002DC8]  5821  	NOP
File: ev6_pal_macros.mar
         47FF041F [002DC8]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002DCC]  5822  	NOP
File: ev6_pal_macros.mar
         47FF041F [002DCC]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002DD0]  5823  
         7BF78000 [002DD0]  5824  	hw_ret	(p23)				; return
                  [002DD4]  5825  
                  [002DD4]  5826  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002DD4]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002DD4]   176M         GOTO_FREE_CODE
                  [005180]    67M     .align 6
File: ev6_osf_pal.mar
                  [005180]  5827  
                  [005180]  5828  ;+
                  [005180]  5829  ; CALL_PAL__WRUSP
                  [005180]  5830  ;
                  [005180]  5831  ; Entry:
                  [005180]  5832  ;	p23		pc of instruction following the call_pal instruction
                  [005180]  5833  ;
                  [005180]  5834  ; Function:
                  [005180]  5835  ;	USP <- r16(a0)
                  [005180]  5836  ;-
                  [005180]  5837  	START_CALL_PAL <WRUSP>
File: ev6_pal_macros.mar
                  [005180]   104i         ASSUME <<OSFPAL_FUNC__WRUSP> & <^x40>> eq 0
                  [005180]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002E00]   120i CALL_PAL__WRUSP::
File: ev6_osf_pal.mar
                  [002E00]  5838  
         7E151020 [002E00]  5839  	hw_stq/p r16, PT__USP(p_temp)		; write usp
                  [002E04]  5840  	NOP					; no hw_ret in 1st fetch block
File: ev6_pal_macros.mar
         47FF041F [002E04]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002E08]  5841  	NOP
File: ev6_pal_macros.mar
         47FF041F [002E08]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002E0C]  5842  	NOP
File: ev6_pal_macros.mar
         47FF041F [002E0C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002E10]  5843  
         7BF78000 [002E10]  5844  	hw_ret	(p23)				; return
                  [002E14]  5845  
                  [002E14]  5846  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002E14]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002E14]   176M         GOTO_FREE_CODE
                  [005180]    67M     .align 6
File: ev6_osf_pal.mar
                  [005180]  5847  
                  [005180]  5848  ;+
                  [005180]  5849  ; CALL_PAL__MTPR_PERFMON
                  [005180]  5850  ;
                  [005180]  5851  ; Entry:
                  [005180]  5852  ;	p23		pc of instruction following the call_pal instruction
                  [005180]  5853  ;	r16(a0)		function select
                  [005180]  5854  ;	r17(a1)		value
                  [005180]  5855  ;
                  [005180]  5856  ; Function:
                  [005180]  5857  ;	Execute indicated performance monitoring function.
                  [005180]  5858  ;
                  [005180]  5859  ; Exit state:
                  [005180]  5860  ;	r0(v0)		Value returned for read
                  [005180]  5861  ;	r17(a1)		UNPREDICTABLE
                  [005180]  5862  ;-
                  [005180]  5863  
                  [005180]  5864  
                  [005180]  5865  ;-----------------------------------------------------------------------
                  [005180]  5866  ;	Arguments and Actions
                  [005180]  5867  ;-----------------------------------------------------------------------
                  [005180]  5868  ;	r16(a0) = 0		Disable performance monitoring
                  [005180]  5869  ;	r17(a1) = bitmask	r17(a1)<0>=1	disable CTR0
                  [005180]  5870  ;				r17(a1)<1>=1	disable CTR1
                  [005180]  5871  ;
                  [005180]  5872  ;	Action: Clear PCTx_EN in I_CTL as directed. If CTRx is already
                  [005180]  5873  ;		disabled, it stays disabled.
                  [005180]  5874  ;-----------------------------------------------------------------------
                  [005180]  5875  ;	r16(a0) = 1		Enable performance monitoring
                  [005180]  5876  ;	r17(a1) = bitmask	r17(a1)<0>=1	enable CTR0
                  [005180]  5877  ;				r17(a1)<1>=1	enable CTR1
                  [005180]  5878  ;
                  [005180]  5879  ;	Action: Set PCTx_EN in I_CTL as directed. If CTRx is already
                  [005180]  5880  ;		enabled, it stays enabled.
                  [005180]  5881  ;-----------------------------------------------------------------------
                  [005180]  5882  ;	r16(a0) = 2		Mux select
                  [005180]  5883  ;	r17(a1) = pctr_ctl	r17(a1)<3:0>	SL1 pass 2.3 (see table)
                  [005180]  5884  ;				r17(a1)<3:2>	SL1 pass 3   (see table)
                  [005180]  5885  ;				r17(a1)<4>	SL0 (see table below)
                  [005180]  5886  ;	Action: Write PCTR_CTL SLx fields.
                  [005180]  5887  ;-----------------------------------------------------------------------
                  [005180]  5888  ;	r16(a0) = 3		Options
                  [005180]  5889  ;	r17(a1) = options	r17(a1)<0>	logging option
                  [005180]  5890  ;					0 => log all processes
                  [005180]  5891  ;					1 => log only selected processes
                  [005180]  5892  ;	Action: If r17(a1)<0> is clear, set SPCE bit in I_CTL
                  [005180]  5893  ;-----------------------------------------------------------------------
                  [005180]  5894  ;	r16(a0) = 5		Read counters
                  [005180]  5895  ;
                  [005180]  5896  ;	Action: Return in r0(v0) the counters of PCTR_CTL
                  [005180]  5897  ;-----------------------------------------------------------------------
                  [005180]  5898  ;	r16(a0) = 6		Write counters
                  [005180]  5899  ;	r17(a1)			r17(a1)<0> Write counter 0
                  [005180]  5900  ;				r17(a1)<1> Write counter 1
                  [005180]  5901  ;				r17(a1)<25:6>  new pctr1 value
                  [005180]  5902  ;				r17(a1)<47:28> new pctr0 value
                  [005180]  5903  ;	Action: Selectively write counter fields in PCTR_CTL
                  [005180]  5904  ;-----------------------------------------------------------------------
                  [005180]  5905  ;	r16(a0) = 7		Enable and write selected counters
                  [005180]  5906  ;	r17(a1) = bitmask	r17(a1)<0>=1	enable and clear PCTR0
                  [005180]  5907  ;				r17(a1)<1>=1	enable and clear PCTR1
                  [005180]  5908  ;
                  [005180]  5909  ;	Action: Write specified counter(s) as directed
                  [005180]  5910  ;		Set PCTx_EN in I_CTL as directed
                  [005180]  5911  ;		User requests a clear by having 0 in the counter fields
                  [005180]  5912  ;-----------------------------------------------------------------------
                  [005180]  5913  ;	r16(a0) = 8		Read i_stat (ProfileMe)
                  [005180]  5914  ;
                  [005180]  5915  ;	Action: Return in r0(v0) the i_stat values
                  [005180]  5916  ;-----------------------------------------------------------------------
                  [005180]  5917  ;	r16(a0) = 9		Read pmpc (ProfileMe)
                  [005180]  5918  ;
                  [005180]  5919  ;	Action: Return in r0(v0) the PC of the last profiled instruction
                  [005180]  5920  ;-----------------------------------------------------------------------
                  [005180]  5921  ;-----------------------------------------------------------------------
                  [005180]  5922  ; Pass 2.3 Aggregate mode
                  [005180]  5923  ;
                  [005180]  5924  ; SL0 mux values
                  [005180]  5925  ;	0	PCTR0 <- cycles
                  [005180]  5926  ;	1	PCTR0 <- retired instructions
                  [005180]  5927  ; SL1 mux values
                  [005180]  5928  ;	0000 	PCTR1 <- cycles
                  [005180]  5929  ;	0001 	PCTR1 <- retired conditional branches
                  [005180]  5930  ;	0010 	PCTR1 <- cycles (retired branch mispredicts not implemented)
                  [005180]  5931  ;	0011 	PCTR1 <- retired dtb single misses * 2 (bats 943)
                  [005180]  5932  ;	0100 	PCTR1 <- retired dtb double misses
                  [005180]  5933  ;	0101 	PCTR1 <- retired itb misses
                  [005180]  5934  ;	0110 	PCTR1 <- retired unaligned traps
                  [005180]  5935  ;	0111 	PCTR1 <- replay traps
                  [005180]  5936  ;-----------------------------------------------------------------------
                  [005180]  5937  ; Pass 3 or higher Aggregate mode
                  [005180]  5938  ;
                  [005180]  5939  ; SL0 mux values
                  [005180]  5940  ;	0	aggregate mode
                  [005180]  5941  ; SL1 mux values
                  [005180]  5942  ;	00	PCTR0 <- retired  PCTR1 <- cycles
                  [005180]  5943  ;	01	PCTR0 <- cycles	  PCTR1 <- undefined
                  [005180]  5944  ;	10	PCTR0 <- retired  PCTR1 <- bcache misses/long probe latency
                  [005180]  5945  ;	11	PCTR0 <- cycles	  PCTR1 <- Mbox replay traps
                  [005180]  5946  ;-----------------------------------------------------------------------
                  [005180]  5947  ; Pass 3 or higher ProfileMe mode
                  [005180]  5948  ;
                  [005180]  5949  ; SL0 mux values
                  [005180]  5950  ;	1	ProfileMe mode
                  [005180]  5951  ; SL1 mux values
                  [005180]  5952  ;	00	PCTR0 <- retired  PCTR1 <- cycles
                  [005180]  5953  ;	01	PCTR0 <- cycles	  PCTR1 <- cycles of delayed retire ptr advance
                  [005180]  5954  ;	10	PCTR0 <- retired  PCTR1 <- bcache misses/long probe latency
                  [005180]  5955  ;	11	PCTR0 <- cycles	  PCTR1 <- Mbox replay traps
                  [005180]  5956  ;-----------------------------------------------------------------------
                  [005180]  5957  ;-----------------------------------------------------------------------
                  [005180]  5958  ; Note that the PPCE (per process counter enable) bit in PCTX, is
                  [005180]  5959  ; set/cleared on swap context, and does not get changed as a result of
                  [005180]  5960  ; a perfmon call.
                  [005180]  5961  ;-----------------------------------------------------------------------
                  [005180]  5962  
                  [005180]  5963  	START_CALL_PAL <WRPERFMON>
File: ev6_pal_macros.mar
                  [005180]   104i         ASSUME <<OSFPAL_FUNC__WRPERFMON> & <^x40>> eq 0
                  [005180]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002E40]   120i CALL_PAL__WRPERFMON::
File: ev6_osf_pal.mar
                  [002E40]  5964  
                  [002E40]  5965  ASSUME EV6__I_CTL__PCT0_EN__S eq ^x12
                  [002E40]  5966  ASSUME EV6__I_CTL__PCT1_EN__S eq ^x13
                  [002E40]  5967  
         4200B5A0 [002E40]  5968  	cmpeq	r16, #5, r0			; check for read counters
         F400092E [002E44]  5969  	bne	r0, call_pal__perfmon_rd	; branch if so
         4200D5A0 [002E48]  5970  	cmpeq	r16, #6, r0			; check for write counters
         F400093C [002E4C]  5971  	bne	r0, call_pal__perfmon_wr	; branch if so
         420115A0 [002E50]  5972  	cmpeq	r16, #8, r0			; check for read i_stat
         F400096A [002E54]  5973  	bne	r0, call_pal__perfmon_rd_istat	; branch if so
         420135A0 [002E58]  5974  	cmpeq	r16, #9, r0			; check for read pmpc
         F400096E [002E5C]  5975  	bne	r0, call_pal__perfmon_rd_pmpc	; branch if so
         420035A0 [002E60]  5976  	cmpeq	r16, #1, r0			; check for enable
         F40008F6 [002E64]  5977  	bne	r0, call_pal__perfmon_en	; branch if so
         420055A0 [002E68]  5978  	cmpeq	r16, #2, r0			; check for mux select
         F4000904 [002E6C]  5979  	bne	r0, call_pal__perfmon_mux	; branch if so
         420075A0 [002E70]  5980  	cmpeq	r16, #3, r0			; check for options
         F4000912 [002E74]  5981  	bne	r0, call_pal__perfmon_opt	; branch if so
                  [002E78]  5982  
                  [002E78]  5983  	CONT_CALL_PAL<WRPERFMON>
File: ev6_pal_macros.mar
                  [002E78]   181M     ASSUME <_pal_func_cont> eq 0
         C3E008C1 [002E78]   186i 	br	r31, CALL_PAL__WRPERFMON_CONT
                  [002E7C]   189M                 ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002E7C]   191M     GOTO_FREE_CODE
                  [005180]    67M     .align 6
                  [005180]   196i CALL_PAL__WRPERFMON_CONT:
File: ev6_osf_pal.mar
                  [005180]  5984  
         4200F5A0 [005180]  5985  	cmpeq	r16, #7, r0			; check for enable and write
         F400008E [005184]  5986  	bne	r0, call_pal__perfmon_en_wr	; branch if so
         F60000A6 [005188]  5987  	bne	r16, call_pal__perfmon_unknown	; branch for unknown
         C3E0000C [00518C]  5988  	br	r31, call_pal__perfmon_dis	; branch for disable
                  [005190]  5989  ;
                  [005190]  5990  ; Disable
                  [005190]  5991  ;	r17(a1) = bitmask	r17(a1)<0>=1	disable CTR0
                  [005190]  5992  ;				r17(a1)<1>=1	disable CTR1
                  [005190]  5993  ;
                  [005190]  5994  ;	Action: Clear PCTx_EN in I_CTL as directed
                  [005190]  5995  ;
                  [005190]  5996  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [005190]   275i 	.align 6
00000000 00000000 [005198]
00000000 00000000 [0051A0]
00000000 00000000 [0051A8]
00000000 00000000 [0051B0]
00000000 00000000 [0051B8]
File: ev6_osf_pal.mar
                  [0051C0]  5997  call_pal__perfmon_dis:
         649F1110 [0051C0]  5998  	hw_mfpr	p4, EV6__I_CTL			; (4,0L) get current control
         46207005 [0051C4]  5999  	and	r17, #3, p5			; clean input
         48A25725 [0051C8]  6000  	sll	p5, #EV6__I_CTL__PCT0_EN__S, p5	; shift into position
         44850104 [0051CC]  6001  	bic	p4, p5, p4			; clear bits as requested
         77E41110 [0051D0]  6002  	hw_mtpr	p4, EV6__I_CTL			; (4,0L)
                  [0051D4]  6003  ;
                  [0051D4]  6004  ; Make sure that the counters are not near overflow so that we
                  [0051D4]  6005  ; avoid interrupts being blocked in anticipation of an overflow interrupt.
                  [0051D4]  6006  ; Rather than checking the whole count, just look at the most significant bit.
                  [0051D4]  6007  ; Zap low nibble of count if most significant bit of count is set and
                  [0051D4]  6008  ; we were asked to disable that counter.
                  [0051D4]  6009  ;
                  [0051D4]  6010  	ALIGN_FETCH_BLOCK <^x47FF041F>
File: ev6_pal_macros.mar
47FF041F 47FF041F [0051D4]   265i 	.align 4, <^x47FF041F>
         47FF041F [0051DC]
File: ev6_osf_pal.mar
                  [0051E0]  6011  
         649F1410 [0051E0]  6012  	hw_mfpr	p4, EV6__PCTR_CTL			; (4,0L) get PCTR_CTL
                  [0051E4]  6013  
         47E1F405 [0051E4]  6014  	bis	r31, #^xF, p5				; get an ^xF
         4885F686 [0051E8]  6015  	srl	p4, #<EV6__PCTR_CTL__PCTR0__S+19>, p6 	; pctr0 msbit to lsbit
         44DF02C5 [0051EC]  6016  	cmovlbc	p6, r31, p5				; zap mask if lsbit=0
         46203006 [0051F0]  6017  	and	r17, #1, p6				; check for disable
         44DF0485 [0051F4]  6018  	cmoveq	p6, r31, p5				; zap mask if dis=0
                  [0051F8]  6019  
         47E1F407 [0051F8]  6020  	bis	r31, #^xF, p7				; get an ^xF
         48833686 [0051FC]  6021  	srl	p4, #<EV6__PCTR_CTL__PCTR1__S+19>, p6 	; pctr1 msbit to lsbit
         44DF02C7 [005200]  6022  	cmovlbc	p6, r31, p7				; zap mask if lsbit=0
         46205006 [005204]  6023  	and	r17, #2, p6				; check for disable
         44DF0487 [005208]  6024  	cmoveq	p6, r31, p7				; zap mask if dis=0
                  [00520C]  6025  
         48A39725 [00520C]  6026  	sll	p5, #EV6__PCTR_CTL__PCTR0__S,  p5	; shift mask into place
         48E0D727 [005210]  6027  	sll	p7, #EV6__PCTR_CTL__PCTR1__S,  p7	; shift mask into place
         44A70407 [005214]  6028  	bis	p5, p7, p7				; or together
         F4E00002 [005218]  6029  	bne	p7, call_pal__perfmon_zap		; zap if non-zero
                  [00521C]  6030  
         77FF2710 [00521C]  6031  	hw_mtpr	r31, <EV6__MM_STAT ! ^x10>		; (4,0L) force retire
         7BF7A000 [005220]  6032  	hw_ret_stall (p23)				; return with stall
                  [005224]  6033  
                  [005224]  6034  call_pal__perfmon_zap:
         44870104 [005224]  6035  	bic	p4, p7, p4				; clear as needed
         77E41410 [005228]  6036  	hw_mtpr	p4, EV6__PCTR_CTL			; (4,0L) write PCTR_CTL
                  [00522C]  6037  
                  [00522C]  6038  	ALIGN_FETCH_BLOCK <^x47FF041F>
File: ev6_pal_macros.mar
         47FF041F [00522C]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
         77FF2710 [005230]  6039  	hw_mtpr	r31, <EV6__MM_STAT ! ^x10>		; (4,0L) force retire
                  [005234]  6040  
         7BF7A000 [005234]  6041  	hw_ret_stall (p23)				; return with stall
                  [005238]  6042  ;
                  [005238]  6043  ; Enable
                  [005238]  6044  ;	r17(a1) = bitmask	r17(a1)<0>=1	enable CTR0
                  [005238]  6045  ;				r17(a1)<1>=1	enable CTR1
                  [005238]  6046  ;
                  [005238]  6047  ;	Action: Set PCTx_EN in I_CTL as directed. If CTRx is already enabled,
                  [005238]  6048  ;		it stays enabled.
                  [005238]  6049  ;
                  [005238]  6050  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [005238]   275i 	.align 6
File: ev6_osf_pal.mar
                  [005240]  6051  call_pal__perfmon_en:
         649F1110 [005240]  6052   	hw_mfpr	p4, EV6__I_CTL			; (4,0L) get current control
         46207005 [005244]  6053  	and	r17, #3, p5			; clean input
         48A25725 [005248]  6054  	sll	p5, #EV6__I_CTL__PCT0_EN__S, p5	; shift into position
         44850404 [00524C]  6055  	bis	p4, p5, p4			; enable bits as requested
         77E41110 [005250]  6056  	hw_mtpr	p4, EV6__I_CTL			; (4,0L)
                  [005254]  6057  
                  [005254]  6058  	ALIGN_FETCH_BLOCK <^x47FF041F>
File: ev6_pal_macros.mar
47FF041F 47FF041F [005254]   265i 	.align 4, <^x47FF041F>
         47FF041F [00525C]
File: ev6_osf_pal.mar
         77FF2710 [005260]  6059  	hw_mtpr	r31, <EV6__MM_STAT ! ^x10>	; (4,0L) force retire
                  [005264]  6060  
         7BF7A000 [005264]  6061  	hw_ret_stall (p23)			; return with stall
                  [005268]  6062  ;
                  [005268]  6063  ; Mux select
                  [005268]  6064  ;	r17(a1) = pctr_ctl	r17(a1)<3:0>	SL1
                  [005268]  6065  ;				r17(a1)<4>	SL0
                  [005268]  6066  ;					0 => cycles
                  [005268]  6067  ;					1 => retired instructions
                  [005268]  6068  ;	Action: Write PCTR_CTL SLx fields.
                  [005268]  6069  ;
                  [005268]  6070  ASSUME EV6__PCTR_CTL__SL1__S eq 2
                  [005268]  6071  ASSUME EV6__PCTR_CTL__SL0__S eq 4
                  [005268]  6072  
                  [005268]  6073  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [005268]   275i 	.align 6
00000000 00000000 [005270]
00000000 00000000 [005278]
File: ev6_osf_pal.mar
                  [005280]  6074  call_pal__perfmon_mux:
         649F1410 [005280]  6075  	hw_mfpr	p4, EV6__PCTR_CTL		; (4,0L) get current control
         47E3F406 [005284]  6076  	bis	r31, #^x1F, p6			; cleaning mask
         4623F005 [005288]  6077  	and	r17, #^x1F, p5			; clean input
         44860104 [00528C]  6078  	bic	p4, p6, p4			; clean mux
         44850404 [005290]  6079  	bis	p4, p5, p4			; or in new mux values
         77E41410 [005294]  6080  	hw_mtpr	p4, EV6__PCTR_CTL		; (4,0L)
                  [005298]  6081  
                  [005298]  6082  	ALIGN_FETCH_BLOCK <^x47FF041F>
File: ev6_pal_macros.mar
47FF041F 47FF041F [005298]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
         77FF2710 [0052A0]  6083  	hw_mtpr	r31, <EV6__MM_STAT ! ^x10>	; (4,0L) force retire
                  [0052A4]  6084  
         7BF7A000 [0052A4]  6085  	hw_ret_stall (p23)			; return with stall
                  [0052A8]  6086  ;
                  [0052A8]  6087  ; Options
                  [0052A8]  6088  ;	r17(a1) = options	r17(a1)<0>	logging option
                  [0052A8]  6089  ;					0 => log all processes
                  [0052A8]  6090  ;					1 => log only selected processes
                  [0052A8]  6091  ;	Action: If r17(a1)<0> is clear, set SPCE bit in I_CTL
                  [0052A8]  6092  ;
                  [0052A8]  6093  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [0052A8]   275i 	.align 6
00000000 00000000 [0052B0]
00000000 00000000 [0052B8]
File: ev6_osf_pal.mar
                  [0052C0]  6094  call_pal__perfmon_opt:
         649F1110 [0052C0]  6095  	hw_mfpr	p4, EV6__I_CTL			; (4,0L) get I_CTL
         47E03405 [0052C4]  6096  	bis	r31, #1, p5			; get a 1
         48A01725 [0052C8]  6097  	sll	p5, #EV6__I_CTL__SPCE__S, p5	; get into spce position
         44850104 [0052CC]  6098  	bic	p4, p5, p4			; clear spce
         463F0285 [0052D0]  6099  	cmovlbs	r17, r31, p5			; if lbs, just selected process
         44850404 [0052D4]  6100  	bis	p4, p5, p4			; or new spce in
         77E41110 [0052D8]  6101  	hw_mtpr	p4, EV6__I_CTL			; (4,0L) write I_CTL
                  [0052DC]  6102  
                  [0052DC]  6103  	ALIGN_FETCH_BLOCK <^x47FF041F>
File: ev6_pal_macros.mar
         47FF041F [0052DC]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
         77FF2710 [0052E0]  6104  	hw_mtpr	r31, <EV6__MM_STAT ! ^x10>	; (4,0L) force retire
                  [0052E4]  6105  
         7BF7A000 [0052E4]  6106  	hw_ret_stall (p23)			; return with stall
                  [0052E8]  6107  ;
                  [0052E8]  6108  ; Read counters
                  [0052E8]  6109  ;
                  [0052E8]  6110  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [0052E8]   275i 	.align 6
00000000 00000000 [0052F0]
00000000 00000000 [0052F8]
File: ev6_osf_pal.mar
                  [005300]  6111  call_pal__perfmon_rd:
         641F1410 [005300]  6112  	hw_mfpr	r0, EV6__PCTR_CTL		; (4,0L) get PCTR_CTL
                  [005304]  6113  
         7BF78000 [005304]  6114  	hw_ret	(p23)				; just return, no changes
                  [005308]  6115  ;
                  [005308]  6116  ; Write counters selectively
                  [005308]  6117  ;	r17(a1)			r17(a1)<0> Write counter 0
                  [005308]  6118  ;				r17(a1)<1> Write counter 1
                  [005308]  6119  ;				r17(a1)<25:6>  new ctr1 value
                  [005308]  6120  ;				r17(a1)<47:28> new ctr0 value
                  [005308]  6121  ;	Action: Selectively write counter fields in PCTR_CTL
                  [005308]  6122  ;
                  [005308]  6123  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [005308]   275i 	.align 6
00000000 00000000 [005310]
00000000 00000000 [005318]
00000000 00000000 [005320]
00000000 00000000 [005328]
00000000 00000000 [005330]
00000000 00000000 [005338]
File: ev6_osf_pal.mar
                  [005340]  6124  call_pal__perfmon_wr:
         649F1410 [005340]  6125  	hw_mfpr	p4, EV6__PCTR_CTL		; (4,0L) get PCTR_CTL
                  [005344]  6126  	GET_32CONS p5, <^xFFFFF>, r31		; get mask for count field
File: ev6_pal_macros.mar
                  [005344]   239i  ASSUME <^xFFFFF> le  <^x7FFFFFFF>
         24BF0010 [005344]   240M 	ldah	p5,<<^xFFFFF>+32768>@-16(r31); + xxx<31:16>
         20A5FFFF [005348]   241M 	lda	p5,<<^xFFFFF> & ^XFFFF>(p5) ; r31+xxx<15:0>
File: ev6_osf_pal.mar
                  [00534C]  6127  
         E2200004 [00534C]  6128  	blbc	r17, call_pal__perfmon_wr_1	; if clear, don't write 0
         48A39726 [005350]  6129  	sll	p5, #EV6__PCTR_CTL__PCTR0__S, p6; mask for pctr0
         46260007 [005354]  6130  	and	r17, p6, p7			; new pctr0
         44860104 [005358]  6131  	bic	p4, p6, p4			; clear old pctr0
         44870404 [00535C]  6132  	bis	p4, p7, p4			; or in new pctr0
                  [005360]  6133  
                  [005360]  6134  call_pal__perfmon_wr_1:
         4A203686 [005360]  6135  	srl	r17, #1, p6			; now look at pctr1
         E0C00004 [005364]  6136  	blbc	p6, call_pal__perfmon_wr_ipr	; if clear, go on to write
         48A0D726 [005368]  6137  	sll	p5, #EV6__PCTR_CTL__PCTR1__S, p6; mask for pctr1
         46260007 [00536C]  6138  	and	r17, p6, p7			; new pctr1
         44860104 [005370]  6139  	bic	p4, p6, p4			; clear old pctr1
         44870404 [005374]  6140  	bis	p4, p7, p4			; or in new pctr1
                  [005378]  6141  
                  [005378]  6142  call_pal__perfmon_wr_ipr:
                  [005378]  6143  ;
                  [005378]  6144  ; To make counter accurate, we no longer zap the lower nibble. But the user
                  [005378]  6145  ; must be careful with the values! If the counter is near overflow and
                  [005378]  6146  ; counting is disabled, interrupts can be blocked in anticipation of an
                  [005378]  6147  ; overflow interrupt.
                  [005378]  6148  ;
         77E41410 [005378]  6149  	hw_mtpr	p4, EV6__PCTR_CTL		; (4,0L) write PCTR_CTL
                  [00537C]  6150  
                  [00537C]  6151  	ALIGN_FETCH_BLOCK <^x47FF041F>
File: ev6_pal_macros.mar
         47FF041F [00537C]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_pal.mar
         77FF2710 [005380]  6152  	hw_mtpr	r31, <EV6__MM_STAT ! ^x10>	; (4,0L) force retire
                  [005384]  6153  
         7BF7A000 [005384]  6154  	hw_ret_stall (p23)			; return with stall
                  [005388]  6155  ;
                  [005388]  6156  ; Enable and write specified counters
                  [005388]  6157  ;	r17(a1) = bitmask	r17(a1)<0>=1	enable CTR0
                  [005388]  6158  ;				r17(a1)<1>=1	enable CTR1
                  [005388]  6159  ;
                  [005388]  6160  ;	Action: Write specified counter(s)
                  [005388]  6161  ;		Set PCTx_EN in I_CTL as directed
                  [005388]  6162  ;
                  [005388]  6163  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [005388]   275i 	.align 6
00000000 00000000 [005390]
00000000 00000000 [005398]
00000000 00000000 [0053A0]
00000000 00000000 [0053A8]
00000000 00000000 [0053B0]
00000000 00000000 [0053B8]
File: ev6_osf_pal.mar
                  [0053C0]  6164  call_pal__perfmon_en_wr:
         649F1110 [0053C0]  6165   	hw_mfpr	p4, EV6__I_CTL			; (4,0L) get current control
         46207005 [0053C4]  6166  	and	r17, #3, p5			; clean input
         48A25725 [0053C8]  6167  	sll	p5, #EV6__I_CTL__PCT0_EN__S, p5	; shift into position
         44850404 [0053CC]  6168  	bis	p4, p5, p4			; enable bits as requested
         77E41110 [0053D0]  6169  	hw_mtpr	p4, EV6__I_CTL			; (4,0L)
         C3FFFFDA [0053D4]  6170  	br	r31, call_pal__perfmon_wr	; write selected counters
                  [0053D8]  6171  ;
                  [0053D8]  6172  ; Read I_STAT
                  [0053D8]  6173  ;
                  [0053D8]  6174  EV6__I_STAT__PRFME__S = ^x1e	
                  [0053D8]  6175  EV6__I_STAT__PRFME__V = ^xb	
                  [0053D8]  6176  EV6__I_STAT__PRFME__M = ^x7FF
                  [0053D8]  6177  
                  [0053D8]  6178  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [0053D8]   275i 	.align 6
00000000 00000000 [0053E0]
00000000 00000000 [0053E8]
00000000 00000000 [0053F0]
00000000 00000000 [0053F8]
File: ev6_osf_pal.mar
                  [005400]  6179  
                  [005400]  6180  call_pal__perfmon_rd_istat:
         641F1610 [005400]  6181  	hw_mfpr	r0, EV6__I_STAT			; (4,0L) get I_STAT
         4803D680 [005404]  6182  	srl	r0, #EV6__I_STAT__PRFME__S, r0	; clean <29:0>
         209F07FF [005408]  6183  	lda	p4, EV6__I_STAT__PRFME__M(r31)	; mask for cleaning
         44800000 [00540C]  6184  	and	p4, r0, r0			; mask
         4803D720 [005410]  6185  	sll	r0, #EV6__I_STAT__PRFME__S,r0	; shift back
         7BF78000 [005414]  6186  	hw_ret	(p23)				; just return, no changes
                  [005418]  6187  ;
                  [005418]  6188  ; Read pmpc
                  [005418]  6189  ;
                  [005418]  6190  call_pal__perfmon_rd_pmpc:
         641F0510 [005418]  6191  	hw_mfpr	r0, EV6__PMPC			; get PMPC
         44005100 [00541C]  6192  	bic	r0, #2, r0			; clear RAZ bit to be neat
         7BF78000 [005420]  6193  	hw_ret	(p23)				; just return, no changes
                  [005424]  6194  ;
                  [005424]  6195  ; Unknown function
                  [005424]  6196  ;
                  [005424]  6197  call_pal__perfmon_unknown:
                  [005424]  6198  
         7BF78000 [005424]  6199  	hw_ret	(p23)				; just return
                  [005428]  6200  
                  [005428]  6201  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [005428]   176M         GOTO_FREE_CODE
00000000 00000000 [005428]    67M     .align 6
00000000 00000000 [005430]
00000000 00000000 [005438]
File: ev6_osf_pal.mar
                  [005440]  6202  
                  [005440]  6203  ;+
                  [005440]  6204  ; CALL_PAL__RDUSP
                  [005440]  6205  ;
                  [005440]  6206  ; Entry:
                  [005440]  6207  ;	p23		pc of instruction following the call_pal instruction
                  [005440]  6208  ;
                  [005440]  6209  ; Function:
                  [005440]  6210  ;	r0(v0) <- USP
                  [005440]  6211  ;-
                  [005440]  6212  	START_CALL_PAL <RDUSP>
File: ev6_pal_macros.mar
                  [005440]   104i         ASSUME <<OSFPAL_FUNC__RDUSP> & <^x40>> eq 0
                  [005440]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002E80]   120i CALL_PAL__RDUSP::
File: ev6_osf_pal.mar
                  [002E80]  6213  
         6C151020 [002E80]  6214  	hw_ldq/p r0, PT__USP(p_temp)		; read usp
                  [002E84]  6215  	NOP					; no hw_ret in 1st fetch block
File: ev6_pal_macros.mar
         47FF041F [002E84]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002E88]  6216  	NOP
File: ev6_pal_macros.mar
         47FF041F [002E88]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002E8C]  6217  	NOP
File: ev6_pal_macros.mar
         47FF041F [002E8C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002E90]  6218  
         7BF78000 [002E90]  6219  	hw_ret	(p23)				; return
                  [002E94]  6220  
                  [002E94]  6221  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002E94]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002E94]   176M         GOTO_FREE_CODE
                  [005440]    67M     .align 6
File: ev6_osf_pal.mar
                  [005440]  6222  
                  [005440]  6223  
                  [005440]  6224  ;+
                  [005440]  6225  ; CALL_PAL__003B
                  [005440]  6226  ;
                  [005440]  6227  ; Entry:
                  [005440]  6228  ;	r16		0xBAC
                  [005440]  6229  ;	p23		pc of instruction following the call_pal instruction
                  [005440]  6230  ;
                  [005440]  6231  ; Function:
                  [005440]  6232  ;	Return in palmode. For FP emulation.
                  [005440]  6233  ;-
                  [005440]  6234  .if ne ev6_p1
                  [005440]  6235  
                  [005440]  6236  OSFPAL_FUNC__003B = ^x3B
                  [005440]  6237  
                  [005440]  6238  	START_CALL_PAL <003B>
                  [005440]  6239  
                  [005440]  6240  	lda	p4, ^xBAC(r31)			; test for ^xBAC
                  [005440]  6241  	cmpeq	p4, r16, p4
                  [005440]  6242  	bis	r31, r31, r31
                  [005440]  6243  	bis	r31, r31, r31
                  [005440]  6244  
                  [005440]  6245  	beq	p4, call_pal__003B_fail		; fail if not ^xBAC
                  [005440]  6246  	sll	p23, #22, p23
                  [005440]  6247  	srl	p23, #22, p23			; clean off kseg
                  [005440]  6248  	bis	p23, #1, p23			; or in pal-mode bit
                  [005440]  6249  	hw_ret	(p23)				; return in pal-mode
                  [005440]  6250  
                  [005440]  6251  call_pal__003B_fail:
                  [005440]  6252  	br	r31, trap__opcdec_call_pal	; take an opcdec
                  [005440]  6253  
                  [005440]  6254  	END_CALL_PAL
                  [005440]  6255  .endc
                  [005440]  6256  
                  [005440]  6257  
                  [005440]  6258  ;+
                  [005440]  6259  ; CALL_PAL__WHAMI
                  [005440]  6260  ;
                  [005440]  6261  ; Entry:
                  [005440]  6262  ;	p23		pc of instruction following the call_pal instruction
                  [005440]  6263  ;
                  [005440]  6264  ; Function:
                  [005440]  6265  ;	r0(v0) <- WHAMI
                  [005440]  6266  ;-
                  [005440]  6267  	START_CALL_PAL <WHAMI>
File: ev6_pal_macros.mar
                  [005440]   104i         ASSUME <<OSFPAL_FUNC__WHAMI> & <^x40>> eq 0
                  [005440]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002F00]   120i CALL_PAL__WHAMI::
File: ev6_osf_pal.mar
                  [002F00]  6268  
         6C151098 [002F00]  6269  	hw_ldq/p r0, PT__WHAMI(p_temp)		; get whami
                  [002F04]  6270  	NOP
File: ev6_pal_macros.mar
         47FF041F [002F04]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002F08]  6271  	NOP
File: ev6_pal_macros.mar
         47FF041F [002F08]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002F0C]  6272  	NOP					; no hw_ret in 1st fetch block
File: ev6_pal_macros.mar
         47FF041F [002F0C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [002F10]  6273  
         7BF78000 [002F10]  6274  	hw_ret	(p23)				; return
                  [002F14]  6275  
                  [002F14]  6276  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002F14]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002F14]   176M         GOTO_FREE_CODE
                  [005440]    67M     .align 6
File: ev6_osf_pal.mar
                  [005440]  6277  
                  [005440]  6278  ;+
                  [005440]  6279  ; CALL_PAL__RETSYS
                  [005440]  6280  ;
                  [005440]  6281  ; Entry:
                  [005440]  6282  ;	p23		pc of instruction following the call_pal instruction
                  [005440]  6283  ;
                  [005440]  6284  ; Function:
                  [005440]  6285  ;	The return from system call instruction pops the return address
                  [005440]  6286  ;	and the user mode global pointer form the kernel stack. It then
                  [005440]  6287  ;	saves the kernal stack pointer, sets the mode to user, sets the
                  [005440]  6288  ;	IPL to 0, and enters the user mode code at the address popped
                  [005440]  6289  ;	off the stack. In addition the interrupt and load lock flags
                  [005440]  6290  ;	have been cleared.
                  [005440]  6291  ;
                  [005440]  6292  ; Note:
                  [005440]  6293  ;	For now save pc+4. To be more accurate, we may want to save pc.
                  [005440]  6294  ;	For ev5, just pc+4 was used. This pc is used for ksp not valid
                  [005440]  6295  ;	halts.
                  [005440]  6296  ; Note:
                  [005440]  6297  ;	Any load below clears the lock flag.
                  [005440]  6298  ;-
                  [005440]  6299  	START_CALL_PAL <RETSYS>
File: ev6_pal_macros.mar
                  [005440]   104i         ASSUME <<OSFPAL_FUNC__RETSYS> & <^x40>> eq 0
                  [005440]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002F40]   120i CALL_PAL__RETSYS::
File: ev6_osf_pal.mar
                  [002F40]  6300  
                  [002F40]  6301  ASSUME OSF_P_MISC__PS__S eq 0
                  [002F40]  6302  ASSUME EV6__PS__CM__S eq 3
                  [002F40]  6303  
         7EF51060 [002F40]  6304  	hw_stq/p p23, PT__STACK_PC(p_temp)		; in case of fault
                  [002F44]  6305  
         A69E0008 [002F44]  6306  	ldq	p20, OSF_FRM__PC(r30)			; get pc
         A7BE0010 [002F48]  6307  	ldq	r29, OSF_FRM__GP(r30)			; get gp
                  [002F4C]  6308  
         46807117 [002F4C]  6309  	bic	p20, #3, p23				; clean pc, move to p23
         63FFE000 [002F50]  6310  	rc	r31					; clear interrupt flag
                  [002F54]  6311  
         229E0030 [002F54]  6312  	lda	p20, OSF_FRM__SIZE(r30)			; pop kernel stack
         6FD51020 [002F58]  6313  	hw_ldq/p r30, PT__USP(p_temp)			; get usp
         7E951018 [002F5C]  6314  	hw_stq/p p20, PT__KSP(p_temp)			; save kernel stack
                  [002F60]  6315  ;
                  [002F60]  6316  ; Now set up for cm=1 and ipl=0.
                  [002F60]  6317  ;
         649F1010 [002F60]  6318  	hw_mfpr	p4, EV6__PAL_BASE			; (4,0L) get pal base
         20840D00 [002F64]  6319  	lda	p4, ipl_offset(p4)			; pal base + table base
         6C841000 [002F68]  6320  	hw_ldq/p p4, (p4)				; get new ier
                  [002F6C]  6321  
                  [002F6C]  6322  	CONT_CALL_PAL <RETSYS>				; finish in new space
File: ev6_pal_macros.mar
                  [002F6C]   181M     ASSUME <_pal_func_cont> eq 0
         C3E00934 [002F6C]   186i 	br	r31, CALL_PAL__RETSYS_CONT
                  [002F70]   189M                 ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002F70]   191M     GOTO_FREE_CODE
                  [005440]    67M     .align 6
                  [005440]   196i CALL_PAL__RETSYS_CONT:
File: ev6_osf_pal.mar
                  [005440]  6323  
         46C1F116 [005440]  6324  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc	; clean ps
         46C11416 [005444]  6325  	bis	p_misc, #<1@OSF_P_MISC__CM__S>, p_misc	; new ps with mode=user
         44811404 [005448]  6326  	bis	p4, #<1@EV6__PS__CM__S>, p4		; new ier and new cm
                  [00544C]  6327  
         77E40B10 [00544C]  6328  	hw_mtpr	p4, EV6__IER_CM				; (4,0L) new ier_cm
                  [005450]  6329  
         7BF7A000 [005450]  6330  	hw_ret_stall (p23)				; return
                  [005454]  6331  
                  [005454]  6332  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [005454]   176M         GOTO_FREE_CODE
00000000 00000000 [005454]    67M     .align 6
00000000 00000000 [00545C]
00000000 00000000 [005464]
00000000 00000000 [00546C]
00000000 00000000 [005474]
         00000000 [00547C]
File: ev6_osf_pal.mar
                  [005480]  6333  
                  [005480]  6334  ;+
                  [005480]  6335  ; CALL_PAL__WRINT
                  [005480]  6336  ;
                  [005480]  6337  ; Entry:
                  [005480]  6338  ;	p23		pc of instruction following the call_pal instruction
                  [005480]  6339  ;	r16(a0)		maximum nmber of interval clock ticks to skip
                  [005480]  6340  ;
                  [005480]  6341  ; Function:
                  [005480]  6342  ;	The wait for interrupt instruction requests that, if possible, the
                  [005480]  6343  ;	PALcode wait for the first of either of the following conditions
                  [005480]  6344  ;	before returning:
                  [005480]  6345  ;		any interrupt other than a clock tick
                  [005480]  6346  ;		the first clock tick after the specified number
                  [005480]  6347  ;
                  [005480]  6348  ; Exit state:
                  [005480]  6349  ;	r0(v0)		number of interval clock ticks actually skipped
                  [005480]  6350  ;
                  [005480]  6351  ;-
                  [005480]  6352  
                  [005480]  6353  	START_CALL_PAL <WTINT>
File: ev6_pal_macros.mar
                  [005480]   104i         ASSUME <<OSFPAL_FUNC__WTINT> & <^x40>> eq 0
                  [005480]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002F80]   120i CALL_PAL__WTINT::
File: ev6_osf_pal.mar
                  [002F80]  6354  
                  [002F80]  6355  .if eq reference_platform
                  [002F80]  6356  
                  [002F80]  6357  	hw_ret	(p23)				; return
                  [002F80]  6358  
                  [002F80]  6359  .iff
                  [002F80]  6360  
                  [002F80]  6361  	br	r31, sys__wtint			; handle in system module
                  [002F80]  6362  
                  [002F80]  6363  .endc
                  [002F80]  6360I 
         C3E00A04 [002F80]  6361I 	br	r31, sys__wtint			; handle in system module
                  [002F84]  6362I 
                  [002F84]  6364  
                  [002F84]  6365  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [002F84]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002F84]   176M         GOTO_FREE_CODE
                  [005480]    67M     .align 6
File: ev6_osf_pal.mar
                  [005480]  6366  
                  [005480]  6367  
                  [005480]  6368  ;+
                  [005480]  6369  ; CALL_PAL__RTI
                  [005480]  6370  ;
                  [005480]  6371  ; Entry:
                  [005480]  6372  ;	p23		pc of instruction following the call_pal instruction
                  [005480]  6373  ;
                  [005480]  6374  ; Function:
                  [005480]  6375  ;	The return from fault, trap, or interrupt instruction pops the
                  [005480]  6376  ;	kernel stack, restoring a0..a2, PS, PC, GP. If the new mode is user,
                  [005480]  6377  ;	the kernel stack is saved and the user stack is restored.
                  [005480]  6378  ;	Any load below clears the lock flag.
                  [005480]  6379  ;-
                  [005480]  6380  	START_CALL_PAL <RTI>
File: ev6_pal_macros.mar
                  [005480]   104i         ASSUME <<OSFPAL_FUNC__RTI> & <^x40>> eq 0
                  [005480]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [002FC0]   120i CALL_PAL__RTI::
File: ev6_osf_pal.mar
                  [002FC0]  6381  
                  [002FC0]  6382  ASSUME OSF_P_MISC__PS__S eq 0
                  [002FC0]  6383  
         7EF51060 [002FC0]  6384  	hw_stq/p p23, PT__STACK_PC(p_temp)		; in case of fault
                  [002FC4]  6385  
         A69E0000 [002FC4]  6386  	ldq	p20, OSF_FRM__PS(r30)			; get ps
         A65E0028 [002FC8]  6387  	ldq	r18, OSF_FRM__A2(r30)			; get a2
                  [002FCC]  6388  							; 1.39 last possible
                  [002FCC]  6389  							;   dfault or tnv
                  [002FCC]  6390  
         A7BE0010 [002FCC]  6391  	ldq	r29, OSF_FRM__GP(r30)			; get gp
         A61E0018 [002FD0]  6392  	ldq	r16, OSF_FRM__A0(r30)			; get a0
         A63E0020 [002FD4]  6393  	ldq	r17, OSF_FRM__A1(r30)			; get a1
                  [002FD8]  6394  
         A6FE0008 [002FD8]  6395  	ldq	p23, OSF_FRM__PC(r30)			; 1.39 get pc
         46E07117 [002FDC]  6396  	bic	p23, #3, p23				; clean return pc
         63FFE000 [002FE0]  6397  	rc	r31					; clear interrupt flag
                  [002FE4]  6398  
         46811004 [002FE4]  6399  	and	p20, #<1@OSF_PS__CM__S>, p4		; get mode
         E4800937 [002FE8]  6400  	beq	p4, call_pal__rti_to_kern		; br if rti to kernel
                  [002FEC]  6401  
                  [002FEC]  6402  	CONT_CALL_PAL <RTI>
File: ev6_pal_macros.mar
                  [002FEC]   181M     ASSUME <_pal_func_cont> eq 0
         C3E00924 [002FEC]   186i 	br	r31, CALL_PAL__RTI_CONT
                  [002FF0]   189M                 ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [002FF0]   191M     GOTO_FREE_CODE
                  [005480]    67M     .align 6
                  [005480]   196i CALL_PAL__RTI_CONT:
File: ev6_osf_pal.mar
                  [005480]  6403  ;
                  [005480]  6404  ; rti to user mode
                  [005480]  6405  ;
                  [005480]  6406  ; Some platforms, such as those with tsunami, have a problem with the
                  [005480]  6407  ; latency between clearing an interrupt and the interrupt being deasserted.
                  [005480]  6408  ; Those platforms are opting to, on isum<device_irq> set, write to
                  [005480]  6409  ; a tsunami csr to deassert the interrupt. A real interrupt will
                  [005480]  6410  ; re-assert on the next polling loop.
                  [005480]  6411  ;
                  [005480]  6412  
                  [005480]  6413  .if ne	check_interrupt_pending
                  [005480]  6414  	hw_mfpr	p6, EV6__ISUM				; (0L) get ISUM
                  [005480]  6415  .endc
         64DF0D00 [005480]  6414I 	hw_mfpr	p6, EV6__ISUM				; (0L) get ISUM
                  [005484]  6416  
         229E0030 [005484]  6417  	lda	p20, OSF_FRM__SIZE(r30)			; pop kernel stack
         6FD51020 [005488]  6418  	hw_ldq/p r30, PT__USP(p_temp)			; get usp
         7E951018 [00548C]  6419  	hw_stq/p p20, PT__KSP(p_temp)			; save kernel stack
                  [005490]  6420  ;
                  [005490]  6421  ; Now set up for cm=1 and ipl=0.
                  [005490]  6422  ;
         649F1010 [005490]  6423  	hw_mfpr	p4, EV6__PAL_BASE			; (4,0L) get pal base
         20840D00 [005494]  6424  	lda	p4, ipl_offset(p4)			; pal base + table base
         6C841000 [005498]  6425  	hw_ldq/p p4, (p4)				; get new ier
                  [00549C]  6426  
         46C1F116 [00549C]  6427  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc	; clean ps
         46C11416 [0054A0]  6428  	bis	p_misc, #<1@OSF_P_MISC__CM__S>, p_misc	; new ps with mode=user
         44811404 [0054A4]  6429  	bis	p4, #<1@EV6__PS__CM__S>, p4		; new ier and new cm
                  [0054A8]  6430  
                  [0054A8]  6431  .if ne	check_interrupt_pending
                  [0054A8]  6432  	xor	p6, p6, p5			; interlock isum and ier
                  [0054A8]  6433  	bis	p5, p4, p4			; interlock isum and ier
                  [0054A8]  6434  .endc
         44C60805 [0054A8]  6432I 	xor	p6, p6, p5			; interlock isum and ier
         44A40404 [0054AC]  6433I 	bis	p5, p4, p4			; interlock isum and ier
                  [0054B0]  6435  
         77E40B10 [0054B0]  6436  	hw_mtpr	p4, EV6__IER_CM			; (4,0L) new ier_cm
                  [0054B4]  6437  
                  [0054B4]  6438  .if eq	check_interrupt_pending
                  [0054B4]  6439  	hw_ret_stall (p23)			; rei to non-kern
                  [0054B4]  6440  .iff
                  [0054B4]  6441  	lda	p4, IRQ_DEV__M(r31)		; mask of IRQ(s) (IRQ1)
                  [0054B4]  6442  	sll	p4, #EV6__ISUM__EI__S, p4	; shift into position
                  [0054B4]  6443  	and	p6, p4, p4			; check for IRQ
                  [0054B4]  6444  
                  [0054B4]  6445  	bne	p4, sys__deassert_interrupt	; go off to deassert
                  [0054B4]  6446  	hw_ret_stall (p23)			; otherwise finish the rei
                  [0054B4]  6447  .endc
         209F0002 [0054B4]  6441I 	lda	p4, IRQ_DEV__M(r31)		; mask of IRQ(s) (IRQ1)
         48843724 [0054B8]  6442I 	sll	p4, #EV6__ISUM__EI__S, p4	; shift into position
         44C40004 [0054BC]  6443I 	and	p6, p4, p4			; check for IRQ
                  [0054C0]  6444I 
         F480014F [0054C0]  6445I 	bne	p4, sys__deassert_interrupt	; go off to deassert
         7BF7A000 [0054C4]  6446I 	hw_ret_stall (p23)			; otherwise finish the rei
                  [0054C8]  6448  
                  [0054C8]  6449  ;
                  [0054C8]  6450  ; rti to kernel mode
                  [0054C8]  6451  ;
                  [0054C8]  6452  ; Current state:
                  [0054C8]  6453  ;	p20		new ps
                  [0054C8]  6454  ;	p23		new pc, cleaned
                  [0054C8]  6455  ;
                  [0054C8]  6456  ; Note: probably don't need to save kernel stack to PT__KSP,
                  [0054C8]  6457  ;	but it doesn't hurt.
                  [0054C8]  6458  ;
                  [0054C8]  6459  ; Some platforms, such as those with tsunami, have a problem with the
                  [0054C8]  6460  ; latency between clearing an interrupt and the interrupt being deasserted.
                  [0054C8]  6461  ; Those platforms are opting to, on isum<device_irq> set, write to
                  [0054C8]  6462  ; a tsunami csr to deassert the interrupt. A real interrupt will
                  [0054C8]  6463  ; re-assert on the next polling loop.
                  [0054C8]  6464  ;
                  [0054C8]  6465  call_pal__rti_to_kern:
                  [0054C8]  6466  
                  [0054C8]  6467  .if ne	check_interrupt_pending
                  [0054C8]  6468  	hw_mfpr	p6, EV6__ISUM				; (0L) get ISUM	
                  [0054C8]  6469  .endc
         64DF0D00 [0054C8]  6468I 	hw_mfpr	p6, EV6__ISUM				; (0L) get ISUM	
                  [0054CC]  6470  
         23DE0030 [0054CC]  6471  	lda	r30, OSF_FRM__SIZE(r30)			; pop kernel stack
         7FD51018 [0054D0]  6472  	hw_stq/p r30, PT__KSP(p_temp)			; save kernel stack
                  [0054D4]  6473  ;
                  [0054D4]  6474  ; Now set up for new PS with cm=0, new ipl.
                  [0054D4]  6475  ;
         649F1010 [0054D4]  6476  	hw_mfpr	p4, EV6__PAL_BASE			; (4,0L) get pal base
                  [0054D8]  6477  
         4680F014 [0054D8]  6478  	and	p20, #OSF_P_MISC__IPL__M, p20	; clean ps
         42840644 [0054DC]  6479  	s8addq	p20, p4, p4			; pal base + index
         20840D00 [0054E0]  6480  	lda	p4, ipl_offset(p4)		; pal base + table base + index
         6C841000 [0054E4]  6481  	hw_ldq/p p4, (p4)			; get new ier
                  [0054E8]  6482  
         46C0F116 [0054E8]  6483  	bic	p_misc, #<OSF_P_MISC__IPL__M>, p_misc	; clear out old ipl
         46D40416 [0054EC]  6484  	or	p_misc, p20, p_misc			; put new ipl in p_misc
                  [0054F0]  6485  
                  [0054F0]  6486  .if ne	check_interrupt_pending
                  [0054F0]  6487  	xor	p6, p6, p5			; interlock isum and ier
                  [0054F0]  6488  	bis	p5, p4, p4			; interlock isum and ier
                  [0054F0]  6489  .endc
         44C60805 [0054F0]  6487I 	xor	p6, p6, p5			; interlock isum and ier
         44A40404 [0054F4]  6488I 	bis	p5, p4, p4			; interlock isum and ier
                  [0054F8]  6490  
         77E40A10 [0054F8]  6491  	hw_mtpr	p4, EV6__IER			; (4,0L) write new ier
                  [0054FC]  6492  
                  [0054FC]  6493  .if eq	check_interrupt_pending
                  [0054FC]  6494  	hw_ret_stall (p23)			; rei to non-kern
                  [0054FC]  6495  .iff
                  [0054FC]  6496  	lda	p4, IRQ_DEV__M(r31)		; mask of IRQ(s) (IRQ1)
                  [0054FC]  6497  	sll	p4, #EV6__ISUM__EI__S, p4	; shift into position
                  [0054FC]  6498  	and	p6, p4, p4			; check for IRQ
                  [0054FC]  6499  
                  [0054FC]  6500  	bne	p4, sys__deassert_interrupt	; go off to deassert
                  [0054FC]  6501  	hw_ret_stall (p23)			; otherwise finish the rei
                  [0054FC]  6502  .endc
         209F0002 [0054FC]  6496I 	lda	p4, IRQ_DEV__M(r31)		; mask of IRQ(s) (IRQ1)
         48843724 [005500]  6497I 	sll	p4, #EV6__ISUM__EI__S, p4	; shift into position
         44C40004 [005504]  6498I 	and	p6, p4, p4			; check for IRQ
                  [005508]  6499I 
         F480013D [005508]  6500I 	bne	p4, sys__deassert_interrupt	; go off to deassert
         7BF7A000 [00550C]  6501I 	hw_ret_stall (p23)			; otherwise finish the rei
                  [005510]  6503  
                  [005510]  6504  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [005510]   176M         GOTO_FREE_CODE
00000000 00000000 [005510]    67M     .align 6
00000000 00000000 [005518]
00000000 00000000 [005520]
00000000 00000000 [005528]
00000000 00000000 [005530]
00000000 00000000 [005538]
File: ev6_osf_pal.mar
                  [005540]  6505  
                  [005540]  6506  ;+
                  [005540]  6507  ; CALL_PAL__BPT
                  [005540]  6508  ;
                  [005540]  6509  ; Entry:
                  [005540]  6510  ;	p23		pc of instruction following the call_pal instruction
                  [005540]  6511  ;
                  [005540]  6512  ; Function:
                  [005540]  6513  ;	The breakpoint trap instruction switches mode to kernel, builds a
                  [005540]  6514  ;	stack frame on the kernel stack, loads the GP with the KGP, loads
                  [005540]  6515  ;	a value of 0 into a0, and dispatches to the breakpoint code pointed
                  [005540]  6516  ;	to by the entIF register. The saved PC at (SP+08) is the address
                  [005540]  6517  ;	of the instruction following the trap instruction that caused the
                  [005540]  6518  ;	trap.
                  [005540]  6519  ;-
                  [005540]  6520  	START_CALL_PAL <BPT>
File: ev6_pal_macros.mar
                  [005540]   104i         ASSUME <<OSFPAL_FUNC__BPT> & <^x40>> eq 0
                  [005540]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [003000]   120i CALL_PAL__BPT::
File: ev6_osf_pal.mar
                  [003000]  6521  
         47E01404 [003000]  6522  	bis	r31, #OSF_A0__BPT, p4			; new a0
         7C951068 [003004]  6523  	hw_stq/p p4, PT__NEW_A0(p_temp)			; save it away
         C3E0094D [003008]  6524  	br	r31, call_pal__bpt_post_if		; merge to complete
                  [00300C]  6525  
                  [00300C]  6526  	CONT_CALL_PAL
File: ev6_pal_macros.mar
                  [00300C]   181M     ASSUME <_pal_func_cont> eq 0
                  [00300C]   189M     ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [00300C]   191M     GOTO_FREE_CODE
                  [005540]    67M     .align 6
File: ev6_osf_pal.mar
                  [005540]  6527  ;
                  [005540]  6528  ; Merge bpt, bugchk, and gentrap to finish up.
                  [005540]  6529  ;
                  [005540]  6530  call_pal__bpt_post_if:
                  [005540]  6531  
         46C11004 [005540]  6532  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p4	; current mode
         46C1F014 [005544]  6533  	and	p_misc, #OSF_P_MISC__PS__M, p20		; save original ps
         E4800008 [005548]  6534  	beq	p4, trap__bpt_stack			; skip switch if kernel
                  [00554C]  6535  ;
                  [00554C]  6536  ; Switch to kernel mode. 
                  [00554C]  6537  ;
                  [00554C]  6538  bpt_cm_offset = <trap__bpt_stack - trap__bpt_cm>
                  [00554C]  6539  
         7FD51020 [00554C]  6540  	hw_stq/p r30, PT__USP(p_temp)			; save user SP
         6FD51018 [005550]  6541  	hw_ldq/p r30, PT__KSP(p_temp)			; get kernel SP
         46C1F116 [005554]  6542  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc	; cm=0, ipl=0
                  [005558]  6543  
         C0C00000 [005558]  6544  	br	p6, trap__bpt_cm			; change mode to kernel
                  [00555C]  6545  trap__bpt_cm:
         40C23406 [00555C]  6546  	addq	p6, #<bpt_cm_offset+1>, p6		; jump past in palmode
         77FF0910 [005560]  6547  	hw_mtpr	r31, EV6__PS				; (4,0L) switch to kern
         D3E00000 [005564]  6548  	bsr	r31, .					; push prediction stack
                  [005568]  6549  	PVC_JSR	bpt_cm					; synch up
File: ev6_pal_macros.mar
                  [005568]   531i  pvc_lbl \pcv_index, \pcv_jsr_bpt_cm0, osf
File: ev6_osf_pal.mar
         7BE6A000 [005568]  6550  	hw_ret_stall (p6)				; pop prediction stack
                  [00556C]  6551  	PVC_JSR	bpt_cm, dest=1
File: ev6_pal_macros.mar
                  [00556C]   534i  pvc_lbl \pcv_index, \pcv_jsr_bpt_cm0, osf, \pcv_jsr_bpt_cm0_inst
File: ev6_osf_pal.mar
                  [00556C]  6552  ;
                  [00556C]  6553  ; Take the trap. Be careful of tb miss!
                  [00556C]  6554  ; Current state:
                  [00556C]  6555  ;	p_misc__ps	if we were in kernel, original ps
                  [00556C]  6556  ;			if we were in user, new ps = 0 (cm=0, ipl=0)
                  [00556C]  6557  ;	p20		original ps
                  [00556C]  6558  ;	p23		nextpc
                  [00556C]  6559  ;
                  [00556C]  6560  trap__bpt_stack:
         7EF51060 [00556C]  6561  	hw_stq/p p23, PT__STACK_PC(p_temp)		; store away nextpc
                  [005570]  6562  
         23DEFFD0 [005570]  6563  	lda	r30, <0-OSF_FRM__SIZE>(r30)		; allocate stack space
                  [005574]  6564  
         B69E0000 [005574]  6565  	stq	p20, OSF_FRM__PS(r30)			; save original ps
         B65E0028 [005578]  6566  	stq	r18, OSF_FRM__A2(r30)			; save a2
                  [00557C]  6567  
         6E951060 [00557C]  6568  	hw_ldq/p p20, PT__STACK_PC(p_temp)		; 1.39 get pc back
                  [005580]  6569  
         B7BE0010 [005580]  6570  	stq	r29, OSF_FRM__GP(r30)			; save gp
         B61E0018 [005584]  6571  	stq	r16, OSF_FRM__A0(r30)			; save a0
         B63E0020 [005588]  6572  	stq	r17, OSF_FRM__A1(r30)			; save a1
         B69E0008 [00558C]  6573  	stq	p20, OSF_FRM__PC(r30)			; 1.39 save next pc
                  [005590]  6574  
         6EF51038 [005590]  6575  	hw_ldq/p p23, PT__ENT_IF(p_temp)		; get entry point
         6FB51028 [005594]  6576  	hw_ldq/p r29, PT__KGP(p_temp)			; get kgp
         6E151068 [005598]  6577  	hw_ldq/p r16, PT__NEW_A0(p_temp)		; a0 <- type code
                  [00559C]  6578  
         7BF78000 [00559C]  6579  	hw_ret	(p23)					; to os
                  [0055A0]  6580  
                  [0055A0]  6581  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [0055A0]   176M         GOTO_FREE_CODE
00000000 00000000 [0055A0]    67M     .align 6
00000000 00000000 [0055A8]
00000000 00000000 [0055B0]
00000000 00000000 [0055B8]
File: ev6_osf_pal.mar
                  [0055C0]  6582  
                  [0055C0]  6583  ;+
                  [0055C0]  6584  ; CALL_PAL__BUGCHK
                  [0055C0]  6585  ;
                  [0055C0]  6586  ; Entry:
                  [0055C0]  6587  ;	p23		pc of instruction following the call_pal instruction
                  [0055C0]  6588  ;
                  [0055C0]  6589  ; Function:
                  [0055C0]  6590  ;	The bugchk instruction switches mode to kernel, builds a
                  [0055C0]  6591  ;	stack frame on the kernel stack, loads the GP with the KGP, loads
                  [0055C0]  6592  ;	a value of 1 into a0, and dispatches to the breakpoint code pointed
                  [0055C0]  6593  ;	to by the entIF register. The saved PC at (SP+08) is the address
                  [0055C0]  6594  ;	of the instruction following the trap instruction that caused the
                  [0055C0]  6595  ;	trap.
                  [0055C0]  6596  ;-
                  [0055C0]  6597  	START_CALL_PAL <BUGCHK>
File: ev6_pal_macros.mar
                  [0055C0]   104i         ASSUME <<OSFPAL_FUNC__BUGCHK> & <^x40>> eq 0
                  [0055C0]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [003040]   120i CALL_PAL__BUGCHK::
File: ev6_osf_pal.mar
                  [003040]  6598  
         47E03404 [003040]  6599  	bis	r31, #OSF_A0__BUGCHK, p4		; new a0
         7C951068 [003044]  6600  	hw_stq/p p4, PT__NEW_A0(p_temp)			; save it away
         C3E0093D [003048]  6601  	br	r31, call_pal__bpt_post_if		; merge to complete
                  [00304C]  6602  
                  [00304C]  6603  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [00304C]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [00304C]   176M         GOTO_FREE_CODE
                  [0055C0]    67M     .align 6
File: ev6_osf_pal.mar
                  [0055C0]  6604  
                  [0055C0]  6605  ;+
                  [0055C0]  6606  ; CALL_PAL__CALLSYS
                  [0055C0]  6607  ;
                  [0055C0]  6608  ; Entry:
                  [0055C0]  6609  ;	p23		pc of instruction following the call_pal instruction
                  [0055C0]  6610  ;
                  [0055C0]  6611  ; Function:
                  [0055C0]  6612  ;	The system call instruction is supported only from user mode.
                  [0055C0]  6613  ;	Issuing a callsys from kernel mode causes a machine check exception.
                  [0055C0]  6614  ;	The callsys instruction switches mode to kernel and builds a
                  [0055C0]  6615  ;	callsys stack frame. The GP is loaded with the KGP. The exception
                  [0055C0]  6616  ;	then dispatches to the system call code pointed to by the
                  [0055C0]  6617  ;	entSys register.
                  [0055C0]  6618  ;-
                  [0055C0]  6619  	START_CALL_PAL <CALLSYS>
File: ev6_pal_macros.mar
                  [0055C0]   104i         ASSUME <<OSFPAL_FUNC__CALLSYS> & <^x40>> eq 0
                  [0055C0]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [0030C0]   120i CALL_PAL__CALLSYS::
File: ev6_osf_pal.mar
                  [0030C0]  6620  
         46C11004 [0030C0]  6621  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p4	; current mode
         46C1F014 [0030C4]  6622  	and	p_misc, #OSF_P_MISC__PS__M, p20		; save original ps
         E49FF515 [0030C8]  6623  	beq	p4, trap__pal_os_bugcheck		; mchk if kernel mode
                  [0030CC]  6624  ;
                  [0030CC]  6625  ; Switch to kernel mode. 
                  [0030CC]  6626  ;
                  [0030CC]  6627  callsys_cm_offset = <trap__callsys_cm_done - trap__callsys_cm>
                  [0030CC]  6628  
         7FD51020 [0030CC]  6629  	hw_stq/p r30, PT__USP(p_temp)			; save user SP
         6FD51018 [0030D0]  6630  	hw_ldq/p r30, PT__KSP(p_temp)			; get kernel SP
         46C1F116 [0030D4]  6631  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc	; cm=0, ipl=0
                  [0030D8]  6632  
         C0C00000 [0030D8]  6633  	br	p6, trap__callsys_cm			; change mode to kernel
                  [0030DC]  6634  trap__callsys_cm:
         40C23406 [0030DC]  6635  	addq	p6, #<callsys_cm_offset+1>, p6		; jump past in palmode
         77FF0910 [0030E0]  6636  	hw_mtpr	r31, EV6__PS				; (4,0L) switch to kern
         D3E00000 [0030E4]  6637  	bsr	r31, .					; push prediciton stack
                  [0030E8]  6638  	PVC_JSR	callsys_cm				; synch up
File: ev6_pal_macros.mar
                  [0030E8]   531i  pvc_lbl \pcv_index, \pcv_jsr_callsys_cm0, osf
File: ev6_osf_pal.mar
         7BE6A000 [0030E8]  6639  	hw_ret_stall (p6)				; pop prediction stack
                  [0030EC]  6640  	PVC_JSR	callsys_cm, dest=1
File: ev6_pal_macros.mar
                  [0030EC]   534i  pvc_lbl \pcv_index, \pcv_jsr_callsys_cm0, osf, \pcv_jsr_callsys_cm0_inst
File: ev6_osf_pal.mar
                  [0030EC]  6641  trap__callsys_cm_done:
                  [0030EC]  6642  
                  [0030EC]  6643  	CONT_CALL_PAL <CALLSYS>
File: ev6_pal_macros.mar
                  [0030EC]   181M     ASSUME <_pal_func_cont> eq 0
         C3E00934 [0030EC]   186i 	br	r31, CALL_PAL__CALLSYS_CONT
                  [0030F0]   189M                 ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [0030F0]   191M     GOTO_FREE_CODE
                  [0055C0]    67M     .align 6
                  [0055C0]   196i CALL_PAL__CALLSYS_CONT:
File: ev6_osf_pal.mar
                  [0055C0]  6644  ;
                  [0055C0]  6645  ; Take the trap. Be careful of tb miss!
                  [0055C0]  6646  ; Current state:
                  [0055C0]  6647  ;	p_misc__ps	new ps = 0 (cm=0, ipl=0)
                  [0055C0]  6648  ;	p20		original ps (cm=1, ipl=0)
                  [0055C0]  6649  ;	p23		nextpc
                  [0055C0]  6650  ;
         7EF51060 [0055C0]  6651  	hw_stq/p p23, PT__STACK_PC(p_temp)		; store away nextpc
                  [0055C4]  6652  
         23DEFFD0 [0055C4]  6653  	lda	r30, <0-OSF_FRM__SIZE>(r30)		; allocate stack space
                  [0055C8]  6654  
         B69E0000 [0055C8]  6655  	stq	p20, OSF_FRM__PS(r30)			; save original ps
         B7BE0010 [0055CC]  6656  	stq	r29, OSF_FRM__GP(r30)			; save gp
                  [0055D0]  6657  
         6E951060 [0055D0]  6658  	hw_ldq/p p20, PT__STACK_PC(p_temp)		; 1.39 get nextpc back
                  [0055D4]  6659  
         B69E0008 [0055D4]  6660  	stq	p20, OSF_FRM__PC(r30)			; 1.39 save nextpc
                  [0055D8]  6661  
         6EF51050 [0055D8]  6662  	hw_ldq/p p23, PT__ENT_SYS(p_temp)		; get entry point
         6FB51028 [0055DC]  6663  	hw_ldq/p r29, PT__KGP(p_temp)			; get kgp
                  [0055E0]  6664  
         7BF78000 [0055E0]  6665  	hw_ret	(p23)					; to os
                  [0055E4]  6666  
                  [0055E4]  6667  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [0055E4]   176M         GOTO_FREE_CODE
00000000 00000000 [0055E4]    67M     .align 6
00000000 00000000 [0055EC]
00000000 00000000 [0055F4]
         00000000 [0055FC]
File: ev6_osf_pal.mar
                  [005600]  6668  
                  [005600]  6669  ;+
                  [005600]  6670  ; CALL_PAL__IMB
                  [005600]  6671  ;
                  [005600]  6672  ; Entry:
                  [005600]  6673  ;	p23		pc of instruction following the call_pal instruction
                  [005600]  6674  ;
                  [005600]  6675  ; Function:
                  [005600]  6676  ;	Make instruction stream coherent with data stream. Does not
                  [005600]  6677  ;	guarantee other processors see a modification of the instruction
                  [005600]  6678  ;	stream.
                  [005600]  6679  ;-
                  [005600]  6680  	START_CALL_PAL <IMB>
File: ev6_pal_macros.mar
                  [005600]   104i         ASSUME <<OSFPAL_FUNC__IMB> & <^x40>> eq 0
                  [005600]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [003180]   120i CALL_PAL__IMB::
File: ev6_osf_pal.mar
                  [003180]  6681  
         63FF4000 [003180]  6682  	MB					; force memory operations
                  [003184]  6683  	NOP
File: ev6_pal_macros.mar
         47FF041F [003184]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [003188]  6684  	NOP
File: ev6_pal_macros.mar
         47FF041F [003188]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [00318C]  6685  	NOP
File: ev6_pal_macros.mar
         47FF041F [00318C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [003190]  6686  
         77FF1310 [003190]  6687  	hw_mtpr	r31, EV6__IC_FLUSH		; (4,0L) flush the icache
         F7E00000 [003194]  6688  	bne	r31, .				; pvc #24
         7BF7A000 [003198]  6689  	hw_ret_stall (p23)			; return with stall
                  [00319C]  6690  
                  [00319C]  6691  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [00319C]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [00319C]   176M         GOTO_FREE_CODE
                  [005600]    67M     .align 6
File: ev6_osf_pal.mar
                  [005600]  6692  
                  [005600]  6693  
                  [005600]  6694  ASSUME <clrmap+force_ecc> ne 2
                  [005600]  6695  .if ne force_ecc
                  [005600]  6696  ;+
                  [005600]  6697  ; CALL_PAL__ECC_ERROR
                  [005600]  6698  ;
                  [005600]  6699  ; Entry:
                  [005600]  6700  ;	r16		address
                  [005600]  6701  ;	r17		data
                  [005600]  6702  ;       p23             pc of instruction following the call_pal instruction
                  [005600]  6703  ;
                  [005600]  6704  ; Function:
                  [005600]  6705  ;	Force ecc error.
                  [005600]  6706  ;
                  [005600]  6707  ; Current state:
                  [005600]  6708  ;	p21	p_temp
                  [005600]  6709  ;	p22	p_misc
                  [005600]  6710  ;	p23	linkage register
                  [005600]  6711  ;
                  [005600]  6712  ; Exit state:
                  [005600]  6713  ;       r0	clobbered
                  [005600]  6714  ;
                  [005600]  6715  ; Note: This is a debugging call_pal. It is not particularly robust.
                  [005600]  6716  ; In particular, it does not expect any exceptions on the virtual accesses.
                  [005600]  6717  ;-
                  [005600]  6718  
                  [005600]  6719  OSFPAL_FUNC__ECCTEST        = ^x87
                  [005600]  6720  
                  [005600]  6721          START_CALL_PAL <ECCTEST>
                  [005600]  6722  
                  [005600]  6723          mb					; force completion
                  [005600]  6724          hw_ldq/p p20, PT__IMPURE(p_temp)	; impure base
                  [005600]  6725          hw_ldq/p r0, CNS__DC_CTL(p20)		; get old DC_CTL value
                  [005600]  6726          ldq     p20, (r16)			; (xL,4) read the data
                  [005600]  6727  
                  [005600]  6728          mb					; force completion
                  [005600]  6729          xor     p20, r17, p20
                  [005600]  6730          bis     r0, #^x20, r0
                  [005600]  6731          hw_mtpr r0, EV6__DC_CTL			; (6,0L) write DC_CTL
                  [005600]  6732  
                  [005600]  6733          bis     r31, r31, r31			
                  [005600]  6734          bis     r31, r31, r31
                  [005600]  6735          mb					; force completion
                  [005600]  6736          hw_mtpr r0, EV6__DC_CTL			; (6,0L) force retire
                  [005600]  6737  
                  [005600]  6738  	CONT_CALL_PAL <ECCTEST>
                  [005600]  6739  
                  [005600]  6740          ASSUME_FETCH_BLOCK
                  [005600]  6741  
                  [005600]  6742          stq     p20, (r16)			; (xL,4) write the data
                  [005600]  6743          mb					; force completion
                  [005600]  6744          bic     r0, #^x20, r0
                  [005600]  6745          hw_mtpr r0, EV6__DC_CTL			; (6,0L) restore DC_CTL
                  [005600]  6746  
                  [005600]  6747          bis     r31, r31, r31
                  [005600]  6748          bis     r31, r31, r31
                  [005600]  6749          mb					; force completion
                  [005600]  6750          hw_mtpr r0, EV6__DC_CTL			; (6,0L) force retire
                  [005600]  6751  
                  [005600]  6752          bis     r31, r31, r31
                  [005600]  6753          hw_ret  (p23)				; return
                  [005600]  6754  
                  [005600]  6755          END_CALL_PAL
                  [005600]  6756  .endc
                  [005600]  6696I ;+
                  [005600]  6697I ; CALL_PAL__ECC_ERROR
                  [005600]  6698I ;
                  [005600]  6699I ; Entry:
                  [005600]  6700I ;	r16		address
                  [005600]  6701I ;	r17		data
                  [005600]  6702I ;       p23             pc of instruction following the call_pal instruction
                  [005600]  6703I ;
                  [005600]  6704I ; Function:
                  [005600]  6705I ;	Force ecc error.
                  [005600]  6706I ;
                  [005600]  6707I ; Current state:
                  [005600]  6708I ;	p21	p_temp
                  [005600]  6709I ;	p22	p_misc
                  [005600]  6710I ;	p23	linkage register
                  [005600]  6711I ;
                  [005600]  6712I ; Exit state:
                  [005600]  6713I ;       r0	clobbered
                  [005600]  6714I ;
                  [005600]  6715I ; Note: This is a debugging call_pal. It is not particularly robust.
                  [005600]  6716I ; In particular, it does not expect any exceptions on the virtual accesses.
                  [005600]  6717I ;-
                  [005600]  6718I 
                  [005600]  6719I OSFPAL_FUNC__ECCTEST        = ^x87
                  [005600]  6720I 
                  [005600]  6721I         START_CALL_PAL <ECCTEST>
File: ev6_pal_macros.mar
                  [005600]   104i         ASSUME <<OSFPAL_FUNC__ECCTEST> & <^x40>> eq 0
                  [005600]   111i     ASSUME <_pal_func_in_prog> eq 0
                  [0031C0]   120i CALL_PAL__ECCTEST::
File: ev6_osf_pal.mar
                  [0031C0]  6722I 
         63FF4000 [0031C0]  6723I         mb					; force completion
         6E951088 [0031C4]  6724I         hw_ldq/p p20, PT__IMPURE(p_temp)	; impure base
         6C141398 [0031C8]  6725I         hw_ldq/p r0, CNS__DC_CTL(p20)		; get old DC_CTL value
         A6900000 [0031CC]  6726I         ldq     p20, (r16)			; (xL,4) read the data
                  [0031D0]  6727I 
         63FF4000 [0031D0]  6728I         mb					; force completion
         46910814 [0031D4]  6729I         xor     p20, r17, p20
         44041400 [0031D8]  6730I         bis     r0, #^x20, r0
         77E02940 [0031DC]  6731I         hw_mtpr r0, EV6__DC_CTL			; (6,0L) write DC_CTL
                  [0031E0]  6732I 
         47FF041F [0031E0]  6733I         bis     r31, r31, r31			
         47FF041F [0031E4]  6734I         bis     r31, r31, r31
         63FF4000 [0031E8]  6735I         mb					; force completion
         77E02940 [0031EC]  6736I         hw_mtpr r0, EV6__DC_CTL			; (6,0L) force retire
                  [0031F0]  6737I 
                  [0031F0]  6738I 	CONT_CALL_PAL <ECCTEST>
File: ev6_pal_macros.mar
                  [0031F0]   181i     ASSUME <_pal_func_cont> eq 0
         C3E00903 [0031F0]   186i 	br	r31, CALL_PAL__ECCTEST_CONT
                  [0031F4]   189i                 ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [0031F4]   191i     GOTO_FREE_CODE
                  [005600]    67i     .align 6
                  [005600]   196i CALL_PAL__ECCTEST_CONT:
File: ev6_osf_pal.mar
                  [005600]  6739I 
                  [005600]  6740I         ASSUME_FETCH_BLOCK
                  [005600]  6741I 
         B6900000 [005600]  6742I         stq     p20, (r16)			; (xL,4) write the data
         63FF4000 [005604]  6743I         mb					; force completion
         44041100 [005608]  6744I         bic     r0, #^x20, r0
         77E02940 [00560C]  6745I         hw_mtpr r0, EV6__DC_CTL			; (6,0L) restore DC_CTL
                  [005610]  6746I 
         47FF041F [005610]  6747I         bis     r31, r31, r31
         47FF041F [005614]  6748I         bis     r31, r31, r31
         63FF4000 [005618]  6749I         mb					; force completion
         77E02940 [00561C]  6750I         hw_mtpr r0, EV6__DC_CTL			; (6,0L) force retire
                  [005620]  6751I 
         47FF041F [005620]  6752I         bis     r31, r31, r31
         7BF78000 [005624]  6753I         hw_ret  (p23)				; return
                  [005628]  6754I 
                  [005628]  6755I         END_CALL_PAL
File: ev6_pal_macros.mar
                  [005628]   176i         GOTO_FREE_CODE
00000000 00000000 [005628]    67i     .align 6
00000000 00000000 [005630]
00000000 00000000 [005638]
File: ev6_osf_pal.mar
                  [005640]  6757  
                  [005640]  6758  
                  [005640]  6759  .if ne clrmap
                  [005640]  6760  ;+
                  [005640]  6761  ; CALL_PAL__CLRMAP
                  [005640]  6762  ;
                  [005640]  6763  ; Entry:
                  [005640]  6764  ;       p23             pc of instruction following the call_pal instruction
                  [005640]  6765  ;
                  [005640]  6766  ; Function:
                  [005640]  6767  ;	Clear the register map
                  [005640]  6768  ;
                  [005640]  6769  ; Current state:
                  [005640]  6770  ;	p21	p_temp
                  [005640]  6771  ;	p22	p_misc
                  [005640]  6772  ;	p23	linkage register
                  [005640]  6773  ;
                  [005640]  6774  ; Exit state:
                  [005640]  6775  ;       restored
                  [005640]  6776  ;-
                  [005640]  6777  
                  [005640]  6778  OSFPAL_FUNC__CLRMAP        = ^x87
                  [005640]  6779  
                  [005640]  6780          START_CALL_PAL <CLRMAP>
                  [005640]  6781  
                  [005640]  6782    .if eq ev6_p1
                  [005640]  6783  	hw_ret	(p23)				; just return if not p1
                  [005640]  6784    .iff
                  [005640]  6785  
                  [005640]  6786          hw_mfpr p7, EV6__PAL_BASE		; (4,0L) pal base
                  [005640]  6787  	hw_ldq/p p6, PT__WHAMI(p_temp)		; get my cpu number
                  [005640]  6788  	s8addq	p6, p7, p7			; (cpu*8)+base
                  [005640]  6789  	hw_stq/p p_temp, ^x30(p7)		; p_temp at ^x30+(cpu*8)+base
                  [005640]  6790  
                  [005640]  6791          hw_ldq/p p4, PT__IMPURE(p_temp)		; get base of impure area
                  [005640]  6792          hw_stq/p p_misc, CNS__P_MISC(p4)	; store p_misc
                  [005640]  6793          hw_stq/p p23, CNS__P23(p4)		; store call_pal linkage
                  [005640]  6794  	hw_mfpr	p5, EV6__SIRR			; (4,0L) get sirr
                  [005640]  6795  
                  [005640]  6796  	hw_stq/p p5, CNS__SIRR(p4)		; store sirr
                  [005640]  6797  	sll	p6, #EV6__SIRR__SIR__S, p6	; cpu number into place
                  [005640]  6798  	hw_mtpr	p6, EV6__SIRR			; (4,0L) save cpu number
                  [005640]  6799  	bis	r31, r31, r31			; pad fetch block
                  [005640]  6800  
                  [005640]  6801          hw_mfpr  p5, EV6__I_CTL                 ; (4,0L) get i_ctl
                  [005640]  6802  
                  [005640]  6803  	CONT_CALL_PAL <CLRMASK>
                  [005640]  6804  
                  [005640]  6805          ASSUME_FETCH_BLOCK
                  [005640]  6806  
                  [005640]  6807  	GET_32CONS p20, <^x804000>, r31		; hack for ev6isp
                  [005640]  6808  	bic	p5, p20, p5			; clear unpredictables
                  [005640]  6809          hw_stq/p p5, CNS__I_CTL(p4)		; store i_ctl
                  [005640]  6810  
                  [005640]  6811          hw_stq/p r0, CNS__R0(p4)           	; save r0
                  [005640]  6812          hw_stq/p r1, CNS__R1(p4)           	; save r1
                  [005640]  6813          hw_stq/p r2, CNS__R2(p4)           	; save r2
                  [005640]  6814          hw_mfpr r2, EV6__I_CTL                  ; (4,0L) get i_ctl
                  [005640]  6815  
                  [005640]  6816          bis     p4, r31, r1                     ; impure base into r1
                  [005640]  6817          bic     r2, #<2@EV6__I_CTL__SDE__S>, r2 ; zap sde
                  [005640]  6818          hw_stq/p r3, CNS__R3(p4)           	; save r3
                  [005640]  6819          hw_stq/p r8, CNS__R8(r1)           	; save gpr
                  [005640]  6820  
                  [005640]  6821          hw_mtpr r2, EV6__I_CTL                  ; (4,0L) write i_ctl
                  [005640]  6822          hw_stq/p r9, CNS__R9(r1)           	; save gpr
                  [005640]  6823          hw_stq/p r10, CNS__R10(r1)         	; save gpr
                  [005640]  6824          hw_stq/p r11, CNS__R11(r1)         	; save gpr
                  [005640]  6825  
                  [005640]  6826          hw_mtpr r2, EV6__I_CTL                  ; (4,0L) stall outside IQ
                  [005640]  6827          hw_stq/p r12, CNS__R12(r1)         	; save gpr
                  [005640]  6828          hw_stq/p r13, CNS__R13(r1)         	; save gpr
                  [005640]  6829          hw_stq/p r14, CNS__R14(r1)         	; save gpr
                  [005640]  6830  
                  [005640]  6831          hw_stq/p r15, CNS__R15(r1)         	; buffer block 1 -- save gpr
                  [005640]  6832          hw_stq/p r16, CNS__R16(r1)         	; save gpr
                  [005640]  6833          hw_stq/p r17, CNS__R17(r1)         	; save gpr
                  [005640]  6834          hw_stq/p r18, CNS__R18(r1)         	; save gpr
                  [005640]  6835  
                  [005640]  6836          hw_stq/p r19, CNS__R19(r1)         	; buffer block 2 -- save gpr
                  [005640]  6837          hw_stq/p r24, CNS__R24(r1)         	; save gpr
                  [005640]  6838          hw_stq/p r25, CNS__R25(r1)         	; save gpr
                  [005640]  6839          hw_stq/p r26, CNS__R26(r1)         	; save gpr
                  [005640]  6840  
                  [005640]  6841          hw_stq/p r27, CNS__R27(r1)         	; buffer block 3 -- save gpr
                  [005640]  6842          hw_stq/p r28, CNS__R28(r1)         	; save gpr
                  [005640]  6843          hw_stq/p r29, CNS__R29(r1)         	; save gpr
                  [005640]  6844          hw_stq/p r30, CNS__R30(r1)         	; save gpr
                  [005640]  6845  
                  [005640]  6846          hw_stq/p r4, CNS__R4(r1)           	; save gpr
                  [005640]  6847          hw_stq/p r5, CNS__R5(r1)           	; save gpr
                  [005640]  6848          hw_stq/p r6, CNS__R6(r1)           	; save gpr
                  [005640]  6849          hw_stq/p r7, CNS__R7(r1)           	; save gpr
                  [005640]  6850  
                  [005640]  6851          hw_stq/p r20, CNS__R20(r1)         	; save gpr
                  [005640]  6852          hw_stq/p r21, CNS__R21(r1)         	; save gpr
                  [005640]  6853          hw_stq/p r22, CNS__R22(r1)         	; save gpr
                  [005640]  6854          hw_stq/p r23, CNS__R23(r1)         	; save gpr
                  [005640]  6855  
                  [005640]  6856          hw_stq/p r31, CNS__R31(r1)         	; save gpr
                  [005640]  6857  	bis	r31, r31, r31
                  [005640]  6858  	bis	r31, r31, r31
                  [005640]  6859  	mb					; dll -- add mb
                  [005640]  6860  
                  [005640]  6861          hw_mfpr r0, EV6__I_CTL			; (4,0L) get i_ctl
                  [005640]  6862          or	r31, #EV6__I_CTL__SBE__M, r3	; form SBE mask
                  [005640]  6863          sll 	r3, #EV6__I_CTL__SBE__S, r3
                  [005640]  6864          bic	r0, r3, r0			; zap SBE bits
                  [005640]  6865  
                  [005640]  6866  clr_map_1_offset = <clr_map_1_done - clr_map_1>
                  [005640]  6867  
                  [005640]  6868          hw_mtpr r0, EV6__I_CTL			; (4,0L) turn off stream buffers
                  [005640]  6869  	br	r2, clr_map_1
                  [005640]  6870  clr_map_1:
                  [005640]  6871  	addq	r2, #<clr_map_1_offset+1>, r2	; jump past in palmode
                  [005640]  6872  	bsr	r31, .				; push prediction stack
                  [005640]  6873  
                  [005640]  6874          hw_mtpr r31, EV6__IC_FLUSH		; flush icache
                  [005640]  6875  	bne	r31, .
                  [005640]  6876  	PVC_JSR	clr_map_1			; synch up
                  [005640]  6877  	hw_ret_stall (r2)			; pop prediction stack
                  [005640]  6878  	PVC_JSR	clr_map_1, dest=1
                  [005640]  6879  
                  [005640]  6880          .ALIGN 6 ,<^X47FF041F>
                  [005640]  6881  clr_map_1_done:
                  [005640]  6882          hw_mtpr r0, EV6__CLR_MAP      		; (4-7,0L) clear map
                  [005640]  6883  	NOP
                  [005640]  6884  	NOP
                  [005640]  6885  	NOP
                  [005640]  6886  
                  [005640]  6887  	NOP					; dll - add quiet stuff
                  [005640]  6888  	NOP
                  [005640]  6889  	NOP
                  [005640]  6890  	NOP
                  [005640]  6891  
                  [005640]  6892  clr_map_2_offset = <real_code_1 - clr_map_2>
                  [005640]  6893  
                  [005640]  6894  	NOP
                  [005640]  6895  	NOP
                  [005640]  6896  	bsr	r31, .				; push prediction stack
                  [005640]  6897  	lda	r3, <clr_map_2_offset>(r31)
                  [005640]  6898  
                  [005640]  6899  	br	r2, clr_map_2
                  [005640]  6900  clr_map_2:
                  [005640]  6901  	addq	r2, r3, r2
                  [005640]  6902  	addq	r2, #<1>, r2			; jump past in palmode
                  [005640]  6903  	PVC_JSR	clr_map_2			; synch up
                  [005640]  6904  	hw_ret_stall (r2)			; pop prediction stack
                  [005640]  6905  	PVC_JSR	clr_map_2, dest=1
                  [005640]  6906  
                  [005640]  6907  	NOP					; dll - add more quiet stuff
                  [005640]  6908  	NOP
                  [005640]  6909  	NOP
                  [005640]  6910  	NOP
                  [005640]  6911  
                  [005640]  6912  	.ALIGN 6,<^X47FF041F>
                  [005640]  6913  	NOP
                  [005640]  6914  	NOP
                  [005640]  6915  	NOP
                  [005640]  6916  	NOP
                  [005640]  6917  
                  [005640]  6918  	.ALIGN 6,<^X47FF041F>
                  [005640]  6919  	NOP
                  [005640]  6920  	NOP
                  [005640]  6921  	NOP
                  [005640]  6922  	NOP
                  [005640]  6923  
                  [005640]  6924  	.ALIGN 6,<^X47FF041F>
                  [005640]  6925  	NOP
                  [005640]  6926  	NOP
                  [005640]  6927  	NOP
                  [005640]  6928  	NOP
                  [005640]  6929  
                  [005640]  6930  	.ALIGN 6,<^X47FF041F>
                  [005640]  6931  	NOP
                  [005640]  6932  	NOP
                  [005640]  6933  	NOP
                  [005640]  6934  	NOP
                  [005640]  6935  
                  [005640]  6936  	.ALIGN 6,<^X47FF041F>
                  [005640]  6937  	NOP
                  [005640]  6938  	NOP
                  [005640]  6939  	NOP
                  [005640]  6940  	NOP
                  [005640]  6941  ;
                  [005640]  6942  ; Now do the mapper again
                  [005640]  6943  ;
                  [005640]  6944          .ALIGN 6 ,<^X47FF041F>
                  [005640]  6945  real_code_1:
                  [005640]  6946          addq    r31,r31,r0
                  [005640]  6947          addq    r31,r31,r1
                  [005640]  6948          addq    r31,r31,r2
                  [005640]  6949          addq    r31,r31,r3
                  [005640]  6950  
                  [005640]  6951          addq    r31,r31,r4
                  [005640]  6952          addq    r31,r31,r5
                  [005640]  6953          addq    r31,r31,r6
                  [005640]  6954          addq    r31,r31,r7
                  [005640]  6955  
                  [005640]  6956          addq    r31,r31,r8
                  [005640]  6957          addq    r31,r31,r9
                  [005640]  6958          addq    r31,r31,r10
                  [005640]  6959          addq    r31,r31,r11
                  [005640]  6960  
                  [005640]  6961          addq    r31,r31,r12
                  [005640]  6962          addq    r31,r31,r13
                  [005640]  6963          addq    r31,r31,r14
                  [005640]  6964          addq    r31,r31,r15
                  [005640]  6965  
                  [005640]  6966          addq    r31,r31,r16
                  [005640]  6967          addq    r31,r31,r17
                  [005640]  6968          addq    r31,r31,r18
                  [005640]  6969          addq    r31,r31,r19
                  [005640]  6970  
                  [005640]  6971          addq    r31,r31,r20
                  [005640]  6972          addq    r31,r31,r21
                  [005640]  6973          addq    r31,r31,r22
                  [005640]  6974          addq    r31,r31,r23
                  [005640]  6975  
                  [005640]  6976          addq    r31,r31,r24
                  [005640]  6977          addq    r31,r31,r25
                  [005640]  6978          addq    r31,r31,r26
                  [005640]  6979          addq    r31,r31,r27
                  [005640]  6980  
                  [005640]  6981          addq    r31,r31,r28
                  [005640]  6982          addq    r31,r31,r29
                  [005640]  6983          addq    r31,r31,r30
                  [005640]  6984          addq    r31,r31,r0			; done 32
                  [005640]  6985  
                  [005640]  6986          addq    r31,r31,r0
                  [005640]  6987          addq    r31,r31,r1
                  [005640]  6988          addq    r31,r31,r2
                  [005640]  6989          addq    r31,r31,r3
                  [005640]  6990  
                  [005640]  6991          addq    r31,r31,r4
                  [005640]  6992          addq    r31,r31,r5
                  [005640]  6993          addq    r31,r31,r6
                  [005640]  6994          addq    r31,r31,r7
                  [005640]  6995  
                  [005640]  6996          addq    r31,r31,r8
                  [005640]  6997          addq    r31,r31,r9
                  [005640]  6998          addq    r31,r31,r10
                  [005640]  6999          addq    r31,r31,r11
                  [005640]  7000  
                  [005640]  7001          addq    r31,r31,r12
                  [005640]  7002          addq    r31,r31,r13
                  [005640]  7003          addq    r31,r31,r14
                  [005640]  7004          addq    r31,r31,r15
                  [005640]  7005  
                  [005640]  7006          addq    r31,r31,r16
                  [005640]  7007          addq    r31,r31,r17
                  [005640]  7008          addq    r31,r31,r18
                  [005640]  7009          addq    r31,r31,r19
                  [005640]  7010  
                  [005640]  7011          addq    r31,r31,r20
                  [005640]  7012          addq    r31,r31,r21
                  [005640]  7013          addq    r31,r31,r22
                  [005640]  7014          addq    r31,r31,r23
                  [005640]  7015  
                  [005640]  7016          addq    r31,r31,r24
                  [005640]  7017          addq    r31,r31,r25
                  [005640]  7018          addq    r31,r31,r26
                  [005640]  7019          addq    r31,r31,r27
                  [005640]  7020  
                  [005640]  7021          addq    r31,r31,r28
                  [005640]  7022          addq    r31,r31,r29
                  [005640]  7023          addq    r31,r31,r30
                  [005640]  7024  	addq	r31,r31,r0			; done 64
                  [005640]  7025  
                  [005640]  7026          addq    r31,r31,r0
                  [005640]  7027          addq    r31,r31,r1
                  [005640]  7028          addq    r31,r31,r2
                  [005640]  7029          addq    r31,r31,r3
                  [005640]  7030  
                  [005640]  7031          addq    r31,r31,r4
                  [005640]  7032          addq    r31,r31,r5
                  [005640]  7033          addq    r31,r31,r6
                  [005640]  7034          addq    r31,r31,r7
                  [005640]  7035  
                  [005640]  7036          addq    r31,r31,r8
                  [005640]  7037          addq    r31,r31,r9
                  [005640]  7038          addq    r31,r31,r10
                  [005640]  7039          addq    r31,r31,r11
                  [005640]  7040  
                  [005640]  7041          addq    r31,r31,r12
                  [005640]  7042          addq    r31,r31,r13
                  [005640]  7043          addq    r31,r31,r14
                  [005640]  7044          addq    r31,r31,r15			; done 80
                  [005640]  7045  ;
                  [005640]  7046  ; Now turn on mapper source enables
                  [005640]  7047  ;
                  [005640]  7048          hw_mtpr r31,EV6__ITB_IA         ; (4,0L) flush ITB, enable source map
                  [005640]  7049          hw_mtpr r31,EV6__DTB_IA         ; (7,1L) flush DTB
                  [005640]  7050          addq    r31,r31,r0              ; nop
                  [005640]  7051          addq    r31,r31,r0              ; nop
                  [005640]  7052  ;
                  [005640]  7053  ; Create a stall outside the IQ until the mtpr EV6__ITB_IA retires.
                  [005640]  7054  ;
                  [005640]  7055  	PVC_VIOLATE <21>
                  [005640]  7056          hw_mtpr r31,<EV6__MM_STAT ! ^x90>    ; (4&7,0L) IQ stall.
                  [005640]  7057          addq    r31,r31,r0              ; nop
                  [005640]  7058          addq    r31,r31,r0              ; nop
                  [005640]  7059          addq    r31,r31,r0              ; nop
                  [005640]  7060  
                  [005640]  7061          addq    r31,r31,r0              ; 1st buffer fetch block. IMAP stall
                  [005640]  7062          addq    r31,r31,r0              ; nop
                  [005640]  7063          addq    r31,r31,r0              ; nop
                  [005640]  7064          addq    r31,r31,r0              ; nop
                  [005640]  7065  
                  [005640]  7066          addq    r31,r31,r0              ; 2nd buffer fetch block. FMAP stall
                  [005640]  7067          addq    r31,r31,r0              ; nop
                  [005640]  7068          addq    r31,r31,r0              ; nop
                  [005640]  7069          addq    r31,r31,r0              ; nop
                  [005640]  7070  ;
                  [005640]  7071  ; Now map the shadow registers
                  [005640]  7072  ;
                  [005640]  7073          lda     r0,^x0086(r31)          ; load I_CTL.....
                  [005640]  7074  	bis	r0, r0, r0
                  [005640]  7075  	bis	r0, r0, r0
                  [005640]  7076  	bis	r0, r0, r0
                  [005640]  7077  
                  [005640]  7078          hw_mtpr r0,EV6__I_CTL           ; .....SDE=2, IC_EN=3 (SCRBRD=4)
                  [005640]  7079  	bis	r0, r0, r0
                  [005640]  7080  	bis	r0, r0, r0
                  [005640]  7081  	bis	r0, r0, r0
                  [005640]  7082  
                  [005640]  7083          hw_mtpr r0,EV6__I_CTL           ; .....SDE=2, IC_EN=3 (SCRBRD=4)
                  [005640]  7084          addq    r31,r31,r0              ; nop
                  [005640]  7085          addq    r31,r31,r0              ; nop
                  [005640]  7086          addq    r31,r31,r0              ; nop
                  [005640]  7087  
                  [005640]  7088          addq    r31,r31,r0              ; 1st buffer fetch block for above map-stall
                  [005640]  7089          addq    r31,r31,r0              ; nop
                  [005640]  7090          addq    r31,r31,r0              ; nop
                  [005640]  7091          addq    r31,r31,r0              ; nop
                  [005640]  7092  
                  [005640]  7093          addq    r31,r31,r0              ; 2nd buffer fetch block for above map-stall
                  [005640]  7094          addq    r31,r31,r0              ; nop
                  [005640]  7095          addq    r31,r31,r0              ; nop
                  [005640]  7096          addq    r31,r31,r0              ; nop
                  [005640]  7097  
                  [005640]  7098          addq    r31,r31,r0              ; need 3rd buffer fetch block to get sde bit
                  [005640]  7099          addq    r31,r31,r0              ; nop
                  [005640]  7100          addq    r31,r31,r0              ; nop
                  [005640]  7101          addq    r31,r31,r0              ; nop
                  [005640]  7102  ;
                  [005640]  7103  ; map shadow registers
                  [005640]  7104  ;
                  [005640]  7105          addq    r31,r31,r4
                  [005640]  7106          addq    r31,r31,r5
                  [005640]  7107          addq    r31,r31,r6
                  [005640]  7108          addq    r31,r31,r7
                  [005640]  7109  
                  [005640]  7110          addq    r31,r31,r20
                  [005640]  7111          addq    r31,r31,r21
                  [005640]  7112          addq    r31,r31,r22
                  [005640]  7113          addq    r31,r31,r23
                  [005640]  7114  ;
                  [005640]  7115  ; Now restore stuff
                  [005640]  7116  ;	p21 = p_temp
                  [005640]  7117  ;	p22 = p_misc
                  [005640]  7118  ;	p23 = linkage
                  [005640]  7119  ;
                  [005640]  7120  ;	(pal_base+^x30+(8*cpu)) = p_temp
                  [005640]  7121  ;	CNS__P_MISC =  p_misc
                  [005640]  7122  ;	CNS__P23    = linkage
                  [005640]  7123  ;	CNS__I_CTL  = i_ctl
                  [005640]  7124  ;	CNS__SIRR   = sirr value
                  [005640]  7125  ;
                  [005640]  7126  	ASSUME_FETCH_BLOCK
                  [005640]  7127  
                  [005640]  7128  	hw_mfpr	p6, EV6__SIRR			; (4,0L) get cpu number
                  [005640]  7129  	srl	p6, #EV6__SIRR__SIR__S, p6	; shift into place
                  [005640]  7130  	bis	r31, r31, r31
                  [005640]  7131  	bis	r31, r31, r31
                  [005640]  7132  
                  [005640]  7133  	hw_mfpr	r2, EV6__PAL_BASE		; (4,0L) pal base
                  [005640]  7134  	s8addq	p6, r2, r2			; (cpu*8)+base
                  [005640]  7135  	hw_ldq/p p_temp, ^x30(r2)		; restore p_temp
                  [005640]  7136  	hw_ldq/p r1, PT__IMPURE(p_temp)		; get base of impure area
                  [005640]  7137  
                  [005640]  7138          hw_ldq/p p_misc, CNS__P_MISC(r1)	; restore p_misc
                  [005640]  7139          hw_ldq/p p23, CNS__P23(r1)		; restore call_pal linkage
                  [005640]  7140  	hw_ldq/p p5, CNS__SIRR(r1)		; get SIRR back
                  [005640]  7141  	hw_mtpr	p5, EV6__SIRR			; (4,0L) restore it
                  [005640]  7142  
                  [005640]  7143          hw_ldq/p r0, CNS__I_CTL(r1)		; get saved i_ctl
                  [005640]  7144          bic     r0, #<2@EV6__I_CTL__SDE__S>, r2 ; zap sde
                  [005640]  7145          hw_ldq/p r8, CNS__R8(r1)           	; restore gpr
                  [005640]  7146          hw_ldq/p r9, CNS__R9(r1)           	; restore gpr
                  [005640]  7147  
                  [005640]  7148          hw_mtpr r2, EV6__I_CTL                  ; (4,0L) write i_ctl
                  [005640]  7149          hw_ldq/p r10, CNS__R10(r1)         	; restore gpr
                  [005640]  7150          hw_ldq/p r11, CNS__R11(r1)         	; restore gpr
                  [005640]  7151          hw_ldq/p r12, CNS__R12(r1)         	; restore gpr
                  [005640]  7152  
                  [005640]  7153          hw_mtpr r2, EV6__I_CTL                  ; stall outside IQ
                  [005640]  7154          hw_ldq/p r13, CNS__R13(r1)         	; restore gpr
                  [005640]  7155          hw_ldq/p r14, CNS__R14(r1)         	; restore gpr
                  [005640]  7156          hw_ldq/p r15, CNS__R15(r1)         	; restore gpr
                  [005640]  7157  
                  [005640]  7158          hw_ldq/p r16, CNS__R16(r1)         	; buffer block 1 -- restore gpr
                  [005640]  7159          hw_ldq/p r17, CNS__R17(r1)         	; restore gpr
                  [005640]  7160          hw_ldq/p r18, CNS__R18(r1)         	; restore gpr
                  [005640]  7161          hw_ldq/p r19, CNS__R19(r1)         	; restore gpr
                  [005640]  7162  
                  [005640]  7163          hw_ldq/p r24, CNS__R24(r1)         	; buffer block 2 -- restore gpr
                  [005640]  7164          hw_ldq/p r25, CNS__R25(r1)         	; restore gpr
                  [005640]  7165          hw_ldq/p r26, CNS__R26(r1)         	; restore gpr
                  [005640]  7166          hw_ldq/p r27, CNS__R27(r1)         	; restore gpr
                  [005640]  7167  
                  [005640]  7168          hw_ldq/p r28, CNS__R28(r1)         	; buffer block 3 -- restore gpr
                  [005640]  7169          hw_ldq/p r29, CNS__R29(r1)         	; restore gpr
                  [005640]  7170          hw_ldq/p r30, CNS__R30(r1)         	; restore gpr
                  [005640]  7171          bis     r31, r31, r31
                  [005640]  7172  
                  [005640]  7173          hw_ldq/p r4, CNS__R4(r1)           	; restore gpr
                  [005640]  7174          hw_ldq/p r5, CNS__R5(r1)           	; restore gpr
                  [005640]  7175          hw_ldq/p r6, CNS__R6(r1)           	; restore gpr
                  [005640]  7176          hw_ldq/p r7, CNS__R7(r1)           	; restore gpr
                  [005640]  7177  
                  [005640]  7178          hw_ldq/p r20, CNS__R20(r1)         	; restore gpr
                  [005640]  7179          hw_ldq/p r21, CNS__R21(r1)         	; restore gpr
                  [005640]  7180          hw_ldq/p r22, CNS__R22(r1)         	; restore gpr
                  [005640]  7181          hw_ldq/p r23, CNS__R23(r1)         	; restore gpr
                  [005640]  7182  ;
                  [005640]  7183  ; Now turn shadow mode back on.
                  [005640]  7184  ;
                  [005640]  7185          bis     r2, #<2@EV6__I_CTL__SDE__S>, r2 ; enable sde
                  [005640]  7186          hw_mtpr r2, EV6__I_CTL                  ; (4,0L) write i_ctl
                  [005640]  7187          bis     r31, r31, r31
                  [005640]  7188          bis     r31, r31, r31
                  [005640]  7189  
                  [005640]  7190          hw_mtpr r2, EV6__I_CTL                  ; (4,0L) stall outside IQ
                  [005640]  7191          bis     r31, r31, r31
                  [005640]  7192          bis     r31, r31, r31
                  [005640]  7193          bis     r31, r31, r31
                  [005640]  7194  
                  [005640]  7195          bis     r0, r0, r0                      ; buffer block 1
                  [005640]  7196          bis     r31, r31, r31
                  [005640]  7197          bis     r31, r31, r31
                  [005640]  7198          bis     r31, r31, r31
                  [005640]  7199  
                  [005640]  7200          bis     r0, r0, r0                      ; buffer block 2
                  [005640]  7201          bis     r31, r31, r31
                  [005640]  7202          bis     r31, r31, r31
                  [005640]  7203          bis     r31, r31, r31
                  [005640]  7204  
                  [005640]  7205          bis     r0, r0, r0                      ; buffer block 3
                  [005640]  7206          bis     r31, r31, r31
                  [005640]  7207          bis     r31, r31, r31
                  [005640]  7208          bis     r31, r31, r31
                  [005640]  7209  
                  [005640]  7210          bis     r1, #0, p4                      ; impure pointer
                  [005640]  7211          hw_ldq/p r0, CNS__R0(p4)           	; restore r0
                  [005640]  7212          hw_ldq/p r1, CNS__R1(p4)           	; restore r1
                  [005640]  7213          hw_ldq/p r2, CNS__R2(p4)           	; restore r2
                  [005640]  7214  
                  [005640]  7215          hw_ldq/p r3, CNS__R3(p4)           	; restore r3
                  [005640]  7216          hw_ret_stall  (p23)                     ; return
                  [005640]  7217  
                  [005640]  7218    .endc						; if/iff eq ev6_p1
                  [005640]  7219  
                  [005640]  7220          END_CALL_PAL
                  [005640]  7221  .endc						; if ne clrmap
                  [005640]  7222  
                  [005640]  7223  ;+
                  [005640]  7224  ; CALL_PAL__URTI
                  [005640]  7225  ;
                  [005640]  7226  ; Entry:
                  [005640]  7227  ;	p23		pc of instruction following the call_pal instruction
                  [005640]  7228  ;
                  [005640]  7229  ; Function:
                  [005640]  7230  ;	The return from user mode trap insruction pops the user registers
                  [005640]  7231  ;	(a0..a2, and GP), the new user AT, SP, PC and PS from the user stack.
                  [005640]  7232  ;
                  [005640]  7233  ; Stack Frame:
                  [005640]  7234  ;	---------------------------------------------------------
                  [005640]  7235  ;	|			at				|:00
                  [005640]  7236  ;	---------------------------------------------------------
                  [005640]  7237  ;	|			SP				|:08
                  [005640]  7238  ;	---------------------------------------------------------
                  [005640]  7239  ;	|			PS				|:16
                  [005640]  7240  ;	---------------------------------------------------------
                  [005640]  7241  ;	|			PC				|:24
                  [005640]  7242  ;	---------------------------------------------------------
                  [005640]  7243  ;	|			GP				|:32
                  [005640]  7244  ;	---------------------------------------------------------
                  [005640]  7245  ;	|			a0				|:40
                  [005640]  7246  ;	---------------------------------------------------------
                  [005640]  7247  ;	|			a1				|:48
                  [005640]  7248  ;	---------------------------------------------------------
                  [005640]  7249  ;	|			a2				|:56
                  [005640]  7250  ;	---------------------------------------------------------
                  [005640]  7251  ;
                  [005640]  7252  ; Algorithm:
                  [005640]  7253  ;	if (PS<mode> EQ 0) then
                  [005640]  7254  ;		machineCheck
                  [005640]  7255  ;	 endif
                  [005640]  7256  ;	if {SP<5:0> NE 0 }
                  [005640]  7257  ;		{ initiate illegal operand exception }
                  [005640]  7258  ;	tempps  <- (SP+16)              ! Check access to stack frame
                  [005640]  7259  ;	if {{ tempps<mode> EQ 0 } OR {tempps<IPL> NE 0 }} then
                  [005640]  7260  ;		{ initiate illegal operand exception }
                  [005640]  7261  ;	endif
                  [005640]  7262  ;
                  [005640]  7263  ;	at      <- (SP+0)
                  [005640]  7264  ;	tempsp  <- (SP+8)
                  [005640]  7265  ;	temppc  <- (SP+24)
                  [005640]  7266  ;	GP      <- (SP+32)
                  [005640]  7267  ;	a0      <- (SP+40)
                  [005640]  7268  ;	a1      <- (SP+48)
                  [005640]  7269  ;	a2      <- (SP+56)
                  [005640]  7270  ;
                  [005640]  7271  ;	intr_flag = 0
                  [005640]  7272  ;	lock_flag = 0
                  [005640]  7273  ;
                  [005640]  7274  ;	SP      <- tempsp
                  [005640]  7275  ;	PC      <- temppc
                  [005640]  7276  ;
                  [005640]  7277  ; Note: On a multiprocessor system, the other CPU can mark the in-memory
                  [005640]  7278  ; PTE with fault bits to indicate it is a LRU candidate for the VM
                  [005640]  7279  ; system. The PALcode must ensure it sees the same PTE throughout the
                  [005640]  7280  ; operation. By doing a scoreboard stall, we ensure that we either
                  [005640]  7281  ; get what's already in the TB for the entire operation, or take the
                  [005640]  7282  ; miss and get a new PTE that we use for the entire operation.
                  [005640]  7283  ;-
                  [005640]  7284  	START_CALL_PAL <URTI>
File: ev6_pal_macros.mar
                  [005640]   104i         ASSUME <<OSFPAL_FUNC__URTI> & <^x40>> eq 0
                  [005640]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [003480]   120i CALL_PAL__URTI::
File: ev6_osf_pal.mar
                  [003480]  7285  
         77FF27F0 [003480]  7286  	hw_mtpr	r31, <EV6__MM_STAT ! ^xF0>	; 1.40 wait for pte write
                  [003484]  7287  
         7EF51060 [003484]  7288  	hw_stq/p p23, PT__STACK_PC(p_temp)		; in case of fault
                  [003488]  7289  
         46C11004 [003488]  7290  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p4	; current mode
         47C7F005 [00348C]  7291  	and	r30, #^x3F, p5				; check alignment
         63FFE000 [003490]  7292  	rc	r31					; clear interrrupt flag
                  [003494]  7293  
         E49FF422 [003494]  7294  	beq	p4, trap__pal_os_bugcheck		; mchk if kernel mode
         F4A00872 [003498]  7295  	bne	p5, call_pal__urti_illop		; error if unaligned
                  [00349C]  7296  ;
                  [00349C]  7297  ; The stack is naturally aligned, so we don't need to probe the ends.
                  [00349C]  7298  ; TNV and DFaults can occur on the first read. We also must
                  [00349C]  7299  ; avoid misses anywhere after the first read because another cpu
                  [00349C]  7300  ; may have marked the in memory PTE with fault bits to indicate it is a LRU
                  [00349C]  7301  ; candidate in the VM handler. We must ensure we see the same PTE the entire
                  [00349C]  7302  ; flow. So, at the beginning of this flow, we did a scoreboard stall to
                  [00349C]  7303  ; avoid having a mid-stream PTE/TAG  write retire and kick our entry out.
                  [00349C]  7304  ;
                  [00349C]  7305  call_pal__urti_ldq:
         A69E0010 [00349C]  7306  	ldq	p20, 16(r30)				; fetch new ps
         4681F004 [0034A0]  7307  	and	p20, #^xF, p4				; check <3:0>
                  [0034A4]  7308  							; 1.37 take out urti_stq
         44811804 [0034A4]  7309  	xor	p4, #<1@OSF_PS__CM__S>, p4		; test cm=1, ipl=0
         F480086E [0034A8]  7310  	bne	p4, call_pal__urti_illop
                  [0034AC]  7311  
                  [0034AC]  7312  	CONT_CALL_PAL <URTI>
File: ev6_pal_macros.mar
                  [0034AC]   181M     ASSUME <_pal_func_cont> eq 0
         C3E00864 [0034AC]   186i 	br	r31, CALL_PAL__URTI_CONT
                  [0034B0]   189M                 ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [0034B0]   191M     GOTO_FREE_CODE
                  [005640]    67M     .align 6
                  [005640]   196i CALL_PAL__URTI_CONT:
File: ev6_osf_pal.mar
                  [005640]  7313  
         A69E0018 [005640]  7314  	ldq	p20, 24(r30)				; 1.39 new pc
         46807114 [005644]  7315  	bic	p20, #3, p20				; 1.39 clean pc
                  [005648]  7316  
         A61E0028 [005648]  7317  	ldq	r16, 40(r30)				; a0
         A63E0030 [00564C]  7318  	ldq	r17, 48(r30)				; a1
         A65E0038 [005650]  7319  	ldq	r18, 56(r30)				; a2
         A7BE0020 [005654]  7320  	ldq	r29, 32(r30)				; gp
         A79E0000 [005658]  7321  	ldq	r28, 0(r30)				; at
         A7DE0008 [00565C]  7322  	ldq	r30, 8(r30)				; sp
                  [005660]  7323  
         7BF48000 [005660]  7324  	hw_ret	(p20)					; 1.39 return
                  [005664]  7325  ;
                  [005664]  7326  ; Illop. Either stack not aligned or new ps wrong.
                  [005664]  7327  ;
                  [005664]  7328  call_pal__urti_illop:
         6EF51060 [005664]  7329  	hw_ldq/p p23, PT__STACK_PC(p_temp)		; 1.37 get pc back
         47E0B404 [005668]  7330  	bis	r31, #OSF_A0__ILLOP, p4			; new a0
         7C951068 [00566C]  7331  	hw_stq/p p4, PT__NEW_A0(p_temp)			; save it away
         42E09537 [005670]  7332  	subq	p23, #4, p23				; want pc of urti
         C3FFFFB2 [005674]  7333  	br	r31, call_pal__bpt_post_if		; merge to complete
                  [005678]  7334  
                  [005678]  7335  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [005678]   176M         GOTO_FREE_CODE
00000000 00000000 [005678]    67M     .align 6
File: ev6_osf_pal.mar
                  [005680]  7336  
                  [005680]  7337  ;+
                  [005680]  7338  ; CALL_PAL__RDUNIQUE
                  [005680]  7339  ;
                  [005680]  7340  ; Entry:
                  [005680]  7341  ;	p23		pc of instruction following the call_pal instruction
                  [005680]  7342  ;
                  [005680]  7343  ; Function:
                  [005680]  7344  ;	Write into r0(v0) the hardware process (thread) unique context value.
                  [005680]  7345  ;
                  [005680]  7346  ; Exit state:
                  [005680]  7347  ;	r0(v0)		process unique context
                  [005680]  7348  ;
                  [005680]  7349  ;-
                  [005680]  7350  	START_CALL_PAL <RDUNIQUE>
File: ev6_pal_macros.mar
                  [005680]   104i         ASSUME <<OSFPAL_FUNC__RDUNIQUE> & <^x40>> eq 0
                  [005680]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [003780]   120i CALL_PAL__RDUNIQUE::
File: ev6_osf_pal.mar
                  [003780]  7351  
         6C151010 [003780]  7352  	hw_ldq/p r0, PT__PCBB(p_temp)	; get PCBB
         6C001020 [003784]  7353  	hw_ldq/p r0, OSF_PCB__UNQ(r0)	; get UNQ
                  [003788]  7354  	NOP				; no hw_ret in 1st fetch block
File: ev6_pal_macros.mar
         47FF041F [003788]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [00378C]  7355  	NOP
File: ev6_pal_macros.mar
         47FF041F [00378C]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [003790]  7356  
         7BF78000 [003790]  7357  	hw_ret	(p23)			; return
                  [003794]  7358  
                  [003794]  7359  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [003794]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [003794]   176M         GOTO_FREE_CODE
                  [005680]    67M     .align 6
File: ev6_osf_pal.mar
                  [005680]  7360  
                  [005680]  7361  ;+
                  [005680]  7362  ; CALL_PAL__WRUNIQUE
                  [005680]  7363  ;
                  [005680]  7364  ; Entry:
                  [005680]  7365  ;	p23		pc of instruction following the call_pal instruction
                  [005680]  7366  ;
                  [005680]  7367  ; Function:
                  [005680]  7368  ;	Store the value of r16(a0) in the hardware process (thread) unique
                  [005680]  7369  ;	context value.
                  [005680]  7370  ;-
                  [005680]  7371  	START_CALL_PAL <WRUNIQUE>
File: ev6_pal_macros.mar
                  [005680]   104i         ASSUME <<OSFPAL_FUNC__WRUNIQUE> & <^x40>> eq 0
                  [005680]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [0037C0]   120i CALL_PAL__WRUNIQUE::
File: ev6_osf_pal.mar
                  [0037C0]  7372  
         6C951010 [0037C0]  7373  	hw_ldq/p p4, PT__PCBB(p_temp)	; get PCBB
         7E041020 [0037C4]  7374  	hw_stq/p r16, OSF_PCB__UNQ(p4)	; write UNQ
                  [0037C8]  7375  	NOP				; no hw_ret in 1st fetch block
File: ev6_pal_macros.mar
         47FF041F [0037C8]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [0037CC]  7376  	NOP
File: ev6_pal_macros.mar
         47FF041F [0037CC]   283M 	bis	r31, r31, r31
File: ev6_osf_pal.mar
                  [0037D0]  7377  
         7BF78000 [0037D0]  7378  	hw_ret	(p23)			; return
                  [0037D4]  7379  
                  [0037D4]  7380  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [0037D4]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [0037D4]   176M         GOTO_FREE_CODE
                  [005680]    67M     .align 6
File: ev6_osf_pal.mar
                  [005680]  7381  
                  [005680]  7382  
                  [005680]  7383  ;+
                  [005680]  7384  ; CALL_PAL__GENTRAP
                  [005680]  7385  ;
                  [005680]  7386  ; Entry:
                  [005680]  7387  ;	p23		pc of instruction following the call_pal instruction
                  [005680]  7388  ;
                  [005680]  7389  ; Function:
                  [005680]  7390  ;	The gentrap instruction switches mode to kernel, builds a
                  [005680]  7391  ;	stack frame on the kernel stack, loads the GP with the KGP, loads
                  [005680]  7392  ;	a value of 2 into a0, and dispatches to the breakpoint code pointed
                  [005680]  7393  ;	to by the entIF register. The saved PC at (SP+08) is the address
                  [005680]  7394  ;	of the instruction following the trap instruction that caused the
                  [005680]  7395  ;	trap.
                  [005680]  7396  ;-
                  [005680]  7397  	START_CALL_PAL <GENTRAP>
File: ev6_pal_macros.mar
                  [005680]   104i         ASSUME <<OSFPAL_FUNC__GENTRAP> & <^x40>> eq 0
                  [005680]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [003A80]   120i CALL_PAL__GENTRAP::
File: ev6_osf_pal.mar
                  [003A80]  7398  
         47E05404 [003A80]  7399  	bis	r31, #OSF_A0__GENTRAP, p4		; new a0
         7C951068 [003A84]  7400  	hw_stq/p p4, PT__NEW_A0(p_temp)			; save it away
         C3E006AD [003A88]  7401  	br	r31, call_pal__bpt_post_if		; merge to complete
                  [003A8C]  7402  
                  [003A8C]  7403  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [003A8C]   172i         ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [003A8C]   176M         GOTO_FREE_CODE
                  [005680]    67M     .align 6
File: ev6_osf_pal.mar
                  [005680]  7404  
                  [005680]  7405  
                  [005680]  7406  
                  [005680]  7407  .if ne ev6_p1
                  [005680]  7408      .if ne fp_count
                  [005680]  7409  
                  [005680]  7410  ;+
                  [005680]  7411  ; CALL_PAL__FP_COUNT
                  [005680]  7412  ;
                  [005680]  7413  ; Entry:
                  [005680]  7414  ;	p23		pc of instruction following the call_pal instruction
                  [005680]  7415  ;
                  [005680]  7416  ; Function:
                  [005680]  7417  ;	r0(v0) <- fp counter
                  [005680]  7418  ;
                  [005680]  7419  ;-
                  [005680]  7420  
                  [005680]  7421  OSFPAL_FUNC__00AD = ^xAD
                  [005680]  7422  
                  [005680]  7423  	START_CALL_PAL <00AD>
                  [005680]  7424  
                  [005680]  7425  	hw_ldq/p r0, PT__RSV_FOR_PAL(p_temp)	; read fp counter
                  [005680]  7426  	NOP					; no hw_ret in 1st fetch block
                  [005680]  7427  	NOP
                  [005680]  7428  	NOP
                  [005680]  7429  
                  [005680]  7430  	hw_ret	(p23)				; return to user
                  [005680]  7431  
                  [005680]  7432  	END_CALL_PAL
                  [005680]  7433  
                  [005680]  7434      .endc
                  [005680]  7435  .endc
                  [005680]  7436  
                  [005680]  7437  
                  [005680]  7438  ;+
                  [005680]  7439  ; CALL_PAL__CLRFEN
                  [005680]  7440  ;
                  [005680]  7441  ; Entry:
                  [005680]  7442  ;	p23		pc of instruction following the call_pal instruction
                  [005680]  7443  ;
                  [005680]  7444  ; Function:
                  [005680]  7445  ;	The clear floating-point enable (CLRFEN) instruction writes a
                  [005680]  7446  ;	zero to the floating-point enable register and to the PCB
                  [005680]  7447  ;	at offset (PCBB+FEN)<0>.
                  [005680]  7448  ;
                  [005680]  7449  ;	FEN 	   <- 0
                  [005680]  7450  ;	(PCB+FEN) <- FEN
                  [005680]  7451  ;-
                  [005680]  7452  	START_CALL_PAL <CLRFEN>
File: ev6_pal_macros.mar
                  [005680]   104i         ASSUME <<OSFPAL_FUNC__CLRFEN> & <^x40>> eq 0
                  [005680]   111M     ASSUME <_pal_func_in_prog> eq 0
                  [003B80]   120i CALL_PAL__CLRFEN::
File: ev6_osf_pal.mar
                  [003B80]  7453  
         6C951010 [003B80]  7454  	hw_ldq/p p4, PT__PCBB(p_temp)		; get PCBB
         77FF5010 [003B84]  7455  	hw_mtpr	r31, EV6__FPE			; (4,0L) write new fpe
         7FE40028 [003B88]  7456  	hw_stl/p r31, OSF_PCB__FEN(p4)		; store cleared FEN in PCB
         47FF041F [003B8C]  7457  	bis	r31, r31, r31
                  [003B90]  7458  
         77FF5010 [003B90]  7459  	hw_mtpr	r31, EV6__FPE			; (4,0L) force retire
         47FF041F [003B94]  7460  	bis	r31, r31, r31
         47FF041F [003B98]  7461  	bis	r31, r31, r31
         47FF041F [003B9C]  7462  	bis	r31, r31, r31
                  [003BA0]  7463  
         44000400 [003BA0]  7464  	bis	r0, r0, r0			; buffer block 1
         47FF041F [003BA4]  7465  	bis	r31, r31, r31
         47FF041F [003BA8]  7466  	bis	r31, r31, r31
         47FF041F [003BAC]  7467  	bis	r31, r31, r31
                  [003BB0]  7468  
         44000400 [003BB0]  7469  	bis	r0, r0, r0			; buffer block 2
         47FF041F [003BB4]  7470  	bis	r31, r31, r31
         47FF041F [003BB8]  7471  	bis	r31, r31, r31
                  [003BBC]  7472  	CONT_CALL_PAL <CLRFEN>
File: ev6_pal_macros.mar
                  [003BBC]   181M     ASSUME <_pal_func_cont> eq 0
         C3E006B0 [003BBC]   186i 	br	r31, CALL_PAL__CLRFEN_CONT
                  [003BC0]   189M                 ASSUME <.-_start_of_last_pal_func> le <^x40>
                  [003BC0]   191M     GOTO_FREE_CODE
                  [005680]    67M     .align 6
                  [005680]   196i CALL_PAL__CLRFEN_CONT:
File: ev6_osf_pal.mar
                  [005680]  7473  
         44000400 [005680]  7474  	bis	r0, r0, r0			; buffer block 3
         47FF041F [005684]  7475  	bis	r31, r31, r31
         47FF041F [005688]  7476  	bis	r31, r31, r31
         47FF041F [00568C]  7477  	bis	r31, r31, r31
                  [005690]  7478  
                  [005690]  7479  .if ne ev6_p1
                  [005690]  7480  	hw_ldq/p p5, PT__IMPURE(p_temp)		; get impure pointer
                  [005690]  7481  	hw_stq/p r31, CNS__FPE_STATE(p5)	; clear FPE state	
                  [005690]  7482  .endc
                  [005690]  7483  
         7BF7A000 [005690]  7484  	hw_ret_stall (p23)			; return with stall
                  [005694]  7485  
                  [005694]  7486  	END_CALL_PAL
File: ev6_pal_macros.mar
                  [005694]   176M         GOTO_FREE_CODE
00000000 00000000 [005694]    67M     .align 6
00000000 00000000 [00569C]
00000000 00000000 [0056A4]
00000000 00000000 [0056AC]
00000000 00000000 [0056B4]
         00000000 [0056BC]
File: ev6_osf_pal.mar
                  [0056C0]  7487  
                  [0056C0]  7488  	END_FREE_CODE
File: sromcsrv.mar
                  [0056C0]     1  ;/*
                  [0056C0]     2  ;*****************************************************************************
                  [0056C0]     3  ;**                                                                          *
                  [0056C0]     4  ;**  Copyright © 1994							    *
                  [0056C0]     5  ;**  by Digital Equipment Corporation, Maynard, Massachusetts.		    *
                  [0056C0]     6  ;**                                                                          *
                  [0056C0]     7  ;**  All Rights Reserved							    *
                  [0056C0]     8  ;**                                                                          *
                  [0056C0]     9  ;**  Permission  is  hereby  granted  to  use, copy, modify and distribute   *
                  [0056C0]    10  ;**  this  software  and  its  documentation,  in  both  source  code  and   *
                  [0056C0]    11  ;**  object  code  form,  and without fee, for the purpose of distribution   *
                  [0056C0]    12  ;**  of this software  or  modifications  of this software within products   *
                  [0056C0]    13  ;**  incorporating  an  integrated   circuit  implementing  Digital's  AXP   *
                  [0056C0]    14  ;**  architecture,  regardless  of the  source of such integrated circuit,   *
                  [0056C0]    15  ;**  provided that the  above copyright  notice and this permission notice   *
                  [0056C0]    16  ;**  appear  in  all copies,  and  that  the  name  of  Digital  Equipment   *
                  [0056C0]    17  ;**  Corporation  not  be  used  in advertising or publicity pertaining to   *
                  [0056C0]    18  ;**  distribution of the  document  or  software without specific, written   *
                  [0056C0]    19  ;**  prior permission.							    *
                  [0056C0]    20  ;**                                                                          *
                  [0056C0]    21  ;**  Digital  Equipment  Corporation   disclaims  all   warranties  and/or   *
                  [0056C0]    22  ;**  guarantees  with  regard  to  this  software,  including  all implied   *
                  [0056C0]    23  ;**  warranties of fitness for  a  particular purpose and merchantability,   *
                  [0056C0]    24  ;**  and makes  no  representations  regarding  the use of, or the results   *
                  [0056C0]    25  ;**  of the use of, the software and documentation in terms of correctness,  *
                  [0056C0]    26  ;**  accuracy,  reliability,  currentness  or  otherwise;  and you rely on   *
                  [0056C0]    27  ;**  the software, documentation and results solely at your own risk.	    *
                  [0056C0]    28  ;**                                                                          *
                  [0056C0]    29  ;**  AXP is a trademark of Digital Equipment Corporation.		    *
                  [0056C0]    30  ;**                                                                          *
                  [0056C0]    31  ;*****************************************************************************
                  [0056C0]    32  ;**
                  [0056C0]    33  ;**  FACILITY:	
                  [0056C0]    34  ;**
                  [0056C0]    35  ;**	DECchip 21064/21066/211164 OSF/1 PALcode
                  [0056C0]    36  ;**
                  [0056C0]    37  ;**  MODULE:
                  [0056C0]    38  ;**
                  [0056C0]    39  ;** 	sromcsrv.s
                  [0056C0]    40  ;** 
                  [0056C0]    41  ;**  MODULE DESCRIPTION:
                  [0056C0]    42  ;** 
                  [0056C0]    43  ;**	Interface to SROM Serial Port I/O routines.
                  [0056C0]    44  ;** 
                  [0056C0]    45  ;**  AUTHOR: Franklin Hooker
                  [0056C0]    46  ;** 
                  [0056C0]    47  ;**  CREATION-DATE: 13-May-1996
                  [0056C0]    48  ;**
                  [0056C0]    49  ;**  $Id: sromcsrv.mar,v 1.3 1999/03/22 14:54:44 samberg Exp $
                  [0056C0]    50  ;**
                  [0056C0]    51  ;**  MODIFICATION HISTORY: 
                  [0056C0]    52  ;**
                  [0056C0]    53  ;**  $Log: sromcsrv.mar,v $
                  [0056C0]    54  ;**  Revision 1.3  1999/03/22 14:54:44  samberg
                  [0056C0]    55  ;**
                  [0056C0]    56  ;**  palcode release vms 1.54 unix 1.49
                  [0056C0]    57  ;**
                  [0056C0]    58  ;** Revision 1.4  1998/12/29  16:30:57  samberg
                  [0056C0]    59  ;** In srom_init, load mc_m_echo (^x100) into r0 instead of trying to use it as a literal.
                  [0056C0]    60  ;**
                  [0056C0]    61  ;** Revision 1.3  1997/11/12  15:31:21  samberg
                  [0056C0]    62  ;** Make pvc clean
                  [0056C0]    63  ;**
                  [0056C0]    64  ;** Revision 1.2  1997/10/20  17:30:10  samberg
                  [0056C0]    65  ;** checkin to my library
                  [0056C0]    66  ;**
                  [0056C0]    67  ;** Revision 1.1  1997/10/20  16:40:10  samberg
                  [0056C0]    68  ;** Initial revision
                  [0056C0]    69  ;**
                  [0056C0]    70  ;**  Revision 1.2  1997/08/12  04:33:38  fdh
                  [0056C0]    71  ;**  Modified register usage for compatibility with PALcode.
                  [0056C0]    72  ;**
                  [0056C0]    73  ;**  Revision 1.1  1997/08/07  14:35:53  fdh
                  [0056C0]    74  ;**  Initial revision
                  [0056C0]    75  ;**
                  [0056C0]    76  ;# Revision 1.4  1997/05/02  13:45:24  pbell
                  [0056C0]    77  ;# Updated to use the cpu.h include file instead of all
                  [0056C0]    78  ;# the cpu type switches.
                  [0056C0]    79  ;#
                  [0056C0]    80  ;# Revision 1.3  1997/02/21  04:25:35  fdh
                  [0056C0]    81  ;# Modified to save line status in a global variable
                  [0056C0]    82  ;# instead of a PALtemp.
                  [0056C0]    83  ;#
                  [0056C0]    84  ;# Revision 1.2  1996/08/22  14:07:35  fdh
                  [0056C0]    85  ;# Save/restore r15 to/from pt11.
                  [0056C0]    86  ;#
                  [0056C0]    87  ;# Revision 1.1  1996/05/22  22:25:47  fdh
                  [0056C0]    88  ;# Initial revision
                  [0056C0]    89  ;#
                  [0056C0]    90  ;*/
                  [0056C0]    91  mc_m_echo		= ^x0100	; (1 << mc_v_echo)
                  [0056C0]    92  
                  [0056C0]    93  .macro	SROM_CSERVES func
                  [0056C0]    94  
                  [0056C0]    95  ;/*
                  [0056C0]    96  ;**
                  [0056C0]    97  ;** FUNCTIONAL DESCRIPTION:
                  [0056C0]    98  ;**
                  [0056C0]    99  ;**      Initialize the SROM serial port for character I/O.
                  [0056C0]   100  ;**
                  [0056C0]   101  ;** INPUT PARAMETERS:
                  [0056C0]   102  ;**
                  [0056C0]   103  ;**      None
                  [0056C0]   104  ;**
                  [0056C0]   105  ;** OUTPUT PARAMETERS:
                  [0056C0]   106  ;**
                  [0056C0]   107  ;**	None
                  [0056C0]   108  ;**
                  [0056C0]   109  ;** SIDE EFFECTS:
                  [0056C0]   110  ;**
                  [0056C0]   111  ;*/
                  [0056C0]   112  	ALIGN_FETCH_BLOCK
                  [0056C0]   113  
                  [0056C0]   114  Sys_Cserve_Srom_Init:
                  [0056C0]   115  	PVC_JSR	auto, bsr=1
                  [0056C0]   116  	bsr	p7, autobaud_sync	; do the autobaud thing	
                  [0056C0]   117  	lda	r0, mc_m_echo(r31)	; get ^x100
                  [0056C0]   118  	bis	r24, r0, r24		; Enable echo 	
                  [0056C0]   119  	bis	r24, r31, r0		; Return Line Status	
                  [0056C0]   120  	hw_ret	(p23)
                  [0056C0]   121  
                  [0056C0]   122  
                  [0056C0]   123  ;/*
                  [0056C0]   124  ;**
                  [0056C0]   125  ;** FUNCTIONAL DESCRIPTION:
                  [0056C0]   126  ;**
                  [0056C0]   127  ;**      Output a character to the SROM serial port.
                  [0056C0]   128  ;**
                  [0056C0]   129  ;** INPUT PARAMETERS:
                  [0056C0]   130  ;**
                  [0056C0]   131  ;**      a1 (r17) - Output Character
                  [0056C0]   132  ;**
                  [0056C0]   133  ;** OUTPUT PARAMETERS:
                  [0056C0]   134  ;**
                  [0056C0]   135  ;**	None
                  [0056C0]   136  ;**
                  [0056C0]   137  ;** SIDE EFFECTS:
                  [0056C0]   138  ;**
                  [0056C0]   139  ;*/
                  [0056C0]   140  	ALIGN_FETCH_BLOCK
                  [0056C0]   141  
                  [0056C0]   142  Sys_Cserve_Srom_Putc:
                  [0056C0]   143  	bis	r19, r31, r24
                  [0056C0]   144  	PVC_JSR putchar, bsr=1
                  [0056C0]   145  	bsr	p7, putChar
                  [0056C0]   146  	hw_ret	(p23)
                  [0056C0]   147  
                  [0056C0]   148  
                  [0056C0]   149  ;/*
                  [0056C0]   150  ;**
                  [0056C0]   151  ;** FUNCTIONAL DESCRIPTION:
                  [0056C0]   152  ;**
                  [0056C0]   153  ;**      Get a character from the SROM serial port
                  [0056C0]   154  ;**
                  [0056C0]   155  ;** INPUT PARAMETERS:
                  [0056C0]   156  ;**
                  [0056C0]   157  ;**      None
                  [0056C0]   158  ;**
                  [0056C0]   159  ;** OUTPUT PARAMETERS:
                  [0056C0]   160  ;**
                  [0056C0]   161  ;**	v0 (r0) - Input Character
                  [0056C0]   162  ;**
                  [0056C0]   163  ;** SIDE EFFECTS:
                  [0056C0]   164  ;**
                  [0056C0]   165  ;*/
                  [0056C0]   166  	ALIGN_FETCH_BLOCK
                  [0056C0]   167  
                  [0056C0]   168  Sys_Cserve_Srom_Getc:
                  [0056C0]   169  	bis	r19, r31, r24
                  [0056C0]   170  	PVC_JSR	getchar, bsr=1
                  [0056C0]   171  	bsr	p7, getChar
                  [0056C0]   172  	hw_ret	(p23)
                  [0056C0]   173  
                  [0056C0]   174  .endm	SROM_CSERVES
File: sromio.mar
                  [0056C0]     1  ; FDH....
                  [0056C0]     2  ; Modified register usage to use only volatile registers
                  [0056C0]     3  ; as defined by the calling standards.  Usage of r15 was
                  [0056C0]     4  ; replaced by r24. This file was originally sromio.s which
                  [0056C0]     5  ; is shared with the SROM mini-debugger. The register usage
                  [0056C0]     6  ; in the mini-debugger should be changed to comply with the
                  [0056C0]     7  ; register usage here so that these files can be merged again.
                  [0056C0]     8  ; At that point this file can be removed.  The following
                  [0056C0]     9  ; mini-debugger register usages changes should be made.
                  [0056C0]    10  ;
                  [0056C0]    11  ; 	r15 -> r24
                  [0056C0]    12  ; 	r16 -> r15
                  [0056C0]    13  ; 	r17 -> r16
                  [0056C0]    14  ; 	r18 -> r17
                  [0056C0]    15  ; 	r19 -> r18
                  [0056C0]    16  ; 	r20 -> r19
                  [0056C0]    17  ; 	r21 -> r20
                  [0056C0]    18  ; 	r22 -> r21
                  [0056C0]    19  ;
                  [0056C0]    20  
                  [0056C0]    21  .macro	SROM_IO_FUNCTIONS func
                  [0056C0]    22  ;
                  [0056C0]    23  ; the following bits definitions are flags for the mini-debugger
                  [0056C0]    24  ;
                  [0056C0]    25  
                  [0056C0]    26  mc_v_qw			= 0		; qw output mode flag 			
                  [0056C0]    27  mc_v_display		= 1		; Display on/off flag.			
                  [0056C0]    28  mc_v_loop		= 2		; infinite loop flag 			
                  [0056C0]    29  mc_v_writeaddr		= 3		; A fill with address command.		
                  [0056C0]    30  mc_v_notdata		= 4		; Negate data written.                  
                  [0056C0]    31  mc_v_base		= 5		; base address flag 			
                  [0056C0]    32  mc_v_follow_w_rd	= 6		; Follow command with a read.		
                  [0056C0]    33  mc_v_follow_w_wr	= 7		; Follow command with a write.		
                  [0056C0]    34  mc_v_echo		= 8		; echo output flag 			
                  [0056C0]    35  mc_v_write		= 9		; write/not_read flag 			
                  [0056C0]    36  mc_v_xm			= 10		; An XM command has been executed.	
                  [0056C0]    37  mc_v_block		= 11		; block read/write flag 		
                  [0056C0]    38  mc_v_cmp		= 12		; A CoMpare command.			
                  [0056C0]    39  mc_v_cp			= 13		; A Copy command.			
                  [0056C0]    40  mc_v_mt			= 14		; A memory test command.		
                  [0056C0]    41  
                  [0056C0]    42  mc_m_qw			= ^x0001	; (1 << mc_v_qw)
                  [0056C0]    43  mc_m_display		= ^x0002	; (1 << mc_v_display)
                  [0056C0]    44  mc_m_loop		= ^x0004	; (1 << mc_v_loop)
                  [0056C0]    45  mc_m_writeaddr		= ^x0008	; (1 << mc_v_writeaddr)
                  [0056C0]    46  mc_m_notdata		= ^x0010	; (1 << mc_v_notdata)  
                  [0056C0]    47  mc_m_base		= ^x0020	; (1 << mc_v_base)	
                  [0056C0]    48  mc_m_follow_w_rd	= ^x0040	; (1 << mc_v_follow_w_rd)
                  [0056C0]    49  mc_m_follow_w_wr	= ^x0080	; (1 << mc_v_follow_w_wr)
                  [0056C0]    50  mc_m_echo		= ^x0100	; (1 << mc_v_echo)
                  [0056C0]    51  mc_m_write		= ^x0200	; (1 << mc_v_write)
                  [0056C0]    52  mc_m_xm			= ^x0400	; (1 << mc_v_xm)
                  [0056C0]    53  mc_m_block		= ^x0800	; (1 << mc_v_block)
                  [0056C0]    54  mc_m_cmp		= ^x1000	; (1 << mc_v_cmp)
                  [0056C0]    55  mc_m_cp			= ^x2000	; (1 << mc_v_cp)
                  [0056C0]    56  mc_m_mt			= ^x4000	; (1 << mc_v_mt)
                  [0056C0]    57  
                  [0056C0]    58  ascii_X			= ^x58
                  [0056C0]    59  
                  [0056C0]    60  
                  [0056C0]    61  ; ======================================================================
                  [0056C0]    62  ; = keypressed - detect if user pressed a key				=
                  [0056C0]    63  ; ======================================================================
                  [0056C0]    64  ; OVERVIEW:
                  [0056C0]    65  ;       Returns a 1 if a key has been pressed, 0 if not.
                  [0056C0]    66  ;       check the serial line interrupt bit, if it's set, clear it
                  [0056C0]    67  ;       and return 1, otherwise, return 0
                  [0056C0]    68  ;
                  [0056C0]    69  ; FORM_OF_CALL:
                  [0056C0]    70  ;       bsr r20, keypressed
                  [0056C0]    71  ;  
                  [0056C0]    72  ; RETURNS:
                  [0056C0]    73  ;       R0  - 1 if keypressed, else 0
                  [0056C0]    74  ; 
                  [0056C0]    75  ; SIDE EFFECTS:
                  [0056C0]    76  ;       The Serial Line Interrupt bit is cleared.
                  [0056C0]    77  ;
                  [0056C0]    78  ; ARGUMENTS:
                  [0056C0]    79  ;       none
                  [0056C0]    80  ;
                  [0056C0]    81  ; REGISTERS:
                  [0056C0]    82  ;       R0  - scratch & return value
                  [0056C0]    83  ;       R20 - return address 
                  [0056C0]    84  ;       
                  [0056C0]    85  ; CALLS:
                  [0056C0]    86  ;       none
                  [0056C0]    87  ;
                  [0056C0]    88   
                  [0056C0]    89  keypressed:
                  [0056C0]    90  	hw_mfpr	r0, ev6__isum 			; read Interrupt Summary Register 
                  [0056C0]    91  	srl	r0, #ev6__isum__sl__s, r0	; r0<0> <- Serial Line Intrpt bit 
                  [0056C0]    92  	and	r0, #ev6__isum__sl__m, r0	; :				 
                  [0056C0]    93  	sll	r0, #ev6__hw_int_clr__sl__s, r0	; put into position		 
                  [0056C0]    94  	PVC_VIOLATE <11>			; EJS -- ignore lack of stall
                  [0056C0]    95  	PVC_VIOLATE <35>			; EJS -- ignore not writing twice
                  [0056C0]    96  	hw_mtpr	r0, ev6__hw_int_clr		; Clear any serial line intrpt 
                  [0056C0]    97  	cmovne	r0, #1, r0			; Return 1 if a key was pressed  
                  [0056C0]    98  
                  [0056C0]    99  	PVC_VIOLATE <29>
                  [0056C0]   100  	PVC_JSR	key, bsr=1, dest=1
                  [0056C0]   101  	ret	r31, (r20)
                  [0056C0]   102  
                  [0056C0]   103  
                  [0056C0]   104  ; ======================================================================
                  [0056C0]   105  ; = getChar -- routine to receive a character from the serial line	=
                  [0056C0]   106  ; ======================================================================
                  [0056C0]   107  ; OVERVIEW:
                  [0056C0]   108  ;       Once the start bit of '0' is detected we wait 1 1/2 bit times 
                  [0056C0]   109  ;       before reading the first data bit.  The data bit is packed into a 
                  [0056C0]   110  ;       register and shifted left.  After the first bit we only wait 
                  [0056C0]   111  ;       whole bit times.  After 8 bits have been read the routine is exited.
                  [0056C0]   112  ;
                  [0056C0]   113  ; FORM OF CALL:
                  [0056C0]   114  ;       bsr	p7, getChar
                  [0056C0]   115  ; 
                  [0056C0]   116  ; RETURNS:
                  [0056C0]   117  ;       R0  - Character returned after user input
                  [0056C0]   118  ;       
                  [0056C0]   119  ; CALLS:
                  [0056C0]   120  ;       waitBitHalf
                  [0056C0]   121  ;       waitBitTime
                  [0056C0]   122  ;       
                  [0056C0]   123  ; REGISTERS:
                  [0056C0]   124  ;       R1  - Scratch.
                  [0056C0]   125  ;       R2  - Bit counter AND character acumulator.
                  [0056C0]   126  ;             Bits <0:7> is the bit counter (with an extra value of 8)
                  [0056C0]   127  ;             Bits <8:15> is the character typed in.
                  [0056C0]   128  ;       R20 - return address for the call to waitBitTime()
                  [0056C0]   129  ;
                  [0056C0]   130   
                  [0056C0]   131  getChar:
                  [0056C0]   132  	lda	r2, <0+8>(r31)			; Set the bit count to 0.	 
                  [0056C0]   133  
                  [0056C0]   134  	bis	r31, #<20*8>, r3		; Character timeout 20 characters
                  [0056C0]   135  ;
                  [0056C0]   136  ; Wait for the start bits (sl_rcv bit will go low)		 
                  [0056C0]   137  ;
                  [0056C0]   138  char_start:
                  [0056C0]   139  	hw_mfpr	r0, ev6__i_ctl			; Poll the serial line		 
                  [0056C0]   140          srl     r0, #ev6__i_ctl__sl_rcv__s, r0	;
                  [0056C0]   141  	blbc	r0, start_bit			; until low -> start bit is '0'
                  [0056C0]   142  
                  [0056C0]   143  	PVC_JSR	wait, bsr=1
                  [0056C0]   144  	bsr	r20, waitBitEighth		; Wait for a Eighth bit time	 
                  [0056C0]   145  
                  [0056C0]   146  	subq	r3, 1, r3			; decrement timout
                  [0056C0]   147  	PVC_VIOLATE <1008>			; EJS -- don't follow branch
                  [0056C0]   148  	bne	r3, char_start			; branch until timeout reached
                  [0056C0]   149  	lda	r0, -1(r31)			; Return failure code
                  [0056C0]   150  
                  [0056C0]   151  	PVC_VIOLATE <29>
                  [0056C0]   152  	PVC_JSR	getchar, bsr=1, dest=1
                  [0056C0]   153  	ret	r31, (p7)			; return to caller		 
                  [0056C0]   154  
                  [0056C0]   155  start_bit:
                  [0056C0]   156  	PVC_JSR	wait, bsr=1
                  [0056C0]   157  	bsr	r20, waitBitHalf		; Wait for a half bit time	 
                  [0056C0]   158  
                  [0056C0]   159  get_bits:					; DO				 
                  [0056C0]   160  	PVC_JSR wait, bsr=1
                  [0056C0]   161  	bsr	r20, waitBitTime		; : wait for one bit time	 
                  [0056C0]   162  
                  [0056C0]   163  	hw_mfpr	r0, ev6__i_ctl			; : Get the current data bit.	 
                  [0056C0]   164  	srl 	r0, #ev6__i_ctl__sl_rcv__s, r0	; : r0<0> <- current data bit	 
                  [0056C0]   165          and     r0, #1, r0			; :
                  [0056C0]   166  	sll	r0, r2, r0			; : r0<r2> <- current data bit  
                  [0056C0]   167  	bis	r0, r2, r2			; : r2 <- r2 .bit_or. r0	 
                  [0056C0]   168  	lda	r2, 1(r2)			; : Increment bit countr.	 
                  [0056C0]   169  	and	r2, #^xFF, r0			; : Ignore character in comp.	 
                  [0056C0]   170  	cmpult	r0, #16, r1			; : Do we have a byte now?
                  [0056C0]   171  	PVC_VIOLATE <1008>			; EJS -- don't follow branch
                  [0056C0]   172  	bne	r1, get_bits			; WHILE bit count .NE. 8	 
                  [0056C0]   173  
                  [0056C0]   174  	PVC_JSR wait, bsr=1
                  [0056C0]   175  	bsr	r20, waitBitTime		; Wait for the middle of the 	 
                  [0056C0]   176  						; stop bit.
                  [0056C0]   177  	PVC_JSR	key, bsr=1
                  [0056C0]   178  	bsr	r20, keypressed			; Clear serial line interrupts	 
                  [0056C0]   179  
                  [0056C0]   180  	extbl	r2, #1, r0			; Place character in R0.	 
                  [0056C0]   181  	srl	r24, #mc_v_echo, r1		; IF echo_flag set		 
                  [0056C0]   182  	blbc	r1, exit_getchar		; THEN				 
                  [0056C0]   183  	xor	r0, #ascii_X, r1		; : IF user sent 'X'		 
                  [0056C0]   184  	bne	r1, exit_getchar		; : THEN			 
                  [0056C0]   185  	lda	r1, mc_m_echo(r31)
                  [0056C0]   186  	bic	r24, r1, r24			; : : clear the echo flag	 
                  [0056C0]   187  						; : ENDIF			 
                  [0056C0]   188  exit_getchar:					; ENDIF			 
                  [0056C0]   189  	PVC_VIOLATE <29>
                  [0056C0]   190  	PVC_JSR	getchar, bsr=1, dest=1
                  [0056C0]   191  	ret	r31, (p7)			; return to caller		 
                  [0056C0]   192  
                  [0056C0]   193  
                  [0056C0]   194  ; ======================================================================
                  [0056C0]   195  ; = putChar - routine to send a character over the serial line		=
                  [0056C0]   196  ; ======================================================================
                  [0056C0]   197  ; OVERVIEW:
                  [0056C0]   198  ;  	This routine is used to transmit a character over the serial line.  
                  [0056C0]   199  ; 	First a start bit of '0' is sent.  This is followed by eight data 
                  [0056C0]   200  ;       bits.  The data bits are passed to the routine through a gpr.  The 
                  [0056C0]   201  ; 	data is transmitted one bit at a time and the gpr is shifted once 
                  [0056C0]   202  ;       to the right after each bit.  After the last data bit is transmitted
                  [0056C0]   203  ;       a stop bit of '1' is added to the end of the character.  Extra
                  [0056C0]   204  ;      stop bits are added to make sure that we don't overflow the
                  [0056C0]   205  ;      receiving terminal's buffer. 
                  [0056C0]   206  ;       We make sure that the transmit is initially high so that the
                  [0056C0]   207  ;       receiver can detect the start bit.
                  [0056C0]   208  ;
                  [0056C0]   209  ; FORM OF CALL:
                  [0056C0]   210  ;       R17	<- the character to be sent. 
                  [0056C0]   211  ;       bsr	p7, putChar
                  [0056C0]   212  ;       
                  [0056C0]   213  ; RETURNS:
                  [0056C0]   214  ;      none
                  [0056C0]   215  ;       
                  [0056C0]   216  ; ARGUMENTS:
                  [0056C0]   217  ;       R17 - the character which is to be sent to the SROM port.
                  [0056C0]   218  ;
                  [0056C0]   219  ; REGISTERS:
                  [0056C0]   220  ;	r1  - scratch
                  [0056C0]   221  ;       r2  - scratch, bit count
                  [0056C0]   222  ;       r3  - scratch, I_CTL value
                  [0056C0]   223  ;       r17 - character to output through the SROM port
                  [0056C0]   224  ;       r20 - return address for the call to waitBitTime()
                  [0056C0]   225  ;
                  [0056C0]   226   
                  [0056C0]   227  putChar:
                  [0056C0]   228  	srl	r24, #mc_v_echo, r2		; IF echo flag is clear THEN	 
                  [0056C0]   229  	blbc	r2, exit_putChar		; Output is disabled, exit	 
                  [0056C0]   230  ;
                  [0056C0]   231  ; Initialize routine variables	 
                  [0056C0]   232  ;
                  [0056C0]   233  	lda	r2, 16(r31)			; 1 high + 1 start + 8 data + 	 
                  [0056C0]   234  						; 6 stop (5 extra for delay).   
                  [0056C0]   235  	lda	r17, ^x3F00(r17)		; add stop bits at the end and	 
                  [0056C0]   236  	s4addq	r17, #1, r17			; then add start and high bit	 
                  [0056C0]   237  
                  [0056C0]   238  data_bit:					; REPEAT			
                  [0056C0]   239  	hw_mfpr	r0, ev6__i_ctl			; get current I_CTL value	
                  [0056C0]   240  	lda	r1, 1(r31)			; r1 = mask for sl_xmit bit	
                  [0056C0]   241  	sll	r1, #ev6__i_ctl__sl_xmit__s, r1 ; move to correct position 
                  [0056C0]   242  	bic	r0, r1, r0			; clear sl_xmit bit in old I_CTL value 
                  [0056C0]   243  	blbc	r17, send_bit			; check the new sl_xmit bit	
                  [0056C0]   244  	bis	r0, r1, r0			; set sl_xmit bit in old I_CTL value 
                  [0056C0]   245  send_bit:					; continue			
                  [0056C0]   246  	hw_mtpr	r0, ev6__i_ctl			; EV6 Send the data bit.	
                  [0056C0]   247  
                  [0056C0]   248  	srl	r17, #1, r17			; Shift right, to the next bit. 
                  [0056C0]   249  	subq	r2, #1, r2			; Decrement the bit count.
                  [0056C0]   250  
                  [0056C0]   251  	PVC_JSR	wait, bsr=1
                  [0056C0]   252  	bsr	r20, waitBitTime		; wait for a bit time	   	 
                  [0056C0]   253  
                  [0056C0]   254  	PVC_VIOLATE <1008>			; EJS -- don't follow branch
                  [0056C0]   255  	bne	r2, data_bit			; UNTIL all data sent		 
                  [0056C0]   256  
                  [0056C0]   257  exit_putChar:
                  [0056C0]   258  	PVC_JSR	putchar, bsr=1, dest=1
                  [0056C0]   259  	PVC_VIOLATE <29>
                  [0056C0]   260  	ret	r31, (p7)			; return to caller		 
                  [0056C0]   261  
                  [0056C0]   262  
                  [0056C0]   263  ; ======================================================================
                  [0056C0]   264  ; = waitBitTime - (waitBitHalf) - wait a bit time (wait 0.5 bit-time)	=
                  [0056C0]   265  ; ======================================================================
                  [0056C0]   266  ;
                  [0056C0]   267  ; OVERVIEW:
                  [0056C0]   268  ;       Waits a bit-time or half-bit time, depending on the entry point.
                  [0056C0]   269  ;
                  [0056C0]   270  ; FORM OF CALL:
                  [0056C0]   271  ;       bsr r20, waitBittime
                  [0056C0]   272  ;       bsr r20, waitBithalf
                  [0056C0]   273  ;       
                  [0056C0]   274  ; RETURNS:
                  [0056C0]   275  ;       none
                  [0056C0]   276  ;
                  [0056C0]   277  ; ARGUMENTS:
                  [0056C0]   278  ;       R24	- Upper 32 bits contain CPU cycles per bit.
                  [0056C0]   279  ;
                  [0056C0]   280  ; REGISTERS:
                  [0056C0]   281  ;       R0	- CPU cycle counts per bit
                  [0056C0]   282  ;       R1	- scratch
                  [0056C0]   283  ;
                  [0056C0]   284   
                  [0056C0]   285  waitBitTime:
                  [0056C0]   286  	srl	r24, #32, r0			; Get the timing info.		 
                  [0056C0]   287  	br	r31, waitBitCont
                  [0056C0]   288  waitBitHalf:
                  [0056C0]   289  	srl	r24, #<32+1>, r0		; Divide timing info by 2.	 
                  [0056C0]   290  	br	r31, waitBitCont
                  [0056C0]   291  waitBitQuarter:
                  [0056C0]   292  	srl	r24, #<32+2>, r0		; Divide timing info by 4.	 
                  [0056C0]   293  	br	r31, waitBitCont
                  [0056C0]   294  waitBitEighth:
                  [0056C0]   295  	srl	r24, #<32+3>, r0		; Divide timing info by 8.
                  [0056C0]   296  waitBitCont:
                  [0056C0]   297  
                  [0056C0]   298  wait_init:
                  [0056C0]   299  	lda	r1, 1(r31)			;  				 
                  [0056C0]   300  	sll	r1, #ev6__cc_ctl__cc_ena__s, r1	; Move the cc_ena bit into correct position
                  [0056C0]   301  	hw_mtpr	r1, ev6__cc_ctl			; clear and enable cycle counter
                  [0056C0]   302  	addq	r31, r31, r31			; nop
                  [0056C0]   303  	addq	r31, r31, r31			; nop
                  [0056C0]   304  	addq	r31, r31, r31			; nop
                  [0056C0]   305          hw_mtpr r31, <ev6__mm_stat ! 32> 	; dummy IPR write
                  [0056C0]   306  						;   sets SCBD bit 5
                  [0056C0]   307  						;   (to stall untill cc_ctl gets written)
                  [0056C0]   308  
                  [0056C0]   309  wait:						; REPEAT 			 
                  [0056C0]   310  	rpcc	r1				; : read the cycle count 	 
                  [0056C0]   311  	zapnot	r1, #^x0f, r1			; : clear the high longword 	 
                  [0056C0]   312  	cmplt	r0, r1, r1			; :  				 
                  [0056C0]   313  	PVC_VIOLATE <1008>			; EJS -- don't take branch
                  [0056C0]   314  	beq	r1, wait			; UNTIL we have waited time 	 
                  [0056C0]   315  						; specified	
                  [0056C0]   316  	PVC_VIOLATE <29>
                  [0056C0]   317  	PVC_JSR wait, bsr=1, dest=1
                  [0056C0]   318  	ret	r31, (r20)			; RETURN 			 
                  [0056C0]   319  
                  [0056C0]   320  
                  [0056C0]   321  
                  [0056C0]   322  ; ======================================================================
                  [0056C0]   323  ; = autobaud_sync -- routine used for synchronizing with the serial line=
                  [0056C0]   324  ; ======================================================================
                  [0056C0]   325  ; OVERVIEW:
                  [0056C0]   326  ;       The serial line is polled until the a start bit is seen.  We then
                  [0056C0]   327  ;       time from then until the stop bit is detected.  This happens when
                  [0056C0]   328  ;       the line goes high and stays high for longer than 8 times the 
                  [0056C0]   329  ;       previous time.
                  [0056C0]   330  ;
                  [0056C0]   331  ;      1->0  - is the start bit
                  [0056C0]   332  ;      0->1  - is bit 0 of "55"h
                  [0056C0]   333  ;      1->0  - is bit 1 of "55"h
                  [0056C0]   334  ;      0->1  - is bit 2 of "55"h
                  [0056C0]   335  ;      1->0  - is bit 3 of "55"h
                  [0056C0]   336  ;      0->1  - is bit 4 of "55"h
                  [0056C0]   337  ;      1->0  - is bit 5 of "55"h
                  [0056C0]   338  ;      0->1  - is bit 6 of "55"h
                  [0056C0]   339  ;      1->0  - is bit 7 of "55"h
                  [0056C0]   340  ;      0->1  - is the stop bit
                  [0056C0]   341  ;  
                  [0056C0]   342  ; FORM OF CALL:
                  [0056C0]   343  ;       bsr p7, autobaud_sync
                  [0056C0]   344  ;
                  [0056C0]   345  ; REGISTERS:
                  [0056C0]   346  ;       R0:R2 - Scratch.
                  [0056C0]   347  ;
                  [0056C0]   348  ; RETURNS:	
                  [0056C0]   349  ;       R24  - Timing info for using srom port is saved here.
                  [0056C0]   350  ;
                  [0056C0]   351   
                  [0056C0]   352  autobaud_sync:
                  [0056C0]   353  	lda	r1, 1(r31)			; r1 <- cc_ctl enable bit 	 
                  [0056C0]   354  	sll	r1, #ev6__cc_ctl__cc_ena__s, r1	; Move the cc_ena bit into correct position
                  [0056C0]   355  
                  [0056C0]   356  	PVC_JSR	key, bsr=1
                  [0056C0]   357  	bsr	r20, keypressed			; Clear serial line interrupts	 
                  [0056C0]   358  ;
                  [0056C0]   359  ; Wait for the start bit. Line will transition from high to low 
                  [0056C0]   360  ;
                  [0056C0]   361  poll_start:					; DO 				 
                  [0056C0]   362  	hw_mfpr	r0, ev6__i_ctl			; : r0 <- sl_rcv 		 
                  [0056C0]   363  	srl 	r0, #ev6__i_ctl__sl_rcv__s, r0	; : r0<0> <- current data bit	 
                  [0056C0]   364  	PVC_VIOLATE <1008>			; EJS -- do not follow branch
                  [0056C0]   365      	blbs	r0, poll_start			; WHILE sl_rcv remains high
                  [0056C0]   366  	hw_mtpr	r1, ev6__cc_ctl			; Enable/clear the cycle counter.  
                  [0056C0]   367  ;
                  [0056C0]   368  ; Wait for a low to high transition (or the stop bit)  
                  [0056C0]   369  ;
                  [0056C0]   370  poll_h:                   			; : REPEAT 			 
                  [0056C0]   371  	hw_mfpr	r0, ev6__i_ctl			; : r0 <- sl_rcv 		 
                  [0056C0]   372  	srl 	r0, #ev6__i_ctl__sl_rcv__s, r0	; : r0<0> <- current data bit
                  [0056C0]   373  	PVC_VIOLATE <1008>			; EJS -- do not follow branch	 
                  [0056C0]   374          blbc	r0, poll_h			; : UNTIL sl_rcv goes HI 	 
                  [0056C0]   375  
                  [0056C0]   376  	rpcc	r1				; Record low-to-hi transition.  
                  [0056C0]   377  	zap	r1, #^xF0, r1			; blow off the high longword	 
                  [0056C0]   378  ;	
                  [0056C0]   379  ; Wait for a high to low transition or time out  
                  [0056C0]   380  ;
                  [0056C0]   381  poll_l:						; : REPEAT 			 
                  [0056C0]   382  	rpcc	r0
                  [0056C0]   383  	zap	r0, #^xF0, r0			; blow off the high longword	 
                  [0056C0]   384  	sll	r1, #3, r2			; 8 times low-to-high time.	 
                  [0056C0]   385  	cmpult  r2, r0, r0			; Have reached stop bit?	 
                  [0056C0]   386  	bne	r0, end_sync
                  [0056C0]   387  	hw_mfpr	r0, ev6__i_ctl			; : r0 <- sl_rcv 		 
                  [0056C0]   388  	srl 	r0, #ev6__i_ctl__sl_rcv__s, r0	; : r0<0> <- current data bit
                  [0056C0]   389  	PVC_VIOLATE <1008>			; EJS -- do not follow branch	 
                  [0056C0]   390          blbs	r0, poll_l			; : UNTIL sl_rcv goes LO 	
                  [0056C0]   391  	PVC_VIOLATE <1008> 
                  [0056C0]   392  	br	r31, poll_h			; Wait for next low-to-hi trans
                  [0056C0]   393  
                  [0056C0]   394  end_sync:
                  [0056C0]   395  	lda	r0, 0(r31)			; Divide total cycle count (r1) 
                  [0056C0]   396  simple_div:
                  [0056C0]   397  	mulq	r0, #9, r2			; by 9 (8 data + 1 start bit)	 
                  [0056C0]   398  	cmpult	r2, r1, r2			; This is a simple divide.
                  [0056C0]   399  	beq	r2, set_baud			; R0 = R1/9
                  [0056C0]   400  	addq	r0, #1, r0
                  [0056C0]   401  	br	r31, simple_div
                  [0056C0]   402  
                  [0056C0]   403  set_baud:
                  [0056C0]   404  	sll	r0,  #32, r0			; move to hi longword 		 
                  [0056C0]   405  	lda	r24, mc_m_echo(r0)		; r24 <- cycles-per-bit  	 
                  [0056C0]   406  
                  [0056C0]   407  	PVC_JSR	auto, bsr=1, dest=1
                  [0056C0]   408  	PVC_VIOLATE <29>
                  [0056C0]   409  	ret	r31, (p7)
                  [0056C0]   410  
                  [0056C0]   411  .endm	SROM_IO_FUNCTIONS
File: ev6_osf_system_pal.mar
                  [0056C0]     1  ;+
                  [0056C0]     2  ; ev6_osf_system_pal.mar
                  [0056C0]     3  ;-
                  [0056C0]     4  
                  [0056C0]     5  ;+
                  [0056C0]     6  ; Last Edit:	09-Apr-99
                  [0056C0]     7  ;-
                  [0056C0]     8  	GOTO_FREE_CODE
File: ev6_pal_macros.mar
                  [0056C0]    67M     .align 6
File: ev6_osf_system_pal.mar
                  [0056C0]     9  
                  [0056C0]    10  ;+
                  [0056C0]    11  ; sys__cflush
                  [0056C0]    12  ;
                  [0056C0]    13  ; Entry:
                  [0056C0]    14  ;	r16	page frame number (PFN) of page to be flushed
                  [0056C0]    15  ;	p23	pc of instruction following call_pal instruction
                  [0056C0]    16  ;
                  [0056C0]    17  ; Function:
                  [0056C0]    18  ;	Flush all dstream caches of 1 entire page.
                  [0056C0]    19  ;
                  [0056C0]    20  ; Note on implementation:
                  [0056C0]    21  ;	The dcache is a 64K byte, two-way set associative,
                  [0056C0]    22  ;	virtually indexed, physically tagged, 64-byte block cache.
                  [0056C0]    23  ;	With 32K bytes of data per set, that means that EV6
                  [0056C0]    24  ;	requires 2 additional bits of virtual address beyond the
                  [0056C0]    25  ;	bits which specify an 8K byte page in order to specify a
                  [0056C0]    26  ;	dcache row index. Conceptually, a given virtual address
                  [0056C0]    27  ;	may be found in 4 distinct places in the cache.
                  [0056C0]    28  ;
                  [0056C0]    29  ;	We need to do 2 loads per block because the dcache is
                  [0056C0]    30  ;	2-way set associative. And that needs to be multiplied
                  [0056C0]    31  ;	by 4 because given a PA, bits <14:13> need to be
                  [0056C0]    32  ;	toggled through the 4 combinations to make sure all
                  [0056C0]    33  ;	4 synonym locations are checked.
                  [0056C0]    34  ;
                  [0056C0]    35  ; 	We of course also have to worry about flushing the bcache,
                  [0056C0]    36  ;	so we need to toggle tag bits greater than the bcache size.
                  [0056C0]    37  ;	So we strip the high bits of the PFN so that we can an
                  [0056C0]    38  ;	address between 0 and four times the size of the bcache.
                  [0056C0]    39  ;	We then toggle tag bits to get two addresses and run
                  [0056C0]    40  ;	through the 4 combinations.
                  [0056C0]    41  ;-
                  [0056C0]    42  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
                  [0056C0]   275i 	.align 6
File: ev6_osf_system_pal.mar
                  [0056C0]    43  sys__cflush:
                  [0056C0]    44  .if ne reference_platform
                  [0056C0]    45  ;
                  [0056C0]    46  ; We assume a bcache no larger than 4 MB = 2**22.
                  [0056C0]    47  ;
                  [0056C0]    48  bcache_size = 22
                  [0056C0]    49  
                  [0056C0]    50  	sll     r16, #page_offset_size_bits+<64-<bcache_size+2>>, p4
                  [0056C0]    51  	srl     p4, #64-<bcache_size+2>, p4		; shift into position
                  [0056C0]    52  	ldah    p5, 1@<bcache_size-16>(r31)		; get 1st toggle bit
                  [0056C0]    53  	ldah    p6, 2@<bcache_size-16>(r31)		; get 2nd toggle bit
                  [0056C0]    54  	xor     p4, p5, p5				; xor to get 1st addr
                  [0056C0]    55  	xor	p4, p6, p6				; xor to get 2nd addr
                  [0056C0]    56  
                  [0056C0]    57  	bis	r31, #<8192>/<64*8>, p7			; count of loads
                  [0056C0]    58  
                  [0056C0]    59  sys__cflush_outer_loop:
                  [0056C0]    60  	subq	p7, #1, p7				; decrement counter
                  [0056C0]    61  	bis	r31, #3, p4				; <14:13> bits
                  [0056C0]    62  
                  [0056C0]    63  sys__cflush_inner_loop:
                  [0056C0]    64  	sll	p4, #13, p4				; shift <14:13> up
                  [0056C0]    65  	bis	p5, p4, p5				; or in <14:13>
                  [0056C0]    66  	bis	p6, p4, p6				; or in <14:13>
                  [0056C0]    67  	hw_mfpr	p20, EV6__ISUM				; get isum
                  [0056C0]    68  
                  [0056C0]    69  	hw_ldq/p r31, 64*0(p5)				; first set
                  [0056C0]    70  	hw_ldq/p r31, 64*0(p6)				; second set
                  [0056C0]    71  	
                  [0056C0]    72  	hw_ldq/p r31, 64*1(p5)				; first set
                  [0056C0]    73  	hw_ldq/p r31, 64*1(p6)				; second set
                  [0056C0]    74  
                  [0056C0]    75  	hw_ldq/p r31, 64*2(p5)				; first set
                  [0056C0]    76  	hw_ldq/p r31, 64*2(p6)				; second set
                  [0056C0]    77  
                  [0056C0]    78  	hw_ldq/p r31, 64*3(p5)				; first set
                  [0056C0]    79  	hw_ldq/p r31, 64*3(p6)				; second set
                  [0056C0]    80  
                  [0056C0]    81  	hw_ldq/p r31, 64*4(p5)				; first set
                  [0056C0]    82  	hw_ldq/p r31, 64*4(p6)				; second set
                  [0056C0]    83  	
                  [0056C0]    84  	hw_ldq/p r31, 64*5(p5)				; first set
                  [0056C0]    85  	hw_ldq/p r31, 64*5(p6)				; second set
                  [0056C0]    86  	
                  [0056C0]    87  	hw_ldq/p r31, 64*6(p5)				; first set
                  [0056C0]    88  	hw_ldq/p r31, 64*6(p6)				; second set
                  [0056C0]    89  	
                  [0056C0]    90  	hw_ldq/p r31, 64*7(p5)				; first set
                  [0056C0]    91  	hw_ldq/p r31, 64*7(p6)				; second set
                  [0056C0]    92  
                  [0056C0]    93  	xor	p5, p4, p5				; zap <14:13>
                  [0056C0]    94  	xor	p6, p4, p6				; zap <14:13>
                  [0056C0]    95  	srl	p4, #13, p4				; shift <14:13> down
                  [0056C0]    96  	subq	p4, #1, p4				; decrement inner loop
                  [0056C0]    97  	bne	p20, sys__cflush_interrupt		; need to take interrupt
                  [0056C0]    98  	blt	p4, sys__cflush_do_outer		; branch for next block
                  [0056C0]    99  	br	r31, sys__cflush_inner_loop		; next combination
                  [0056C0]   100  
                  [0056C0]   101  sys__cflush_do_outer:
                  [0056C0]   102  	beq	p7, sys__cflush_done			; branch if done
                  [0056C0]   103  	lda	p5, <64*8>(p5)				; next block
                  [0056C0]   104  	lda	p6, <64*8>(p6)				; next block
                  [0056C0]   105  	br	r31, sys__cflush_outer_loop		; next group
                  [0056C0]   106  
                  [0056C0]   107  sys__cflush_done:
                  [0056C0]   108  	hw_ret	(p23)					; return to user
                  [0056C0]   109  
                  [0056C0]   110  
                  [0056C0]   111  sys__cflush_interrupt:
                  [0056C0]   112  	subq	p23, #4, p23				; back up pc
                  [0056C0]   113  	hw_ret	(p23)					; take interrupt
                  [0056C0]   114  
                  [0056C0]   115  .iff					; if ne reference_platform
                  [0056C0]   116  
                  [0056C0]   117  	hw_ret	(p23)
                  [0056C0]   118  
                  [0056C0]   119  .endc					; if ne reference_platform
                  [0056C0]    45I ;
                  [0056C0]    46I ; We assume a bcache no larger than 4 MB = 2**22.
                  [0056C0]    47I ;
                  [0056C0]    48I bcache_size = 22
                  [0056C0]    49I 
         4A06B724 [0056C0]    50I 	sll     r16, #page_offset_size_bits+<64-<bcache_size+2>>, p4
         48851684 [0056C4]    51I 	srl     p4, #64-<bcache_size+2>, p4		; shift into position
         24BF0040 [0056C8]    52I 	ldah    p5, 1@<bcache_size-16>(r31)		; get 1st toggle bit
         24DF0080 [0056CC]    53I 	ldah    p6, 2@<bcache_size-16>(r31)		; get 2nd toggle bit
         44850805 [0056D0]    54I 	xor     p4, p5, p5				; xor to get 1st addr
         44860806 [0056D4]    55I 	xor	p4, p6, p6				; xor to get 2nd addr
                  [0056D8]    56I 
         47E21407 [0056D8]    57I 	bis	r31, #<8192>/<64*8>, p7			; count of loads
                  [0056DC]    58I 
                  [0056DC]    59I sys__cflush_outer_loop:
         40E03527 [0056DC]    60I 	subq	p7, #1, p7				; decrement counter
         47E07404 [0056E0]    61I 	bis	r31, #3, p4				; <14:13> bits
                  [0056E4]    62I 
                  [0056E4]    63I sys__cflush_inner_loop:
         4881B724 [0056E4]    64I 	sll	p4, #13, p4				; shift <14:13> up
         44A40405 [0056E8]    65I 	bis	p5, p4, p5				; or in <14:13>
         44C40406 [0056EC]    66I 	bis	p6, p4, p6				; or in <14:13>
         669F0D00 [0056F0]    67I 	hw_mfpr	p20, EV6__ISUM				; get isum
                  [0056F4]    68I 
         6FE51000 [0056F4]    69I 	hw_ldq/p r31, 64*0(p5)				; first set
         6FE61000 [0056F8]    70I 	hw_ldq/p r31, 64*0(p6)				; second set
                  [0056FC]    71I 	
         6FE51040 [0056FC]    72I 	hw_ldq/p r31, 64*1(p5)				; first set
         6FE61040 [005700]    73I 	hw_ldq/p r31, 64*1(p6)				; second set
                  [005704]    74I 
         6FE51080 [005704]    75I 	hw_ldq/p r31, 64*2(p5)				; first set
         6FE61080 [005708]    76I 	hw_ldq/p r31, 64*2(p6)				; second set
                  [00570C]    77I 
         6FE510C0 [00570C]    78I 	hw_ldq/p r31, 64*3(p5)				; first set
         6FE610C0 [005710]    79I 	hw_ldq/p r31, 64*3(p6)				; second set
                  [005714]    80I 
         6FE51100 [005714]    81I 	hw_ldq/p r31, 64*4(p5)				; first set
         6FE61100 [005718]    82I 	hw_ldq/p r31, 64*4(p6)				; second set
                  [00571C]    83I 	
         6FE51140 [00571C]    84I 	hw_ldq/p r31, 64*5(p5)				; first set
         6FE61140 [005720]    85I 	hw_ldq/p r31, 64*5(p6)				; second set
                  [005724]    86I 	
         6FE51180 [005724]    87I 	hw_ldq/p r31, 64*6(p5)				; first set
         6FE61180 [005728]    88I 	hw_ldq/p r31, 64*6(p6)				; second set
                  [00572C]    89I 	
         6FE511C0 [00572C]    90I 	hw_ldq/p r31, 64*7(p5)				; first set
         6FE611C0 [005730]    91I 	hw_ldq/p r31, 64*7(p6)				; second set
                  [005734]    92I 
         44A40805 [005734]    93I 	xor	p5, p4, p5				; zap <14:13>
         44C40806 [005738]    94I 	xor	p6, p4, p6				; zap <14:13>
         4881B684 [00573C]    95I 	srl	p4, #13, p4				; shift <14:13> down
         40803524 [005740]    96I 	subq	p4, #1, p4				; decrement inner loop
         F6800007 [005744]    97I 	bne	p20, sys__cflush_interrupt		; need to take interrupt
         E8800001 [005748]    98I 	blt	p4, sys__cflush_do_outer		; branch for next block
         C3FFFFE5 [00574C]    99I 	br	r31, sys__cflush_inner_loop		; next combination
                  [005750]   100I 
                  [005750]   101I sys__cflush_do_outer:
         E4E00003 [005750]   102I 	beq	p7, sys__cflush_done			; branch if done
         20A50200 [005754]   103I 	lda	p5, <64*8>(p5)				; next block
         20C60200 [005758]   104I 	lda	p6, <64*8>(p6)				; next block
         C3FFFFDF [00575C]   105I 	br	r31, sys__cflush_outer_loop		; next group
                  [005760]   106I 
                  [005760]   107I sys__cflush_done:
         7BF78000 [005760]   108I 	hw_ret	(p23)					; return to user
                  [005764]   109I 
                  [005764]   110I 
                  [005764]   111I sys__cflush_interrupt:
         42E09537 [005764]   112I 	subq	p23, #4, p23				; back up pc
         7BF78000 [005768]   113I 	hw_ret	(p23)					; take interrupt
                  [00576C]   114I 
                  [00576C]   120  
                  [00576C]   121  
                  [00576C]   122  ;+
                  [00576C]   123  ; sys__wripir
                  [00576C]   124  ;
                  [00576C]   125  ; Entry:
                  [00576C]   126  ;	r16(a0)	processor number
                  [00576C]   127  ;	p23	pc of instruction following call_pal instruction
                  [00576C]   128  ; Function:
                  [00576C]   129  ;	Request an interprocessor interrupt.
                  [00576C]   130  ;-
                  [00576C]   131  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [00576C]   275i 	.align 6
00000000 00000000 [005774]
         00000000 [00577C]
File: ev6_osf_system_pal.mar
                  [005780]   132  sys__wripir:
                  [005780]   133  	NOP
File: ev6_pal_macros.mar
         47FF041F [005780]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [005784]   134  	NOP
File: ev6_pal_macros.mar
         47FF041F [005784]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [005788]   135  	NOP
File: ev6_pal_macros.mar
         47FF041F [005788]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [00578C]   136  	NOP
File: ev6_pal_macros.mar
         47FF041F [00578C]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [005790]   137  
                  [005790]   138      .if eq force_path				; 1.41
                  [005790]   139  	hw_ret	(p23)				; return
                  [005790]   140      .iff
                  [005790]   141  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align
                  [005790]   142  	PVC_VIOLATE <1007>
                  [005790]   143  	PVC_VIOLATE <1020>			; stop permutation
                  [005790]   144  	hw_jmp	(p23)				; return with jmp
                  [005790]   145  	br	r31, .-4			; stop predictor
                  [005790]   146      .endc					; 1.41
         7BF78000 [005790]   139I 	hw_ret	(p23)				; return
                  [005794]   147      
                  [005794]   148  ;+
                  [005794]   149  ; sys__wtint
                  [005794]   150  ;
                  [005794]   151  ; Entry:
                  [005794]   152  ;	Entered from call_pal__wrint
                  [005794]   153  ;
                  [005794]   154  ; Function:
                  [005794]   155  ;	The wait for interrupt instruction requests that, if possible, the
                  [005794]   156  ;	PALcode wait for the first of either of the following conditions
                  [005794]   157  ;	before returning:
                  [005794]   158  ;		any interrupt other than a clock tick
                  [005794]   159  ;		the first clock tick after the specified number
                  [005794]   160  ;
                  [005794]   161  ; Current state:
                  [005794]   162  ;	p23		pc of instruction following the call_pal instruction
                  [005794]   163  ;	r16(a0)		maximum nmber of interval clock ticks to skip
                  [005794]   164  ;
                  [005794]   165  ; Exit state:
                  [005794]   166  ;	r0(v0)		number of interval clock ticks actually skipped
                  [005794]   167  ;
                  [005794]   168  ;-
                  [005794]   169  
                  [005794]   170  .if ne reference_platform
                  [005794]   171  
                  [005794]   172  IRQ_IP 	= 8				; position within EV6__ISUM__IE field
                  [005794]   173  IRQ_CLK = 4
                  [005794]   174  IRQ_DEV	= 2
                  [005794]   175  IRQ_ERR = 1
                  [005794]   176  
                  [005794]   177  IRQ_NOCLK = <IRQ_IP ! IRQ_DEV ! IRQ_ERR>	; checked during cache sweep
                  [005794]   178  
                  [005794]   179  sys__wtint:
                  [005794]   180  
                  [005794]   181  ;
                  [005794]   182  ; First, check for 0 ticks.
                  [005794]   183  ;
                  [005794]   184  	beq	r16, sys__wtint_noticks
                  [005794]   185  ;
                  [005794]   186  ; Now save state.
                  [005794]   187  ;
                  [005794]   188  	PVC_JSR	save_state, bsr=1
                  [005794]   189  	bsr	p7, pal__save_state		; save state
                  [005794]   190  ;
                  [005794]   191  ; Now enable device interrupts, so we can detect them.
                  [005794]   192  ;
                  [005794]   193  	bis	r31, #<IRQ_NOCLK>, p4		; platform IRQ mask minus CLK
                  [005794]   194  	sll	p4, #EV6__IER__EIEN__S, p4	; shift into place
                  [005794]   195  	hw_mtpr	p4, EV6__IER			; (4,0L) write new ier
                  [005794]   196  	bis	r31, r31, r31
                  [005794]   197  ;
                  [005794]   198  ; Now save what cpu we are.
                  [005794]   199  ;
                  [005794]   200  	hw_ldq/p p6, PT__WHAMI(p_temp)		; get my cpu number
                  [005794]   201  	sll	p6, #EV6__SIRR__SIR__S, p6	; cpu number into place
                  [005794]   202  	hw_mtpr	p6, EV6__SIRR			; (4,0L) save cpu number
                  [005794]   203  ;
                  [005794]   204  ; Set up 48-bit kseg so we can do ECB's to clean and invalidate
                  [005794]   205  ; the data caches.
                  [005794]   206  ;
                  [005794]   207  	bis	r31, #<4@EV6__M_CTL__SPE__S>, p4
                  [005794]   208  	hw_mtpr	p4, EV6__M_CTL			; (6,0L) write m_ctl
                  [005794]   209  	bis	r31, #<1@EV6__VA_CTL__VA_48__S>, p5
                  [005794]   210  	hw_mtpr	p5, EV6__VA_CTL			; (5,1L)
                  [005794]   211  	bis	r31, r31, r31
                  [005794]   212  	bis	r31, r31, r31
                  [005794]   213  	bis	r31, r31, r31
                  [005794]   214  	hw_mtpr	r31, <EV6__MM_STAT ! ^x70>	; stall till they all retire
                  [005794]   215  ;
                  [005794]   216  ; Determine the bcache size from the transformed write-many chain.
                  [005794]   217  ; The following transformation is done on the write_many value
                  [005794]   218  ; to make the shift-in work easily.
                  [005794]   219  ;
                  [005794]   220  ; 	<35:30>|<29:24>|<23:18>|<17:12>|<11:06>|<05:00> =>
                  [005794]   221  ; 	<05:00>|<11:06>|<17;12>|<23:18>|<29:24>|<35:30>
                  [005794]   222  ;
                  [005794]   223  ; The size is found at <5:2> in the untransformed value,
                  [005794]   224  ; and thus at <35:32> in the transformed value.
                  [005794]   225  ;	0000	1  megabytes
                  [005794]   226  ;	0001	2  megabytes
                  [005794]   227  ;	0011	4  megabytes
                  [005794]   228  ;	0111	8  megabytes
                  [005794]   229  ;	1111	16 megabytes
                  [005794]   230  ;
                  [005794]   231  ; We need to calculate twice the size of the bcache.
                  [005794]   232  ; The write-many chain is stored in CNS__WRITE_MANY.
                  [005794]   233  ; The size is store in chain<35:32>.
                  [005794]   234  ;
                  [005794]   235  	hw_ldq/p p7, PT__IMPURE(p_temp)		; get impure pointer
                  [005794]   236  	hw_ldq/p p20, CNS__WRITE_MANY(p7)	; get write-many chain
                  [005794]   237  	srl	p20, #32, p4			; get size
                  [005794]   238  	and	p4, #^xF, p4			; clean it
                  [005794]   239  	addq	p4, #1, p4			; add 1
                  [005794]   240  	sll	p4, #1, p4			; multiply by 2
                  [005794]   241  ;
                  [005794]   242  ; We will be turning off the bcache, so we will need to zap the write many
                  [005794]   243  ; chain bits for enable and size.
                  [005794]   244  ;
                  [005794]   245  ;                 |3333|3322|2222|2222|1111|1111|11                     
                  [005794]   246  ;                 |5432|1098|7654|3210|9876|5432|1098|7654|3210|
                  [005794]   247  ;                 +====+====+====+====+====+====+====+====+====+
                  [005794]   248  ; BC_ENABLE       |    | 1  |  11|1  1|11  |111 |    |    |    |
                  [005794]   249  ; BC_SIZE1        |   1|  1 |    |    |    |    |    |    |   1|
                  [005794]   250  ; BC_SIZE2        |  1 |   1|    |    |    |    |1   |    |    |
                  [005794]   251  ; BC_SIZE3        | 1  |    |1   |    |    |    | 1  |    |    |
                  [005794]   252  ; BC_SIZE4        |1   |    | 1  |    |    |    |  1 |    |    |
                  [005794]   253  ;                 +====+====+====+====+====+====+====+====+====+
                  [005794]   254  ;                   F    7    F    9    C    E    E    0    1
                  [005794]   255  ;
                  [005794]   256  	GET_32CONS	p6, <^x7F9CEE01>, r31		; get low 32
                  [005794]   257  	bic	p20, p6, p20				; clear bits
                  [005794]   258  	bis	r31, #^xF, p6				; get ^xF
                  [005794]   259  	sll	p6, #32, p6				; shift into position
                  [005794]   260  	bic	p20, p6, p20				; new write many chain
                  [005794]   261  ;
                  [005794]   262  ; Turn off SBE.
                  [005794]   263  ;
                  [005794]   264  ; Current state:
                  [005794]   265  ;	p4	twice the size of the bcache in megabytes
                  [005794]   266  ;	p20	write many chain to turn bcache off
                  [005794]   267  ;
                  [005794]   268  	ALIGN_CACHE_BLOCK <^x47FF041F>	; align with nops
                  [005794]   269  
                  [005794]   270  	mb				; wait for MEM-OP's to complete
                  [005794]   271  	lda     r0, ^x0086(r31)		; load I_CTL.....
                  [005794]   272  	hw_mtpr r0, EV6__I_CTL		; .....SDE=2, IC_EN=3, SBE=0
                  [005794]   273  	br      r0, .			; create dest address
                  [005794]   274  
                  [005794]   275  	addq    r0, #17, r0		; finish computing dest address 
                  [005794]   276  	hw_mtpr r31, EV6__IC_FLUSH	; flush the Icache
                  [005794]   277  	bne     r31, .			; separate retires
                  [005794]   278  	PVC_VIOLATE <1007>
                  [005794]   279  	hw_jmp_stall (r0)		; force flush
                  [005794]   280  
                  [005794]   281  ;
                  [005794]   282  ; NOTE:
                  [005794]   283  ;
                  [005794]   284  ; The rest of the code should be pulled into the icache before we start
                  [005794]   285  ; invalidating the data caches. We do that by jumping through the
                  [005794]   286  ; cache blocks.
                  [005794]   287  ;
                  [005794]   288  
                  [005794]   289  ;
                  [005794]   290  ; Now flush data caches. ECB twice the size of the bcache,
                  [005794]   291  ; i.e, 2 - 32 megabytes. Use a double loop, doing a megabyte at a
                  [005794]   292  ; time and check whether we need to punt periodically.
                  [005794]   293  ;
                  [005794]   294  ; Current state:
                  [005794]   295  ;	p4	twice the size of the cache in megabytes
                  [005794]   296  ;	p20	write many chain to turn bcache off
                  [005794]   297  ;
                  [005794]   298  
                  [005794]   299  	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
                  [005794]   300  
                  [005794]   301  sys__wtint_touch0:
                  [005794]   302  	mb					; (1)
                  [005794]   303  	br	r31, sys__wtint_touch1		; (2)
                  [005794]   304  
                  [005794]   305  sys__wtint_start_flush:
                  [005794]   306  	ldah	p6, ^x8000(r31)			; (3) Kseg = 0xffff8000.00000000
                  [005794]   307  	sll	p6, #16, p6			; (4) shift into place
                  [005794]   308  
                  [005794]   309  sys__wtint_outer_loop:
                  [005794]   310  	hw_mfpr	p7, EV6__ISUM			; (3) get ISUM
                  [005794]   311  
                  [005794]   312  	subq	p4, #1, p4			; (4) decrement outer counter
                  [005794]   313  	lda	p5, ^x4000(r31)			; (5) ^x4000 * 64 = 1mb
                  [005794]   314  
                  [005794]   315  	bne	p7, sys__wtint_punt		; (6) got an interrupt
                  [005794]   316  	br	r31, sys__wtint_inner_loop	; (7) go to inner loop
                  [005794]   317  
                  [005794]   318  sys__wtint_inner_loop:
                  [005794]   319  	subq	p5, #1, p5			; (8) decrement inner counter
                  [005794]   320  	ecb	(p6)				; (9) ecb
                  [005794]   321  	lda	p6, 64(p6)			; (10) next address
                  [005794]   322  	beq	p5, sys__wtint_loop_test	; (11) if done 
                  [005794]   323  	br	r31, sys__wtint_inner_loop	; (12) loop back
                  [005794]   324  
                  [005794]   325  sys__wtint_loop_test:
                  [005794]   326  	beq	p4, sys__wtint_bc_off		; (13) now turn off bcache
                  [005794]   327  	br	r31, sys__wtint_outer_loop	; (14) next megabyte
                  [005794]   328  
                  [005794]   329  ;
                  [005794]   330  ; Now turn the bcache off. We probably don't need to do this as long
                  [005794]   331  ; as we have pulled everything into the icache, but the debug (where we
                  [005794]   332  ; just jump to wakeup) needs it anyway.
                  [005794]   333  ;
                  [005794]   334  ; Current state:
                  [005794]   335  ;	p20	write many chain with bcache off
                  [005794]   336  ;
                  [005794]   337  	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
                  [005794]   338  
                  [005794]   339  sys__wtint_touch1:
                  [005794]   340  	mb					; (1)
                  [005794]   341  	br	r31, sys__wtint_touch2		; (2)
                  [005794]   342  	bis	r31, r31, r31			; (3)
                  [005794]   343  	bis	r31, r31, r31			; (4)				
                  [005794]   344  
                  [005794]   345  sys__wtint_bc_off:
                  [005794]   346  	bis	p20, r31, r2			; (5) move chain to r2
                  [005794]   347  	addq	r31, #6, r0			; (6) shift in 6x 6-bits
                  [005794]   348  sys__wtint_bc_off_loop::
                  [005794]   349  	PVC_VIOLATE<30>				;
                  [005794]   350  	hw_mtpr	r2, EV6__DATA			; (7) (6,0L) shift in 6 bits
                  [005794]   351  	subq	r0, #1, r0			; (8) decrement R0
                  [005794]   352  
                  [005794]   353  	beq	r0, sys__wtint_bc_off_done	; (9) done if R0 is zero
                  [005794]   354  	srl	r2, #6, r2			; (10) align next 6 bits
                  [005794]   355  	br	r31, sys__wtint_bc_off_loop	; (11) continue shifting
                  [005794]   356  sys__wtint_bc_off_done:
                  [005794]   357  	hw_mtpr	r31, <EV6__MM_STAT ! ^x40>	; (12) IPR write - sets SCBD 6
                  [005794]   358  
                  [005794]   359  	hw_mtpr	r31, <EV6__MM_STAT ! ^x40>	; (13) stalls until write retires
                  [005794]   360  	beq	r31, sys__wtint_clocks		; (14) predicts fall thru
                  [005794]   361  	PVC_VIOLATE <1006>
                  [005794]   362  	br	r31, .-4			; (15) predict infinite loop
                  [005794]   363  	addq	r31, r31, r2			; (16) nop
                  [005794]   364  ;
                  [005794]   365  ; Bcache should now be off.
                  [005794]   366  ; Now add CLK to interrupts that can wake the CPU.
                  [005794]   367  ;
                  [005794]   368  
                  [005794]   369  IRQ_MASK = ^x0F
                  [005794]   370  
                  [005794]   371  	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
                  [005794]   372  
                  [005794]   373  sys__wtint_touch2:
                  [005794]   374  	mb					; (1)
                  [005794]   375  	br	r31, sys__wtint_touch3		; (2)
                  [005794]   376  
                  [005794]   377  sys__wtint_clocks:
                  [005794]   378  	bis	r31, #<IRQ_MASK>, p4		; (3) platform IRQ mask
                  [005794]   379  	sll	p4, #EV6__IER__EIEN__S, p4	; (4) shift into place
                  [005794]   380  	hw_mtpr	p4, EV6__IER			; (5) (4,0L) write new ier
                  [005794]   381  	br	r31, sys__wtint_addr		; (6) form external address
                  [005794]   382  ;
                  [005794]   383  ; Get address of IICx register and PRBEN register.
                  [005794]   384  ;
                  [005794]   385  ; IICx	cpu 0	380	00 => 0011 1000 0000
                  [005794]   386  ;	cpu 1	3c0	01 => 0011 1100 0000
                  [005794]   387  ;	cpu 2	700	10 => 0111 0000 0000
                  [005794]   388  ;	cpu 3	740	11 => 0111 0100 0000
                  [005794]   389  ;
                  [005794]   390  ;So we start with ^b0011 0000 0000
                  [005794]   391  ;Then OR the whami into <10:9>
                  [005794]   392  ;Then we XOR whami with ^b10 and OR it into <7:6>
                  [005794]   393  ;
                  [005794]   394  	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
                  [005794]   395  
                  [005794]   396  sys__wtint_touch3:
                  [005794]   397  	mb					; (1)
                  [005794]   398  	br	r31, sys__wtint_touch4		; (2)
                  [005794]   399  
                  [005794]   400  sys__wtint_addr:
                  [005794]   401  	lda	p4, ^x801A(r31)			; (3) start to generate csr addr
                  [005794]   402  	zapnot	p4, #3, p4			; (4) zap extension
                  [005794]   403  	sll	p4, #28, p4			; (5) now have 801.A000.0000
                  [005794]   404  	lda	p20, ^x340(p4)			; (6) PRBEN address
                  [005794]   405  
                  [005794]   406  	lda	p4, ^x300(p4)			; (7) now have 801.A000.0300
                  [005794]   407  	hw_ldq/p p5, PT__WHAMI(p_temp)		; (8) get whami
                  [005794]   408  	sll	p5, #9, p6			; (9) move whami to <10:9>
                  [005794]   409  	xor	p5, #^b10, p7			; (10) xor
                  [005794]   410  	sll	p7, #6, p7			; (11) move to <7:6>
                  [005794]   411  
                  [005794]   412  	bis	p4, p6, p4			; (12) OR into <10:9>
                  [005794]   413  	bis	p4, p7, p4			; (13) OR into <7:6> to get IICx
                  [005794]   414  	br	r31, sys__wtint_sleep		; (14)
                  [005794]   415  ;
                  [005794]   416  ; Write the Cchip IIC CSR corresponding to its CPU ID with the
                  [005794]   417  ; number of interval timer interrupts it wishes to ignore.
                  [005794]   418  ; Read PRBEN to turn off probes
                  [005794]   419  ;
                  [005794]   420  ; Current state:
                  [005794]   421  ;	p4	address of IIC CSR for this CPU
                  [005794]   422  ;	p20	address of PRBEN register
                  [005794]   423  ;	r16	number of ticks to skip
                  [005794]   424  ;
                  [005794]   425  	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
                  [005794]   426  
                  [005794]   427  sys__wtint_touch4:
                  [005794]   428  	mb					; (1)
                  [005794]   429  	br	r31, sys__wtint_start_flush	; (2)
                  [005794]   430  
                  [005794]   431  sys__wtint_sleep:
                  [005794]   432  	zapnot	r16, #7, p23			; (3) clean number of ticks
                  [005794]   433  	hw_stq/p p23, (p4)			; (4) store number of ticks
                  [005794]   434  	mb					; (5) force it out
                  [005794]   435  
                  [005794]   436  	hw_mtpr	r31, EV6__SLEEP			; (6) (4-7,0L) prepare to sleep
                  [005794]   437  	bis	r31, r31, r31			; (7)
                  [005794]   438  	bis	r31, r31, r31			; (8)
                  [005794]   439  
                  [005794]   440  	ASSUME_FETCH_BLOCK
                  [005794]   441  
                  [005794]   442  	hw_mtpr	r31, <EV6__MM_STAT ! ^xF0>	; (9) stall
                  [005794]   443  	hw_ldq/p p5, (p20)			; (10) turn off probes
                  [005794]   444  	bis p5, p5, p6				; (11) consume data
                  [005794]   445  	mb					; (12) do an memory barrier
                  [005794]   446  
                  [005794]   447  	hw_mtpr	31, EV6__SLEEP			; (13) (4-7,0L) now do it
                  [005794]   448  	PVC_VIOLATE <1006>
                  [005794]   449  	br	r31, .-4			; (14) branch to self
                  [005794]   450  ;
                  [005794]   451  ; Got an interrupt while we were flushing the bcache.
                  [005794]   452  ;
                  [005794]   453  	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
                  [005794]   454  
                  [005794]   455  sys__wtint_punt:
                  [005794]   456  	PVC_JSR	restore_state, bsr=1
                  [005794]   457  	bsr	p7, pal__restore_state		; (3) restore state
                  [005794]   458  	br	r31, sys__wtint_noticks		; (4) return
                  [005794]   459  ;
                  [005794]   460  ; Called with skipped ticks = 0. Just return.
                  [005794]   461  ;
                  [005794]   462  sys__wtint_noticks:
                  [005794]   463  	bis	r31, r31, r0			; zero ticks skipped
                  [005794]   464  	hw_ret	(p23)
                  [005794]   465  
                  [005794]   466  .endc
                  [005794]   171I 
                  [005794]   172I IRQ_IP 	= 8				; position within EV6__ISUM__IE field
                  [005794]   173I IRQ_CLK = 4
                  [005794]   174I IRQ_DEV	= 2
                  [005794]   175I IRQ_ERR = 1
                  [005794]   176I 
                  [005794]   177I IRQ_NOCLK = <IRQ_IP ! IRQ_DEV ! IRQ_ERR>	; checked during cache sweep
                  [005794]   178I 
                  [005794]   179I sys__wtint:
                  [005794]   180I 
                  [005794]   181I ;
                  [005794]   182I ; First, check for 0 ticks.
                  [005794]   183I ;
         E600008C [005794]   184I 	beq	r16, sys__wtint_noticks
                  [005798]   185I ;
                  [005798]   186I ; Now save state.
                  [005798]   187I ;
                  [005798]   188I 	PVC_JSR	save_state, bsr=1
File: ev6_pal_macros.mar
                  [005798]   531i  pvc_lbl \pcv_index, \pcv_jsr_save_state0, osf
File: ev6_osf_system_pal.mar
         D0FFFC05 [005798]   189I 	bsr	p7, pal__save_state		; save state
                  [00579C]   190I ;
                  [00579C]   191I ; Now enable device interrupts, so we can detect them.
                  [00579C]   192I ;
         47E17404 [00579C]   193I 	bis	r31, #<IRQ_NOCLK>, p4		; platform IRQ mask minus CLK
         48843724 [0057A0]   194I 	sll	p4, #EV6__IER__EIEN__S, p4	; shift into place
         77E40A10 [0057A4]   195I 	hw_mtpr	p4, EV6__IER			; (4,0L) write new ier
         47FF041F [0057A8]   196I 	bis	r31, r31, r31
                  [0057AC]   197I ;
                  [0057AC]   198I ; Now save what cpu we are.
                  [0057AC]   199I ;
         6CD51098 [0057AC]   200I 	hw_ldq/p p6, PT__WHAMI(p_temp)		; get my cpu number
         48C1D726 [0057B0]   201I 	sll	p6, #EV6__SIRR__SIR__S, p6	; cpu number into place
         77E60C10 [0057B4]   202I 	hw_mtpr	p6, EV6__SIRR			; (4,0L) save cpu number
                  [0057B8]   203I ;
                  [0057B8]   204I ; Set up 48-bit kseg so we can do ECB's to clean and invalidate
                  [0057B8]   205I ; the data caches.
                  [0057B8]   206I ;
         47E11404 [0057B8]   207I 	bis	r31, #<4@EV6__M_CTL__SPE__S>, p4
         77E42840 [0057BC]   208I 	hw_mtpr	p4, EV6__M_CTL			; (6,0L) write m_ctl
         47E05405 [0057C0]   209I 	bis	r31, #<1@EV6__VA_CTL__VA_48__S>, p5
         77E5C420 [0057C4]   210I 	hw_mtpr	p5, EV6__VA_CTL			; (5,1L)
         47FF041F [0057C8]   211I 	bis	r31, r31, r31
         47FF041F [0057CC]   212I 	bis	r31, r31, r31
         47FF041F [0057D0]   213I 	bis	r31, r31, r31
         77FF2770 [0057D4]   214I 	hw_mtpr	r31, <EV6__MM_STAT ! ^x70>	; stall till they all retire
                  [0057D8]   215I ;
                  [0057D8]   216I ; Determine the bcache size from the transformed write-many chain.
                  [0057D8]   217I ; The following transformation is done on the write_many value
                  [0057D8]   218I ; to make the shift-in work easily.
                  [0057D8]   219I ;
                  [0057D8]   220I ; 	<35:30>|<29:24>|<23:18>|<17:12>|<11:06>|<05:00> =>
                  [0057D8]   221I ; 	<05:00>|<11:06>|<17;12>|<23:18>|<29:24>|<35:30>
                  [0057D8]   222I ;
                  [0057D8]   223I ; The size is found at <5:2> in the untransformed value,
                  [0057D8]   224I ; and thus at <35:32> in the transformed value.
                  [0057D8]   225I ;	0000	1  megabytes
                  [0057D8]   226I ;	0001	2  megabytes
                  [0057D8]   227I ;	0011	4  megabytes
                  [0057D8]   228I ;	0111	8  megabytes
                  [0057D8]   229I ;	1111	16 megabytes
                  [0057D8]   230I ;
                  [0057D8]   231I ; We need to calculate twice the size of the bcache.
                  [0057D8]   232I ; The write-many chain is stored in CNS__WRITE_MANY.
                  [0057D8]   233I ; The size is store in chain<35:32>.
                  [0057D8]   234I ;
         6CF51088 [0057D8]   235I 	hw_ldq/p p7, PT__IMPURE(p_temp)		; get impure pointer
         6E8713A8 [0057DC]   236I 	hw_ldq/p p20, CNS__WRITE_MANY(p7)	; get write-many chain
         4A841684 [0057E0]   237I 	srl	p20, #32, p4			; get size
         4481F004 [0057E4]   238I 	and	p4, #^xF, p4			; clean it
         40803404 [0057E8]   239I 	addq	p4, #1, p4			; add 1
         48803724 [0057EC]   240I 	sll	p4, #1, p4			; multiply by 2
                  [0057F0]   241I ;
                  [0057F0]   242I ; We will be turning off the bcache, so we will need to zap the write many
                  [0057F0]   243I ; chain bits for enable and size.
                  [0057F0]   244I ;
                  [0057F0]   245I ;                 |3333|3322|2222|2222|1111|1111|11                     
                  [0057F0]   246I ;                 |5432|1098|7654|3210|9876|5432|1098|7654|3210|
                  [0057F0]   247I ;                 +====+====+====+====+====+====+====+====+====+
                  [0057F0]   248I ; BC_ENABLE       |    | 1  |  11|1  1|11  |111 |    |    |    |
                  [0057F0]   249I ; BC_SIZE1        |   1|  1 |    |    |    |    |    |    |   1|
                  [0057F0]   250I ; BC_SIZE2        |  1 |   1|    |    |    |    |1   |    |    |
                  [0057F0]   251I ; BC_SIZE3        | 1  |    |1   |    |    |    | 1  |    |    |
                  [0057F0]   252I ; BC_SIZE4        |1   |    | 1  |    |    |    |  1 |    |    |
                  [0057F0]   253I ;                 +====+====+====+====+====+====+====+====+====+
                  [0057F0]   254I ;                   F    7    F    9    C    E    E    0    1
                  [0057F0]   255I ;
                  [0057F0]   256I 	GET_32CONS	p6, <^x7F9CEE01>, r31		; get low 32
File: ev6_pal_macros.mar
                  [0057F0]   239i  ASSUME <^x7F9CEE01> le  <^x7FFFFFFF>
         24DF7F9D [0057F0]   240i 	ldah	p6,<<^x7F9CEE01>+32768>@-16(r31); + xxx<31:16>
         20C6EE01 [0057F4]   241i 	lda	p6,<<^x7F9CEE01> & ^XFFFF>(p6) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         46860114 [0057F8]   257I 	bic	p20, p6, p20				; clear bits
         47E1F406 [0057FC]   258I 	bis	r31, #^xF, p6				; get ^xF
         48C41726 [005800]   259I 	sll	p6, #32, p6				; shift into position
         46860114 [005804]   260I 	bic	p20, p6, p20				; new write many chain
                  [005808]   261I ;
                  [005808]   262I ; Turn off SBE.
                  [005808]   263I ;
                  [005808]   264I ; Current state:
                  [005808]   265I ;	p4	twice the size of the bcache in megabytes
                  [005808]   266I ;	p20	write many chain to turn bcache off
                  [005808]   267I ;
                  [005808]   268I 	ALIGN_CACHE_BLOCK <^x47FF041F>	; align with nops
File: ev6_pal_macros.mar
47FF041F 47FF041F [005808]   273i 	.align 6, <^x47FF041F>
47FF041F 47FF041F [005810]
47FF041F 47FF041F [005818]
47FF041F 47FF041F [005820]
47FF041F 47FF041F [005828]
47FF041F 47FF041F [005830]
47FF041F 47FF041F [005838]
File: ev6_osf_system_pal.mar
                  [005840]   269I 
         63FF4000 [005840]   270I 	mb				; wait for MEM-OP's to complete
         201F0086 [005844]   271I 	lda     r0, ^x0086(r31)		; load I_CTL.....
         77E01110 [005848]   272I 	hw_mtpr r0, EV6__I_CTL		; .....SDE=2, IC_EN=3, SBE=0
         C0000000 [00584C]   273I 	br      r0, .			; create dest address
                  [005850]   274I 
         40023400 [005850]   275I 	addq    r0, #17, r0		; finish computing dest address 
         77FF1310 [005854]   276I 	hw_mtpr r31, EV6__IC_FLUSH	; flush the Icache
         F7E00000 [005858]   277I 	bne     r31, .			; separate retires
                  [00585C]   278I 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [00585C]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         7BE02000 [00585C]   279I 	hw_jmp_stall (r0)		; force flush
                  [005860]   280I 
                  [005860]   281I ;
                  [005860]   282I ; NOTE:
                  [005860]   283I ;
                  [005860]   284I ; The rest of the code should be pulled into the icache before we start
                  [005860]   285I ; invalidating the data caches. We do that by jumping through the
                  [005860]   286I ; cache blocks.
                  [005860]   287I ;
                  [005860]   288I 
                  [005860]   289I ;
                  [005860]   290I ; Now flush data caches. ECB twice the size of the bcache,
                  [005860]   291I ; i.e, 2 - 32 megabytes. Use a double loop, doing a megabyte at a
                  [005860]   292I ; time and check whether we need to punt periodically.
                  [005860]   293I ;
                  [005860]   294I ; Current state:
                  [005860]   295I ;	p4	twice the size of the cache in megabytes
                  [005860]   296I ;	p20	write many chain to turn bcache off
                  [005860]   297I ;
                  [005860]   298I 
                  [005860]   299I 	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
File: ev6_pal_macros.mar
47FF041F 47FF041F [005860]   273i 	.align 6, <^x47FF041F>
47FF041F 47FF041F [005868]
47FF041F 47FF041F [005870]
47FF041F 47FF041F [005878]
File: ev6_osf_system_pal.mar
                  [005880]   300I 
                  [005880]   301I sys__wtint_touch0:
         63FF4000 [005880]   302I 	mb					; (1)
         C3E0000E [005884]   303I 	br	r31, sys__wtint_touch1		; (2)
                  [005888]   304I 
                  [005888]   305I sys__wtint_start_flush:
         24DF8000 [005888]   306I 	ldah	p6, ^x8000(r31)			; (3) Kseg = 0xffff8000.00000000
         48C21726 [00588C]   307I 	sll	p6, #16, p6			; (4) shift into place
                  [005890]   308I 
                  [005890]   309I sys__wtint_outer_loop:
         64FF0D00 [005890]   310I 	hw_mfpr	p7, EV6__ISUM			; (3) get ISUM
                  [005894]   311I 
         40803524 [005894]   312I 	subq	p4, #1, p4			; (4) decrement outer counter
         20BF4000 [005898]   313I 	lda	p5, ^x4000(r31)			; (5) ^x4000 * 64 = 1mb
                  [00589C]   314I 
         F4E00048 [00589C]   315I 	bne	p7, sys__wtint_punt		; (6) got an interrupt
         C3E00000 [0058A0]   316I 	br	r31, sys__wtint_inner_loop	; (7) go to inner loop
                  [0058A4]   317I 
                  [0058A4]   318I sys__wtint_inner_loop:
         40A03525 [0058A4]   319I 	subq	p5, #1, p5			; (8) decrement inner counter
         63E6E800 [0058A8]   320I 	ecb	(p6)				; (9) ecb
         20C60040 [0058AC]   321I 	lda	p6, 64(p6)			; (10) next address
         E4A00001 [0058B0]   322I 	beq	p5, sys__wtint_loop_test	; (11) if done 
         C3FFFFFB [0058B4]   323I 	br	r31, sys__wtint_inner_loop	; (12) loop back
                  [0058B8]   324I 
                  [0058B8]   325I sys__wtint_loop_test:
         E4800005 [0058B8]   326I 	beq	p4, sys__wtint_bc_off		; (13) now turn off bcache
         C3FFFFF4 [0058BC]   327I 	br	r31, sys__wtint_outer_loop	; (14) next megabyte
                  [0058C0]   328I 
                  [0058C0]   329I ;
                  [0058C0]   330I ; Now turn the bcache off. We probably don't need to do this as long
                  [0058C0]   331I ; as we have pulled everything into the icache, but the debug (where we
                  [0058C0]   332I ; just jump to wakeup) needs it anyway.
                  [0058C0]   333I ;
                  [0058C0]   334I ; Current state:
                  [0058C0]   335I ;	p20	write many chain with bcache off
                  [0058C0]   336I ;
                  [0058C0]   337I 	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
File: ev6_pal_macros.mar
                  [0058C0]   273i 	.align 6, <^x47FF041F>
File: ev6_osf_system_pal.mar
                  [0058C0]   338I 
                  [0058C0]   339I sys__wtint_touch1:
         63FF4000 [0058C0]   340I 	mb					; (1)
         C3E0000E [0058C4]   341I 	br	r31, sys__wtint_touch2		; (2)
         47FF041F [0058C8]   342I 	bis	r31, r31, r31			; (3)
         47FF041F [0058CC]   343I 	bis	r31, r31, r31			; (4)				
                  [0058D0]   344I 
                  [0058D0]   345I sys__wtint_bc_off:
         469F0402 [0058D0]   346I 	bis	p20, r31, r2			; (5) move chain to r2
         43E0D400 [0058D4]   347I 	addq	r31, #6, r0			; (6) shift in 6x 6-bits
                  [0058D8]   348I sys__wtint_bc_off_loop::
                  [0058D8]   349I 	PVC_VIOLATE<30>				;
File: ev6_pal_macros.mar
                  [0058D8]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E22B40 [0058D8]   350I 	hw_mtpr	r2, EV6__DATA			; (7) (6,0L) shift in 6 bits
         40003520 [0058DC]   351I 	subq	r0, #1, r0			; (8) decrement R0
                  [0058E0]   352I 
         E4000002 [0058E0]   353I 	beq	r0, sys__wtint_bc_off_done	; (9) done if R0 is zero
         4840D682 [0058E4]   354I 	srl	r2, #6, r2			; (10) align next 6 bits
         C3FFFFFB [0058E8]   355I 	br	r31, sys__wtint_bc_off_loop	; (11) continue shifting
                  [0058EC]   356I sys__wtint_bc_off_done:
         77FF2740 [0058EC]   357I 	hw_mtpr	r31, <EV6__MM_STAT ! ^x40>	; (12) IPR write - sets SCBD 6
                  [0058F0]   358I 
         77FF2740 [0058F0]   359I 	hw_mtpr	r31, <EV6__MM_STAT ! ^x40>	; (13) stalls until write retires
         E7E00004 [0058F4]   360I 	beq	r31, sys__wtint_clocks		; (14) predicts fall thru
                  [0058F8]   361I 	PVC_VIOLATE <1006>
File: ev6_pal_macros.mar
                  [0058F8]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         C3FFFFFF [0058F8]   362I 	br	r31, .-4			; (15) predict infinite loop
         43FF0402 [0058FC]   363I 	addq	r31, r31, r2			; (16) nop
                  [005900]   364I ;
                  [005900]   365I ; Bcache should now be off.
                  [005900]   366I ; Now add CLK to interrupts that can wake the CPU.
                  [005900]   367I ;
                  [005900]   368I 
                  [005900]   369I IRQ_MASK = ^x0F
                  [005900]   370I 
                  [005900]   371I 	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
File: ev6_pal_macros.mar
                  [005900]   273i 	.align 6, <^x47FF041F>
File: ev6_osf_system_pal.mar
                  [005900]   372I 
                  [005900]   373I sys__wtint_touch2:
         63FF4000 [005900]   374I 	mb					; (1)
         C3E0000E [005904]   375I 	br	r31, sys__wtint_touch3		; (2)
                  [005908]   376I 
                  [005908]   377I sys__wtint_clocks:
         47E1F404 [005908]   378I 	bis	r31, #<IRQ_MASK>, p4		; (3) platform IRQ mask
         48843724 [00590C]   379I 	sll	p4, #EV6__IER__EIEN__S, p4	; (4) shift into place
         77E40A10 [005910]   380I 	hw_mtpr	p4, EV6__IER			; (5) (4,0L) write new ier
         C3E0000C [005914]   381I 	br	r31, sys__wtint_addr		; (6) form external address
                  [005918]   382I ;
                  [005918]   383I ; Get address of IICx register and PRBEN register.
                  [005918]   384I ;
                  [005918]   385I ; IICx	cpu 0	380	00 => 0011 1000 0000
                  [005918]   386I ;	cpu 1	3c0	01 => 0011 1100 0000
                  [005918]   387I ;	cpu 2	700	10 => 0111 0000 0000
                  [005918]   388I ;	cpu 3	740	11 => 0111 0100 0000
                  [005918]   389I ;
                  [005918]   390I ;So we start with ^b0011 0000 0000
                  [005918]   391I ;Then OR the whami into <10:9>
                  [005918]   392I ;Then we XOR whami with ^b10 and OR it into <7:6>
                  [005918]   393I ;
                  [005918]   394I 	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
File: ev6_pal_macros.mar
47FF041F 47FF041F [005918]   273i 	.align 6, <^x47FF041F>
47FF041F 47FF041F [005920]
47FF041F 47FF041F [005928]
47FF041F 47FF041F [005930]
47FF041F 47FF041F [005938]
File: ev6_osf_system_pal.mar
                  [005940]   395I 
                  [005940]   396I sys__wtint_touch3:
         63FF4000 [005940]   397I 	mb					; (1)
         C3E0000E [005944]   398I 	br	r31, sys__wtint_touch4		; (2)
                  [005948]   399I 
                  [005948]   400I sys__wtint_addr:
         209F801A [005948]   401I 	lda	p4, ^x801A(r31)			; (3) start to generate csr addr
         48807624 [00594C]   402I 	zapnot	p4, #3, p4			; (4) zap extension
         48839724 [005950]   403I 	sll	p4, #28, p4			; (5) now have 801.A000.0000
         22840340 [005954]   404I 	lda	p20, ^x340(p4)			; (6) PRBEN address
                  [005958]   405I 
         20840300 [005958]   406I 	lda	p4, ^x300(p4)			; (7) now have 801.A000.0300
         6CB51098 [00595C]   407I 	hw_ldq/p p5, PT__WHAMI(p_temp)		; (8) get whami
         48A13726 [005960]   408I 	sll	p5, #9, p6			; (9) move whami to <10:9>
         44A05807 [005964]   409I 	xor	p5, #^b10, p7			; (10) xor
         48E0D727 [005968]   410I 	sll	p7, #6, p7			; (11) move to <7:6>
                  [00596C]   411I 
         44860404 [00596C]   412I 	bis	p4, p6, p4			; (12) OR into <10:9>
         44870404 [005970]   413I 	bis	p4, p7, p4			; (13) OR into <7:6> to get IICx
         C3E00004 [005974]   414I 	br	r31, sys__wtint_sleep		; (14)
                  [005978]   415I ;
                  [005978]   416I ; Write the Cchip IIC CSR corresponding to its CPU ID with the
                  [005978]   417I ; number of interval timer interrupts it wishes to ignore.
                  [005978]   418I ; Read PRBEN to turn off probes
                  [005978]   419I ;
                  [005978]   420I ; Current state:
                  [005978]   421I ;	p4	address of IIC CSR for this CPU
                  [005978]   422I ;	p20	address of PRBEN register
                  [005978]   423I ;	r16	number of ticks to skip
                  [005978]   424I ;
                  [005978]   425I 	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
File: ev6_pal_macros.mar
47FF041F 47FF041F [005978]   273i 	.align 6, <^x47FF041F>
File: ev6_osf_system_pal.mar
                  [005980]   426I 
                  [005980]   427I sys__wtint_touch4:
         63FF4000 [005980]   428I 	mb					; (1)
         C3FFFFC0 [005984]   429I 	br	r31, sys__wtint_start_flush	; (2)
                  [005988]   430I 
                  [005988]   431I sys__wtint_sleep:
         4A00F637 [005988]   432I 	zapnot	r16, #7, p23			; (3) clean number of ticks
         7EE41000 [00598C]   433I 	hw_stq/p p23, (p4)			; (4) store number of ticks
         63FF4000 [005990]   434I 	mb					; (5) force it out
                  [005994]   435I 
         77FF17F0 [005994]   436I 	hw_mtpr	r31, EV6__SLEEP			; (6) (4-7,0L) prepare to sleep
         47FF041F [005998]   437I 	bis	r31, r31, r31			; (7)
         47FF041F [00599C]   438I 	bis	r31, r31, r31			; (8)
                  [0059A0]   439I 
                  [0059A0]   440I 	ASSUME_FETCH_BLOCK
                  [0059A0]   441I 
         77FF27F0 [0059A0]   442I 	hw_mtpr	r31, <EV6__MM_STAT ! ^xF0>	; (9) stall
         6CB41000 [0059A4]   443I 	hw_ldq/p p5, (p20)			; (10) turn off probes
         44A50406 [0059A8]   444I 	bis p5, p5, p6				; (11) consume data
         63FF4000 [0059AC]   445I 	mb					; (12) do an memory barrier
                  [0059B0]   446I 
         77FF17F0 [0059B0]   447I 	hw_mtpr	31, EV6__SLEEP			; (13) (4-7,0L) now do it
                  [0059B4]   448I 	PVC_VIOLATE <1006>
File: ev6_pal_macros.mar
                  [0059B4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         C3FFFFFF [0059B4]   449I 	br	r31, .-4			; (14) branch to self
                  [0059B8]   450I ;
                  [0059B8]   451I ; Got an interrupt while we were flushing the bcache.
                  [0059B8]   452I ;
                  [0059B8]   453I 	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
File: ev6_pal_macros.mar
47FF041F 47FF041F [0059B8]   273i 	.align 6, <^x47FF041F>
File: ev6_osf_system_pal.mar
                  [0059C0]   454I 
                  [0059C0]   455I sys__wtint_punt:
                  [0059C0]   456I 	PVC_JSR	restore_state, bsr=1
File: ev6_pal_macros.mar
                  [0059C0]   531i  pvc_lbl \pcv_index, \pcv_jsr_restore_state0, osf
File: ev6_osf_system_pal.mar
         D0FFFC5A [0059C0]   457I 	bsr	p7, pal__restore_state		; (3) restore state
         C3E00000 [0059C4]   458I 	br	r31, sys__wtint_noticks		; (4) return
                  [0059C8]   459I ;
                  [0059C8]   460I ; Called with skipped ticks = 0. Just return.
                  [0059C8]   461I ;
                  [0059C8]   462I sys__wtint_noticks:
         47FF0400 [0059C8]   463I 	bis	r31, r31, r0			; zero ticks skipped
         7BF78000 [0059CC]   464I 	hw_ret	(p23)
                  [0059D0]   465I 
                  [0059D0]   467  
                  [0059D0]   468  	END_FREE_CODE
                  [0059D0]   469  
                  [0059D0]   470  ;+
                  [0059D0]   471  ; IPL table
                  [0059D0]   472  ;	proc_corr_err		7
                  [0059D0]   473  ;	performance monitor	6
                  [0059D0]   474  ;	interprocessor,clock	5
                  [0059D0]   475  ;	high priority device	4
                  [0059D0]   476  ;	low priority device	3
                  [0059D0]   477  ;	system software		2
                  [0059D0]   478  ;	system software		1
                  [0059D0]   479  ;	user/system software	0
                  [0059D0]   480  ;
                  [0059D0]   481  ; This table of 8 quadwords, is indexed into by IPL, are used to write IER.
                  [0059D0]   482  ; The EIEN portion will be dependent on the meaning of the IRQ pins
                  [0059D0]   483  ; of the chip.
                  [0059D0]   484  ;
                  [0059D0]   485  ; Sample for tsunami:
                  [0059D0]   486  ;	IRQ<0> = errors			ipl 7 
                  [0059D0]   487  ;	IRQ<1> = device			ipl 4
                  [0059D0]   488  ;	IRQ<2> = clock			ipl 5
                  [0059D0]   489  ;	IRQ<3> = interprocessor		ipl 5
                  [0059D0]   490  ;-
                  [0059D0]   491  .if ne reference_platform
                  [0059D0]   492  IRQ_IP 	= 8				; position within EV6__ISUM__IE field
                  [0059D0]   493  IRQ_CLK = 4
                  [0059D0]   494  IRQ_DEV	= 2
                  [0059D0]   495  IRQ_ERR = 1
                  [0059D0]   496  
                  [0059D0]   497  ipl3 = ^x0F				; mask for EV6__IER__EIEN field
                  [0059D0]   498  ipl4 = ^x0D
                  [0059D0]   499  ipl5 = ^x01
                  [0059D0]   500  ipl6 = ^x01
                  [0059D0]   501  ipl7 = ^x00
                  [0059D0]   502  
                  [0059D0]   503  .iff					; if ne reference_platform
                  [0059D0]   504  
                  [0059D0]   505  ipl3 = ^x00
                  [0059D0]   506  ipl4 = ^x00
                  [0059D0]   507  ipl5 = ^x00
                  [0059D0]   508  ipl6 = ^x00
                  [0059D0]   509  ipl7 = ^x00
                  [0059D0]   510  
                  [0059D0]   511  .endc					; if ne reference_platform
                  [0059D0]   492I IRQ_IP 	= 8				; position within EV6__ISUM__IE field
                  [0059D0]   493I IRQ_CLK = 4
                  [0059D0]   494I IRQ_DEV	= 2
                  [0059D0]   495I IRQ_ERR = 1
                  [0059D0]   496I 
                  [0059D0]   497I ipl3 = ^x0F				; mask for EV6__IER__EIEN field
                  [0059D0]   498I ipl4 = ^x0D
                  [0059D0]   499I ipl5 = ^x01
                  [0059D0]   500I ipl6 = ^x01
                  [0059D0]   501I ipl7 = ^x00
                  [0059D0]   502I 
                  [0059D0]   512  
                  [0059D0]   513  ;
                  [0059D0]   514  ; The format of the IER_CM register is as follows:
                  [0059D0]   515  ;	IER_CM<30:29>		performance counter interrupt enables
                  [0059D0]   516  ;	IER_CM<31>		correct read error interrupt enable
                  [0059D0]   517  ;	IER_CM<32>		serial line interrupt enable
                  [0059D0]   518  ;	IER_CM<38:33>		external interrupt enables (EIEN)
                  [0059D0]   519  ;
                  [000D00]   520  	. = ^x0D00
                  [000D00]   521  
                  [000D00]   522  IPL_TABLE:
                  [000D00]   523  
                  [000D00]   524  ASSUME <IPL_TABLE - TRAP__START> le <^x7FFF>
                  [000D00]   525  IRQ_MASK = ^x0F
                  [000D00]   526  
                  [000D00]   527  ; ipl 0
0000001E E0000000 [000D00]   528  	.quad	<<IRQ_MASK@EV6__IER__EIEN__S>!<^x1@EV6__IER__CREN__S>! -
                  [000D08]   529  		 <^x3@EV6__IER__PCEN__S>>
                  [000D08]   530  ; ipl 1
0000001E E0000000 [000D08]   531  	.quad	<<IRQ_MASK@EV6__IER__EIEN__S>!<^x1@EV6__IER__CREN__S>! -
                  [000D10]   532  		 <^x3@EV6__IER__PCEN__S>>
                  [000D10]   533  ; ipl 2
0000001E E0000000 [000D10]   534  	.quad	<<IRQ_MASK@EV6__IER__EIEN__S>!<^x1@EV6__IER__CREN__S>! -
                  [000D18]   535  		 <^x3@EV6__IER__PCEN__S>>
                  [000D18]   536  ; ipl 3
0000001E E0000000 [000D18]   537  	.quad	<<ipl3@EV6__IER__EIEN__S>!<^x1@EV6__IER__CREN__S>! -
                  [000D20]   538  		 <^x3@EV6__IER__PCEN__S>>
                  [000D20]   539  ; ipl 4
0000001A E0000000 [000D20]   540  	.quad	<<ipl4@EV6__IER__EIEN__S>!<^x1@EV6__IER__CREN__S>! -
                  [000D28]   541  		 <^x3@EV6__IER__PCEN__S>>
                  [000D28]   542  ; ipl 5
00000000 E0000000 [000D28]   543  	.quad	<<^x1@EV6__IER__CREN__S>!<^x3@EV6__IER__PCEN__S>>
                  [000D30]   544  ; ipl 6
00000000 80000000 [000D30]   545  	.quad	<^x1@EV6__IER__CREN__S>
                  [000D38]   546  ; ipl 7
00000000 00000000 [000D38]   547  	.quad	0
                  [000D40]   548  
                  [000D40]   549  	GOTO_FREE_CODE
File: ev6_pal_macros.mar
00000000 00000000 [0059D0]    67M     .align 6
00000000 00000000 [0059D8]
00000000 00000000 [0059E0]
00000000 00000000 [0059E8]
00000000 00000000 [0059F0]
00000000 00000000 [0059F8]
File: ev6_osf_system_pal.mar
                  [005A00]   550  
                  [005A00]   551  .if ne	check_interrupt_pending
                  [005A00]   552  ;+
                  [005A00]   553  ; sys__deassert_interrupt
                  [005A00]   554  ;
                  [005A00]   555  ; Entry:
                  [005A00]   556  ;	Entered from rei when isum<device_irq> is set.
                  [005A00]   557  ;
                  [005A00]   558  ; Function:
                  [005A00]   559  ; 	Some platforms, such as those with tsunami, have a problem with the
                  [005A00]   560  ; 	latency between clearing an interrupt and the interrupt being
                  [005A00]   561  ;	deasserted.
                  [005A00]   562  ;
                  [005A00]   563  ; 	Those platforms are opting to, on isum<device_irq> set, write to
                  [005A00]   564  ; 	a tsunami csr to deassert the interrupt. A real interrupt will
                  [005A00]   565  ; 	re-assert on the next polling loop.
                  [005A00]   566  ;
                  [005A00]   567  ; Current state:
                  [005A00]   568  ;	p23	exc_addr 
                  [005A00]   569  ;-
                  [005A00]   570  	ALIGN_FETCH_BLOCK
                  [005A00]   571  
                  [005A00]   572  sys__deassert_interrupt:
                  [005A00]   573  
                  [005A00]   574      .if ne reference_platform
                  [005A00]   575  ;
                  [005A00]   576  ; Write to MISC<DEVSUP> bit for this cpu.
                  [005A00]   577  ; The MISC CSR is at 801.A000.0080.
                  [005A00]   578  ; Find out who we are from PT__WHAMI.
                  [005A00]   579  ;
                  [005A00]   580  ; <sample code below>
                  [005A00]   581  ;
                  [005A00]   582  	lda	p4, ^x801A(r31)			; generate 801.A000.0000
                  [005A00]   583  	zapnot	p4, #3, p4			; zap extension
                  [005A00]   584  	sll	p4, #28, p4			; move into place
                  [005A00]   585  	hw_ldq/p p5, PT__WHAMI(p_temp)		; get whami
                  [005A00]   586  	bis	r31, #1, p6			; get a one
                  [005A00]   587  	addq	p5, #40, p5			; bit position + whami
                  [005A00]   588  	sll	p6, p5, p6			; shift into position
                  [005A00]   589  	hw_stq/p p6, ^x80(p4)			; write to 801.A000.0080
                  [005A00]   590  
                  [005A00]   591      .endc					; if ne reference_platform
                  [005A00]   592  
                  [005A00]   593  	hw_ret_stall (p23)			; return
                  [005A00]   594  .endc						; if ne check_interrupt_pending
                  [005A00]   552I ;+
                  [005A00]   553I ; sys__deassert_interrupt
                  [005A00]   554I ;
                  [005A00]   555I ; Entry:
                  [005A00]   556I ;	Entered from rei when isum<device_irq> is set.
                  [005A00]   557I ;
                  [005A00]   558I ; Function:
                  [005A00]   559I ; 	Some platforms, such as those with tsunami, have a problem with the
                  [005A00]   560I ; 	latency between clearing an interrupt and the interrupt being
                  [005A00]   561I ;	deasserted.
                  [005A00]   562I ;
                  [005A00]   563I ; 	Those platforms are opting to, on isum<device_irq> set, write to
                  [005A00]   564I ; 	a tsunami csr to deassert the interrupt. A real interrupt will
                  [005A00]   565I ; 	re-assert on the next polling loop.
                  [005A00]   566I ;
                  [005A00]   567I ; Current state:
                  [005A00]   568I ;	p23	exc_addr 
                  [005A00]   569I ;-
                  [005A00]   570I 	ALIGN_FETCH_BLOCK
File: ev6_pal_macros.mar
                  [005A00]   267i 	.align 4
File: ev6_osf_system_pal.mar
                  [005A00]   571I 
                  [005A00]   572I sys__deassert_interrupt:
                  [005A00]   573I 
                  [005A00]   574I     .if ne reference_platform
                  [005A00]   575I ;
                  [005A00]   576I ; Write to MISC<DEVSUP> bit for this cpu.
                  [005A00]   577I ; The MISC CSR is at 801.A000.0080.
                  [005A00]   578I ; Find out who we are from PT__WHAMI.
                  [005A00]   579I ;
                  [005A00]   580I ; <sample code below>
                  [005A00]   581I ;
                  [005A00]   582I 	lda	p4, ^x801A(r31)			; generate 801.A000.0000
                  [005A00]   583I 	zapnot	p4, #3, p4			; zap extension
                  [005A00]   584I 	sll	p4, #28, p4			; move into place
                  [005A00]   585I 	hw_ldq/p p5, PT__WHAMI(p_temp)		; get whami
                  [005A00]   586I 	bis	r31, #1, p6			; get a one
                  [005A00]   587I 	addq	p5, #40, p5			; bit position + whami
                  [005A00]   588I 	sll	p6, p5, p6			; shift into position
                  [005A00]   589I 	hw_stq/p p6, ^x80(p4)			; write to 801.A000.0080
                  [005A00]   590I 
                  [005A00]   591I     .endc					; if ne reference_platform
                  [005A00]   575I ;
                  [005A00]   576I ; Write to MISC<DEVSUP> bit for this cpu.
                  [005A00]   577I ; The MISC CSR is at 801.A000.0080.
                  [005A00]   578I ; Find out who we are from PT__WHAMI.
                  [005A00]   579I ;
                  [005A00]   580I ; <sample code below>
                  [005A00]   581I ;
         209F801A [005A00]   582I 	lda	p4, ^x801A(r31)			; generate 801.A000.0000
         48807624 [005A04]   583I 	zapnot	p4, #3, p4			; zap extension
         48839724 [005A08]   584I 	sll	p4, #28, p4			; move into place
         6CB51098 [005A0C]   585I 	hw_ldq/p p5, PT__WHAMI(p_temp)		; get whami
         47E03406 [005A10]   586I 	bis	r31, #1, p6			; get a one
         40A51405 [005A14]   587I 	addq	p5, #40, p5			; bit position + whami
         48C50726 [005A18]   588I 	sll	p6, p5, p6			; shift into position
         7CC41080 [005A1C]   589I 	hw_stq/p p6, ^x80(p4)			; write to 801.A000.0080
                  [005A20]   590I 
                  [005A20]   592I     
         7BF7A000 [005A20]   593I 	hw_ret_stall (p23)			; return
                  [005A24]   595  
                  [005A24]   596  
                  [005A24]   597  ;+
                  [005A24]   598  ; sys__interrupt_ei
                  [005A24]   599  ;
                  [005A24]   600  ; Interrupt from external source.
                  [005A24]   601  ;
                  [005A24]   602  ; Entry:
                  [005A24]   603  ;	p4	isum
                  [005A24]   604  ;	p7	ei bits in <5:0>
                  [005A24]   605  ;	p23	exc_addr
                  [005A24]   606  ;-
                  [005A24]   607  sys__interrupt_ei:
                  [005A24]   608  .if ne reference_platform
                  [005A24]   609  ;
                  [005A24]   610  ;	IRQ<0> = errors			ipl 7
                  [005A24]   611  ;	IRQ<1> = device			ipl 4
                  [005A24]   612  ;	IRQ<2> = clock			ipl 5
                  [005A24]   613  ;	IRQ<3> = interprocessor		ipl 5
                  [005A24]   614  ;
                  [005A24]   615  	and	p7, #IRQ_CLK, p5		; check for clock
                  [005A24]   616  	beq	p5, sys__int_check_ip		; check ip if not
                  [005A24]   617  	br	r31, sys__int_clk		; branch for clock
                  [005A24]   618  sys__int_check_ip:
                  [005A24]   619  	and	p7, #IRQ_IP, p5			; check for interprocessor
                  [005A24]   620  	beq	p5, sys__int_check_dev		; check dev if not
                  [005A24]   621  	br	r31, sys__int_ip		; branch for ip
                  [005A24]   622  sys__int_check_dev:
                  [005A24]   623  	and	p7, #IRQ_DEV, p5		; check for devices
                  [005A24]   624  	beq	p5, sys__int_check_err		; check err if not
                  [005A24]   625  	br	r31, sys__int_dev		; branch for devices
                  [005A24]   626  sys__int_check_err:
                  [005A24]   627  	and	p7, #IRQ_ERR, p5		; check for errors
                  [005A24]   628  	beq	p5, sys__int_pal_err		; pal error if not
                  [005A24]   629  	br	r31, sys__int_err		; branch for errors
                  [005A24]   630  ;
                  [005A24]   631  ; Since p7 was non-zero, we don't get here unless there is a pal bug.
                  [005A24]   632  ;
                  [005A24]   633  sys__int_pal_err:
                  [005A24]   634  	lda	p7, MCHK__BUGCHECK(r31)		; mchk code
                  [005A24]   635  	br	r31, trap__pal_bugcheck
                  [005A24]   636  
                  [005A24]   637  ;+
                  [005A24]   638  ; Clock interrupt.
                  [005A24]   639  ;
                  [005A24]   640  ; Current state:
                  [005A24]   641  ;	p23	exc_addr
                  [005A24]   642  ;
                  [005A24]   643  ; Do some of the processing as a sample.
                  [005A24]   644  ;-
                  [005A24]   645  sys__int_clk:
                  [005A24]   646  
                  [005A24]   647  ;
                  [005A24]   648  ; Clear the timer interrupt request for this cpu.
                  [005A24]   649  ; On Tsunami for example, we would write the MISC<ININTR> bit for this cpu.
                  [005A24]   650  ; The MISC CSR is at 801.A000.0080
                  [005A24]   651  ; Find out who we are from PT__WHAMI.
                  [005A24]   652  ;
                  [005A24]   653  ;	<sample code below>
                  [005A24]   654  ;
                  [005A24]   655  	lda	p4, ^x801A(r31)			; generate 801.A000.0000
                  [005A24]   656  	zapnot	p4, #3, p4			; zap extension
                  [005A24]   657  	sll	p4, #28, p4			; move into place
                  [005A24]   658  	hw_ldq/p p5, PT__WHAMI(p_temp)		; get whami
                  [005A24]   659  	lda	p6, ^x10(r31)			; start at bit position 4
                  [005A24]   660  	sll	p6, p5, p6			; shift left by whami
                  [005A24]   661  	hw_stq/p p6, ^x80(p4)			; write to 801.A000.0080
                  [005A24]   662  	hw_ldq/p p6, ^x80(p4)			; make sure write completes
                  [005A24]   663  	mb
                  [005A24]   664  ;
                  [005A24]   665  ; Now get ready to post the interrupt.
                  [005A24]   666  ;
                  [005A24]   667  	hw_stq/p p23, PT__STACK_PC(p_temp)	; store pc for post
                  [005A24]   668  	bis	r31, #OSF_A0_INT__CLK, p5	; mark clock
                  [005A24]   669  	hw_stq/p p5, PT__NEW_A0(p_temp)		; save new a0 away
                  [005A24]   670  
                  [005A24]   671  	lda	p6, OSF_IPL__CLK(r31)		; ipl for clock
                  [005A24]   672  	br	r31, sys__int_post		; post interrupt
                  [005A24]   673  
                  [005A24]   674  ;+
                  [005A24]   675  ; Interrupts that need to be handled.
                  [005A24]   676  ;-
                  [005A24]   677  sys__int_ip:
                  [005A24]   678  sys__int_dev:
                  [005A24]   679  
                  [005A24]   680      .if eq force_path			; 1.41
                  [005A24]   681  	hw_ret	(p23)			; return to user
                  [005A24]   682      .iff
                  [005A24]   683  	ALIGN_FETCH_BLOCK <^x47FF041F>	; align
                  [005A24]   684  	PVC_VIOLATE <1007>
                  [005A24]   685  	PVC_VIOLATE <1020>		; stop permutation
                  [005A24]   686  	hw_jmp	(p23)			; return with jmp
                  [005A24]   687  	br	r31, .-4		; stop predictor
                  [005A24]   688      .endc				; 1.41
                  [005A24]   689  
                  [005A24]   690  ;+
                  [005A24]   691  ; Error interrupt from system
                  [005A24]   692  ;
                  [005A24]   693  ; Current state:
                  [005A24]   694  ;	p4	ev6__isum
                  [005A24]   695  ;	p7	ev6__isum__ei bits in <5:0>
                  [005A24]   696  ;	p23	exc_addr
                  [005A24]   697  ;-
                  [005A24]   698  sys__int_err:
                  [005A24]   699  	extbl	p_misc, #2, p5				; get mces
                  [005A24]   700  	zap	p_misc, #^x78, p_misc			; clear mchk_code & SCBv
                  [005A24]   701  
                  [005A24]   702  	bis	p5, #<1@MCES__MCHK__S>, p6		; set MCES<MCHK>
                  [005A24]   703  	sll	p6, #OSF_P_MISC__MCES__MCHK__S, p6	; shift into position
                  [005A24]   704  	bis	p_misc, p6, p_misc			; or back mces
                  [005A24]   705  
                  [005A24]   706  	lda	p6, SCB__SYSMCHK(r31)			; SCB vector
                  [005A24]   707  	sll	p6, #OSF_P_MISC__SCBV__S, p6		; move SCBv into position
                  [005A24]   708  	bis	p_misc, p6, p_misc			; or back scbv
                  [005A24]   709  
                  [005A24]   710  	lda	p6, MCHK__SYS_HRD_ERR(r31)		; mchk code
                  [005A24]   711  	sll	p6, #OSF_P_MISC__MCHK_CODE__S, p6	; mchk code into position
                  [005A24]   712  	bis	p_misc, p6, p_misc			; or back mchk code
                  [005A24]   713  
                  [005A24]   714  	blbs	p5, sys__double_machine_check		; halt on double
                  [005A24]   715  	blbs	p23, sys__machine_check_while_in_pal	; halt on in pal mode
                  [005A24]   716  
                  [005A24]   717  ;
                  [005A24]   718  ; Compute where the frame is.
                  [005A24]   719  ;
                  [005A24]   720  ; Current state:
                  [005A24]   721  ;	p4	isum
                  [005A24]   722  ;	p23	exc_addr
                  [005A24]   723  ;
                  [005A24]   724  	hw_ldq/p p6, PT__WHAMI(p_temp)			; get whami
                  [005A24]   725  
                  [005A24]   726  	lda	p5, PAL__LOGOUT_SPECIFIC_SIZE(r31)	; short&long size
                  [005A24]   727  	mulq	p6, p5, p5				; * whami
                  [005A24]   728  
                  [005A24]   729  	GET_32CONS	p6, PAL__LOGOUT_BASE, r31	; logout base
                  [005A24]   730  	addq	p5, p6, p5				; (size*whami) + base
                  [005A24]   731  	lda	p5, MCHK__BASE(p5)			; start of mchk area
                  [005A24]   732  
                  [005A24]   733  	hw_stq/p p23, MCHK__EXC_ADDR(p5)		; store exc_addr
                  [005A24]   734  	hw_stq/p p23, PT__STACK_PC(p_temp)		; save fault pc
                  [005A24]   735  
                  [005A24]   736  	hw_stq/p p4, MCHK__ISUM(p5)			; store isum
                  [005A24]   737  	hw_stq/p r31, MCHK__DC1_SYNDROME(p5)
                  [005A24]   738  	hw_stq/p r31, MCHK__DC0_SYNDROME(p5)
                  [005A24]   739  	hw_stq/p r31, MCHK__C_STAT(p5)
                  [005A24]   740  	hw_stq/p r31, MCHK__C_STS(p5)
                  [005A24]   741  	hw_stq/p r31, MCHK__C_ADDR(p5)
                  [005A24]   742  
                  [005A24]   743  	hw_stq/p r31, MCHK__MM_STAT(p5)			; store 0
                  [005A24]   744  
                  [005A24]   745  	hw_stq/p r31, MCHK__I_STAT(p5)			; store 0
                  [005A24]   746  	hw_stq/p r31, MCHK__DC_STAT(p5)			; store 0
                  [005A24]   747  
                  [005A24]   748  	bis	r31, r31, p20				; no retry
                  [005A24]   749  ;
                  [005A24]   750  ; Current state
                  [005A24]   751  ;
                  [005A24]   752  ;	p5	base of mchk area
                  [005A24]   753  ;	p20	retry flag
                  [005A24]   754  ;
                  [005A24]   755  	br	r31, sys__mchk_header			; go build frame
                  [005A24]   756  .endc						; if ne reference_platform
                  [005A24]   609I ;
                  [005A24]   610I ;	IRQ<0> = errors			ipl 7
                  [005A24]   611I ;	IRQ<1> = device			ipl 4
                  [005A24]   612I ;	IRQ<2> = clock			ipl 5
                  [005A24]   613I ;	IRQ<3> = interprocessor		ipl 5
                  [005A24]   614I ;
         44E09005 [005A24]   615I 	and	p7, #IRQ_CLK, p5		; check for clock
         E4A00001 [005A28]   616I 	beq	p5, sys__int_check_ip		; check ip if not
         C3E0000B [005A2C]   617I 	br	r31, sys__int_clk		; branch for clock
                  [005A30]   618I sys__int_check_ip:
         44E11005 [005A30]   619I 	and	p7, #IRQ_IP, p5			; check for interprocessor
         E4A00001 [005A34]   620I 	beq	p5, sys__int_check_dev		; check dev if not
         C3E00016 [005A38]   621I 	br	r31, sys__int_ip		; branch for ip
                  [005A3C]   622I sys__int_check_dev:
         44E05005 [005A3C]   623I 	and	p7, #IRQ_DEV, p5		; check for devices
         E4A00001 [005A40]   624I 	beq	p5, sys__int_check_err		; check err if not
         C3E00013 [005A44]   625I 	br	r31, sys__int_dev		; branch for devices
                  [005A48]   626I sys__int_check_err:
         44E03005 [005A48]   627I 	and	p7, #IRQ_ERR, p5		; check for errors
         E4A00001 [005A4C]   628I 	beq	p5, sys__int_pal_err		; pal error if not
         C3E00011 [005A50]   629I 	br	r31, sys__int_err		; branch for errors
                  [005A54]   630I ;
                  [005A54]   631I ; Since p7 was non-zero, we don't get here unless there is a pal bug.
                  [005A54]   632I ;
                  [005A54]   633I sys__int_pal_err:
         20FF008E [005A54]   634I 	lda	p7, MCHK__BUGCHECK(r31)		; mchk code
         C3FFEAB5 [005A58]   635I 	br	r31, trap__pal_bugcheck
                  [005A5C]   636I 
                  [005A5C]   637I ;+
                  [005A5C]   638I ; Clock interrupt.
                  [005A5C]   639I ;
                  [005A5C]   640I ; Current state:
                  [005A5C]   641I ;	p23	exc_addr
                  [005A5C]   642I ;
                  [005A5C]   643I ; Do some of the processing as a sample.
                  [005A5C]   644I ;-
                  [005A5C]   645I sys__int_clk:
                  [005A5C]   646I 
                  [005A5C]   647I ;
                  [005A5C]   648I ; Clear the timer interrupt request for this cpu.
                  [005A5C]   649I ; On Tsunami for example, we would write the MISC<ININTR> bit for this cpu.
                  [005A5C]   650I ; The MISC CSR is at 801.A000.0080
                  [005A5C]   651I ; Find out who we are from PT__WHAMI.
                  [005A5C]   652I ;
                  [005A5C]   653I ;	<sample code below>
                  [005A5C]   654I ;
         209F801A [005A5C]   655I 	lda	p4, ^x801A(r31)			; generate 801.A000.0000
         48807624 [005A60]   656I 	zapnot	p4, #3, p4			; zap extension
         48839724 [005A64]   657I 	sll	p4, #28, p4			; move into place
         6CB51098 [005A68]   658I 	hw_ldq/p p5, PT__WHAMI(p_temp)		; get whami
         20DF0010 [005A6C]   659I 	lda	p6, ^x10(r31)			; start at bit position 4
         48C50726 [005A70]   660I 	sll	p6, p5, p6			; shift left by whami
         7CC41080 [005A74]   661I 	hw_stq/p p6, ^x80(p4)			; write to 801.A000.0080
         6CC41080 [005A78]   662I 	hw_ldq/p p6, ^x80(p4)			; make sure write completes
         63FF4000 [005A7C]   663I 	mb
                  [005A80]   664I ;
                  [005A80]   665I ; Now get ready to post the interrupt.
                  [005A80]   666I ;
         7EF51060 [005A80]   667I 	hw_stq/p p23, PT__STACK_PC(p_temp)	; store pc for post
         47E03405 [005A84]   668I 	bis	r31, #OSF_A0_INT__CLK, p5	; mark clock
         7CB51068 [005A88]   669I 	hw_stq/p p5, PT__NEW_A0(p_temp)		; save new a0 away
                  [005A8C]   670I 
         20DF0005 [005A8C]   671I 	lda	p6, OSF_IPL__CLK(r31)		; ipl for clock
         C3E00038 [005A90]   672I 	br	r31, sys__int_post		; post interrupt
                  [005A94]   673I 
                  [005A94]   674I ;+
                  [005A94]   675I ; Interrupts that need to be handled.
                  [005A94]   676I ;-
                  [005A94]   677I sys__int_ip:
                  [005A94]   678I sys__int_dev:
                  [005A94]   679I 
                  [005A94]   680I     .if eq force_path			; 1.41
                  [005A94]   681I 	hw_ret	(p23)			; return to user
                  [005A94]   682I     .iff
                  [005A94]   683I 	ALIGN_FETCH_BLOCK <^x47FF041F>	; align
                  [005A94]   684I 	PVC_VIOLATE <1007>
                  [005A94]   685I 	PVC_VIOLATE <1020>		; stop permutation
                  [005A94]   686I 	hw_jmp	(p23)			; return with jmp
                  [005A94]   687I 	br	r31, .-4		; stop predictor
                  [005A94]   688I     .endc				; 1.41
         7BF78000 [005A94]   681I 	hw_ret	(p23)			; return to user
                  [005A98]   689I     
                  [005A98]   690I ;+
                  [005A98]   691I ; Error interrupt from system
                  [005A98]   692I ;
                  [005A98]   693I ; Current state:
                  [005A98]   694I ;	p4	ev6__isum
                  [005A98]   695I ;	p7	ev6__isum__ei bits in <5:0>
                  [005A98]   696I ;	p23	exc_addr
                  [005A98]   697I ;-
                  [005A98]   698I sys__int_err:
         4AC050C5 [005A98]   699I 	extbl	p_misc, #2, p5				; get mces
         4ACF1616 [005A9C]   700I 	zap	p_misc, #^x78, p_misc			; clear mchk_code & SCBv
                  [005AA0]   701I 
         44A03406 [005AA0]   702I 	bis	p5, #<1@MCES__MCHK__S>, p6		; set MCES<MCHK>
         48C21726 [005AA4]   703I 	sll	p6, #OSF_P_MISC__MCES__MCHK__S, p6	; shift into position
         46C60416 [005AA8]   704I 	bis	p_misc, p6, p_misc			; or back mces
                  [005AAC]   705I 
         20DF0660 [005AAC]   706I 	lda	p6, SCB__SYSMCHK(r31)			; SCB vector
         48C31726 [005AB0]   707I 	sll	p6, #OSF_P_MISC__SCBV__S, p6		; move SCBv into position
         46C60416 [005AB4]   708I 	bis	p_misc, p6, p_misc			; or back scbv
                  [005AB8]   709I 
         20DF0202 [005AB8]   710I 	lda	p6, MCHK__SYS_HRD_ERR(r31)		; mchk code
         48C51726 [005ABC]   711I 	sll	p6, #OSF_P_MISC__MCHK_CODE__S, p6	; mchk code into position
         46C60416 [005AC0]   712I 	bis	p_misc, p6, p_misc			; or back mchk code
                  [005AC4]   713I 
         F0A0023F [005AC4]   714I 	blbs	p5, sys__double_machine_check		; halt on double
         F2E00241 [005AC8]   715I 	blbs	p23, sys__machine_check_while_in_pal	; halt on in pal mode
                  [005ACC]   716I 
                  [005ACC]   717I ;
                  [005ACC]   718I ; Compute where the frame is.
                  [005ACC]   719I ;
                  [005ACC]   720I ; Current state:
                  [005ACC]   721I ;	p4	isum
                  [005ACC]   722I ;	p23	exc_addr
                  [005ACC]   723I ;
         6CD51098 [005ACC]   724I 	hw_ldq/p p6, PT__WHAMI(p_temp)			; get whami
                  [005AD0]   725I 
         20BF0400 [005AD0]   726I 	lda	p5, PAL__LOGOUT_SPECIFIC_SIZE(r31)	; short&long size
         4CC50405 [005AD4]   727I 	mulq	p6, p5, p5				; * whami
                  [005AD8]   728I 
                  [005AD8]   729I 	GET_32CONS	p6, PAL__LOGOUT_BASE, r31	; logout base
File: ev6_pal_macros.mar
                  [005AD8]   239i  ASSUME <pal__logout_base> le  <^x7FFFFFFF>
         24DF0000 [005AD8]   240i 	ldah	p6,<<pal__logout_base>+32768>@-16(r31); + xxx<31:16>
         20C66000 [005ADC]   241i 	lda	p6,<<pal__logout_base> & ^XFFFF>(p6) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         40A60405 [005AE0]   730I 	addq	p5, p6, p5				; (size*whami) + base
         20A50100 [005AE4]   731I 	lda	p5, MCHK__BASE(p5)			; start of mchk area
                  [005AE8]   732I 
         7EE51058 [005AE8]   733I 	hw_stq/p p23, MCHK__EXC_ADDR(p5)		; store exc_addr
         7EF51060 [005AEC]   734I 	hw_stq/p p23, PT__STACK_PC(p_temp)		; save fault pc
                  [005AF0]   735I 
         7C851068 [005AF0]   736I 	hw_stq/p p4, MCHK__ISUM(p5)			; store isum
         7FE51030 [005AF4]   737I 	hw_stq/p r31, MCHK__DC1_SYNDROME(p5)
         7FE51038 [005AF8]   738I 	hw_stq/p r31, MCHK__DC0_SYNDROME(p5)
         7FE51040 [005AFC]   739I 	hw_stq/p r31, MCHK__C_STAT(p5)
         7FE51048 [005B00]   740I 	hw_stq/p r31, MCHK__C_STS(p5)
         7FE51028 [005B04]   741I 	hw_stq/p r31, MCHK__C_ADDR(p5)
                  [005B08]   742I 
         7FE51050 [005B08]   743I 	hw_stq/p r31, MCHK__MM_STAT(p5)			; store 0
                  [005B0C]   744I 
         7FE51018 [005B0C]   745I 	hw_stq/p r31, MCHK__I_STAT(p5)			; store 0
         7FE51020 [005B10]   746I 	hw_stq/p r31, MCHK__DC_STAT(p5)			; store 0
                  [005B14]   747I 
         47FF0414 [005B14]   748I 	bis	r31, r31, p20				; no retry
                  [005B18]   749I ;
                  [005B18]   750I ; Current state
                  [005B18]   751I ;
                  [005B18]   752I ;	p5	base of mchk area
                  [005B18]   753I ;	p20	retry flag
                  [005B18]   754I ;
         C3E0017F [005B18]   755I 	br	r31, sys__mchk_header			; go build frame
                  [005B1C]   757  
                  [005B1C]   758  .if eq reference_platform
                  [005B1C]   759  
                  [005B1C]   760      .if eq force_path				; 1.41
                  [005B1C]   761  	hw_ret	(p23)				; return
                  [005B1C]   762      .iff
                  [005B1C]   763  	ALIGN_FETCH_BLOCK <^x47FF041F>		; 1.42 align
                  [005B1C]   764  	PVC_VIOLATE <1007>
                  [005B1C]   765  	PVC_VIOLATE <1020>			; stop permutation
                  [005B1C]   766  	hw_jmp	(p23)				; return with jmp
                  [005B1C]   767  	br	r31, .-4			; stop predictor
                  [005B1C]   768      .endc					; 1.41
                  [005B1C]   769  
                  [005B1C]   770  .endc
                  [005B1C]   771  
                  [005B1C]   772  
                  [005B1C]   773  ;+
                  [005B1C]   774  ; sys__interrupt_sl
                  [005B1C]   775  ;
                  [005B1C]   776  ; Function:
                  [005B1C]   777  ;	Handle serial line interrupt. Ack the interrupt.
                  [005B1C]   778  ;	The rest of the exercise is left to the platform programmer.
                  [005B1C]   779  ; Entry:
                  [005B1C]   780  ;	p23	exc_addr
                  [005B1C]   781  ;	p4	ev6__isum
                  [005B1C]   782  ;-
                  [005B1C]   783  	ALIGN_FETCH_BLOCK
File: ev6_pal_macros.mar
         00000000 [005B1C]   267i 	.align 4
File: ev6_osf_system_pal.mar
                  [005B20]   784  sys__interrupt_sl:
                  [005B20]   785  .if ne reference_platform
                  [005B20]   786  	lda	p7, 1(r31)			; get a 1
                  [005B20]   787  	sll	p7, #EV6__HW_INT_CLR__SL__S, p7	; shift into position to ack
                  [005B20]   788  	hw_mtpr	p7, EV6__HW_INT_CLR		; (4,0L) ack the interrupt
                  [005B20]   789  	bis	r31, r31, r31			; fill out fetch block
                  [005B20]   790  
                  [005B20]   791  	hw_mtpr	p7, EV6__HW_INT_CLR		; (4,0L) ack the interrupt
                  [005B20]   792  						; (pvc #35)
                  [005B20]   793  
                  [005B20]   794      .if eq force_path				; 1.41
                  [005B20]   795  	hw_ret_stall (p23)			; return
                  [005B20]   796      .iff
                  [005B20]   797  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align
                  [005B20]   798  	PVC_VIOLATE <1007>
                  [005B20]   799  	PVC_VIOLATE <1020>			; stop permutation
                  [005B20]   800  	hw_jmp_stall (p23)			; return with jmp
                  [005B20]   801  	br	r31, .-4			; stop predictor
                  [005B20]   802      .endc					; 1.41
                  [005B20]   803  
                  [005B20]   804  .iff
                  [005B20]   805  
                  [005B20]   806      .if eq force_path				; 1.41
                  [005B20]   807  	hw_ret_stall (p23)			; return
                  [005B20]   808      .iff
                  [005B20]   809  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align
                  [005B20]   810  	PVC_VIOLATE <1007>
                  [005B20]   811  	PVC_VIOLATE <1020>			; stop permutation
                  [005B20]   812  	hw_jmp_stall (p23)			; return with jmp
                  [005B20]   813  	br	r31, .-4			; stop predictor
                  [005B20]   814      .endc					; 1.41
                  [005B20]   815  
                  [005B20]   816  .endc
         20FF0001 [005B20]   786I 	lda	p7, 1(r31)			; get a 1
         48E41727 [005B24]   787I 	sll	p7, #EV6__HW_INT_CLR__SL__S, p7	; shift into position to ack
         77E70E10 [005B28]   788I 	hw_mtpr	p7, EV6__HW_INT_CLR		; (4,0L) ack the interrupt
         47FF041F [005B2C]   789I 	bis	r31, r31, r31			; fill out fetch block
                  [005B30]   790I 
         77E70E10 [005B30]   791I 	hw_mtpr	p7, EV6__HW_INT_CLR		; (4,0L) ack the interrupt
                  [005B34]   792I 						; (pvc #35)
                  [005B34]   793I 
                  [005B34]   794I     .if eq force_path				; 1.41
                  [005B34]   795I 	hw_ret_stall (p23)			; return
                  [005B34]   796I     .iff
                  [005B34]   797I 	ALIGN_FETCH_BLOCK <^x47FF041F>		; align
                  [005B34]   798I 	PVC_VIOLATE <1007>
                  [005B34]   799I 	PVC_VIOLATE <1020>			; stop permutation
                  [005B34]   800I 	hw_jmp_stall (p23)			; return with jmp
                  [005B34]   801I 	br	r31, .-4			; stop predictor
                  [005B34]   802I     .endc					; 1.41
         7BF7A000 [005B34]   795I 	hw_ret_stall (p23)			; return
                  [005B38]   803I     
                  [005B38]   817  
                  [005B38]   818  ;+
                  [005B38]   819  ; sys__interrupt_pc
                  [005B38]   820  ;
                  [005B38]   821  ; Function:
                  [005B38]   822  ;	Handle performance counter interrupts.
                  [005B38]   823  ; Entry:
                  [005B38]   824  ;	p23	exc_addr
                  [005B38]   825  ;	p4	ev6__isum
                  [005B38]   826  ;-
                  [005B38]   827  sys__interrupt_pc:
         7EF51060 [005B38]   828  	hw_stq/p p23, PT__STACK_PC(p_temp)	; store pc for post
         47E09405 [005B3C]   829  	bis	r31, #OSF_A0_INT__PERFMON, p5	; mark perfmon
         7CB51068 [005B40]   830  	hw_stq/p p5, PT__NEW_A0(p_temp)		; save new a0 away
         20FF0650 [005B44]   831  	lda	p7, SCB__PERFMON(r31)		; SCB offset
         7CF51070 [005B48]   832  	hw_stq/p p7, PT__NEW_A1(p_temp)		; store it for post
                  [005B4C]   833  
         47FF0406 [005B4C]   834  	bis	r31, r31, p6			; assume pc0, r4 will be 0
         4883D685 [005B50]   835  	srl	p4, #<EV6__ISUM__PC__S+1>, p5	; get pc1 bit
         44A03286 [005B54]   836  	cmovlbs	p5, #1, p6			; if pc1, r4 will be 1
         7CD51078 [005B58]   837  	hw_stq/p p6, PT__NEW_A2(p_temp)		; indicate which counter
                  [005B5C]   838  
         20FF0001 [005B5C]   839  	lda	p7, 1(r31)			; get a 1
         48E60727 [005B60]   840  	sll	p7, p6, p7			; bit 0 if pc0, bit 1 if pc1
         48E3B727 [005B64]   841  	sll	p7, #EV6__HW_INT_CLR__PC__S, p7	; move into position to ack
                  [005B68]   842  	PVC_VIOLATE <35>
File: ev6_pal_macros.mar
                  [005B68]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E70E10 [005B68]   843  	hw_mtpr	p7, EV6__HW_INT_CLR		; (4,0L) ack the interrupt
                  [005B6C]   844  
         20DF0006 [005B6C]   845  	lda	p6, OSF_IPL__PERFMON(r31)	; ipl for performance counter
         C3E00000 [005B70]   846  	br	r31, sys__int_post		; post interrupt
                  [005B74]   847  
                  [005B74]   848  ;+
                  [005B74]   849  ; sys__int_post
                  [005B74]   850  ;
                  [005B74]   851  ; Function:
                  [005B74]   852  ;	Post interrupt.
                  [005B74]   853  ;
                  [005B74]   854  ; Current state:
                  [005B74]   855  ;	p6		new IPL
                  [005B74]   856  ;
                  [005B74]   857  ;	PT__STACK_PC	exc_addr
                  [005B74]   858  ;	PT__NEW_A0	type
                  [005B74]   859  ;	PT__NEW_A1	interrupt vector
                  [005B74]   860  ;	PT__NEW_A2	mchk => kseg pointer to logout area
                  [005B74]   861  ;			perfmon => pc indicator
                  [005B74]   862  ;-
                  [005B74]   863  sys__int_post:
         46C11004 [005B74]   864  	and	p_misc, #<1@OSF_P_MISC__CM__S>, p4	; current mode
         46C1F014 [005B78]   865  	and	p_misc, #OSF_P_MISC__PS__M, p20		; save original ps
         E4800007 [005B7C]   866  	beq	p4, sys__int_post_cm_done		; skip switch if kernel
                  [005B80]   867  ;
                  [005B80]   868  ; Switch to kernel mode.
                  [005B80]   869  ;
                  [005B80]   870  post_cm_offset = <sys__int_post_cm_done - sys__int_post_cm>
                  [005B80]   871  
         7FD51020 [005B80]   872  	hw_stq/p r30, PT__USP(p_temp)			; save user SP
         6FD51018 [005B84]   873  	hw_ldq/p r30, PT__KSP(p_temp)			; get kernel SP
                  [005B88]   874  
         C0800000 [005B88]   875  	br	p4, sys__int_post_cm			; change mode to kernel
                  [005B8C]   876  sys__int_post_cm:
         40823404 [005B8C]   877  	addq	p4, #<post_cm_offset+1>, p4		; jump past in palmode
         77FF0910 [005B90]   878  	hw_mtpr	r31, EV6__PS				; (4,0L) switch to kern
         D3E00000 [005B94]   879  	bsr	r31, .					; push prediction stack
                  [005B98]   880  	PVC_JSR	post_cm					; synch up
File: ev6_pal_macros.mar
                  [005B98]   531i  pvc_lbl \pcv_index, \pcv_jsr_post_cm0, osf
File: ev6_osf_system_pal.mar
         7BE4A000 [005B98]   881  	hw_ret_stall (p4)				; pop prediction stack
                  [005B9C]   882  	PVC_JSR	post_cm, dest=1
File: ev6_pal_macros.mar
                  [005B9C]   534i  pvc_lbl \pcv_index, \pcv_jsr_post_cm0, osf, \pcv_jsr_post_cm0_inst
File: ev6_osf_system_pal.mar
                  [005B9C]   883  sys__int_post_cm_done:
                  [005B9C]   884  
         46C1F116 [005B9C]   885  	bic	p_misc, #OSF_P_MISC__PS__M, p_misc	; clear PS
         46C60416 [005BA0]   886  	bis	p_misc, p6, p_misc			; cm=0, ipl=p6
                  [005BA4]   887  
         649F1010 [005BA4]   888  	hw_mfpr	p4, EV6__PAL_BASE		; (4,0L) get pal base
         40C40644 [005BA8]   889  	s8addq	p6, p4, p4			; pal base + index
         20840D00 [005BAC]   890  	lda	p4, ipl_offset(p4)		; pal base + table base + index
         6C841000 [005BB0]   891  	hw_ldq/p p4, (p4)			; get new ier
         77E40A10 [005BB4]   892  	hw_mtpr	p4, EV6__IER			; (4,0L) write new ier
                  [005BB8]   893  
         23DEFFD0 [005BB8]   894  	lda	r30, <0-OSF_FRM__SIZE>(r30)		; allocate stack space
                  [005BBC]   895  
         B69E0000 [005BBC]   896  	stq	p20, OSF_FRM__PS(r30)			; save original ps
         B65E0028 [005BC0]   897  	stq	r18, OSF_FRM__A2(r30)			; save a2
                  [005BC4]   898  
         6E951060 [005BC4]   899  	hw_ldq/p p20, PT__STACK_PC(p_temp)		; 1.39 get exc_addr back
                  [005BC8]   900  
         B7BE0010 [005BC8]   901  	stq	r29, OSF_FRM__GP(r30)			; save gp
         B61E0018 [005BCC]   902  	stq	r16, OSF_FRM__A0(r30)			; save a0
         B63E0020 [005BD0]   903  	stq	r17, OSF_FRM__A1(r30)			; save a1
         B69E0008 [005BD4]   904  	stq	p20, OSF_FRM__PC(r30)			; 1.39 save exc_addr
                  [005BD8]   905  
         6EF51040 [005BD8]   906  	hw_ldq/p p23, PT__ENT_INT(p_temp)		; get entry point
         6FB51028 [005BDC]   907  	hw_ldq/p r29, PT__KGP(p_temp)			; get kgp
         6E151068 [005BE0]   908  	hw_ldq/p r16, PT__NEW_A0(p_temp)		; a0 <- type
         6E351070 [005BE4]   909  	hw_ldq/p r17, PT__NEW_A1(p_temp)		; a1 <- vector
         6E551078 [005BE8]   910  	hw_ldq/p r18, PT__NEW_A2(p_temp)		; a2 <- ptr to logout
                  [005BEC]   911  							; 	or pc indicator
         7BF7A000 [005BEC]   912  	hw_ret_stall	(p23)				; to os
                  [005BF0]   913  
                  [005BF0]   914  ;+
                  [005BF0]   915  ; CRD interrupt.
                  [005BF0]   916  ;
                  [005BF0]   917  ; On DC_STAT<ECC_ERR_LD> and C_STAT <> 0, the hardware guarantees a good local
                  [005BF0]   918  ; copy. But on bcache and memory errors, we should scrub and store to make
                  [005BF0]   919  ; sure memory will be cleaned eventually.
                  [005BF0]   920  ;
                  [005BF0]   921  ; Also, non-target quadwords are not corrected at all, so that's
                  [005BF0]   922  ; another good reason to scrub.
                  [005BF0]   923  ;
                  [005BF0]   924  ; If DC_STAT<ECC_ERR_LD> and C_STAT = 0, we got a error on a speculative load.
                  [005BF0]   925  ; or on a bcache victim on a dcache/bcache miss. If C_STAT = 0, we don't get a
                  [005BF0]   926  ; C_ADDR, so we can't scrub.
                  [005BF0]   927  ;
                  [005BF0]   928  ; We can also enter here via a crd that signals we got a ISTREAM_MEM_ERR
                  [005BF0]   929  ; or ISTREAM_BC_ERR mchk down a bad path. We need to scrub the error in this
                  [005BF0]   930  ; case also.
                  [005BF0]   931  ;
                  [005BF0]   932  ; We can also enter here with a double bit error that has slipped into
                  [005BF0]   933  ; c_stat after we took the crd. So look for that case, and take a mchk
                  [005BF0]   934  ; if so. Note that c_stat double bit error bit is not locked, so we
                  [005BF0]   935  ; can detect this condition.
                  [005BF0]   936  ;
                  [005BF0]   937  ; Current state:
                  [005BF0]   938  ;	p23		exc_addr
                  [005BF0]   939  ;-
                  [005BF0]   940  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [005BF0]   275i 	.align 6
00000000 00000000 [005BF8]
File: ev6_osf_system_pal.mar
                  [005C00]   941  sys__crd:
                  [005C00]   942  ;
                  [005C00]   943  ; First, fetch the cbox error chain, unlocking the error in the process.
                  [005C00]   944  ;
                  [005C00]   945      .if eq force_path			; 1.41
                  [005C00]   946  	PVC_JSR	cbox, bsr=1
                  [005C00]   947  	bsr	p5, sys__cbox
                  [005C00]   948      .iff
                  [005C00]   949  	br	p5, sys__cbox
                  [005C00]   950  	PVC_JSR cbox_hack, dest=1
                  [005C00]   951      .endc				; 1.41
                  [005C00]   946I 	PVC_JSR	cbox, bsr=1
File: ev6_pal_macros.mar
                  [005C00]   531i  pvc_lbl \pcv_index, \pcv_jsr_cbox0, osf
File: ev6_osf_system_pal.mar
         D0A001FB [005C00]   947I 	bsr	p5, sys__cbox
                  [005C04]   952      ;
                  [005C04]   953  ; First check for a double bit error that came in just after the
                  [005C04]   954  ; single bit error.
                  [005C04]   955  ;
                  [005C04]   956  ; Current state:
                  [005C04]   957  ;	p5		available
                  [005C04]   958  ;	p20<43:39>	c_stat<4:0>
                  [005C04]   959  ;
         4A829725 [005C04]   960  	sll	p20, #<64-<CHAIN__STAT__S+CHAIN__STAT__V>>, p5
         48A77685 [005C08]   961  	srl	p5, #<64-CHAIN__STAT__V>, p5		; get c_stat
         44A21005 [005C0C]   962  	and	p5, #<1@EV6__C_STAT__DOUBLE__S>, p5	; check for dbl
         F4A000FC [005C10]   963  	bne	p5, sys__mchk__double_bit		; mchk if so
                  [005C14]   964  ;
                  [005C14]   965  ; Now continue with logout.
                  [005C14]   966  ;
                  [005C14]   967  ; Current state:
                  [005C14]   968  ;	p4		scratched
                  [005C14]   969  ;	p6		scratched
                  [005C14]   970  ;	p20<59:52>	dc1_syndrome<7:0>
                  [005C14]   971  ;	   <51:44>	dc0_syndrome<7:0>
                  [005C14]   972  ;	   <43:39>	c_stat<4:0>
                  [005C14]   973  ;	   <38:35>	c_sts<3:0>
                  [005C14]   974  ;	p23		exc_addr
                  [005C14]   975  ;
                  [005C14]   976  ;	pass1
                  [005C14]   977  ;	-----
                  [005C14]   978  ;	p7 <44:08>	c_addr<6:42>
                  [005C14]   979  ;	   <07:06>	raz
                  [005C14]   980  ;	   <05:00>	UNDEFINED
                  [005C14]   981  ;	pass2
                  [005C14]   982  ;	-----
                  [005C14]   983  ;	p7 <40:04>	c_addr<6:42>
                  [005C14]   984  ;	   <03:00>	raz
                  [005C14]   985  ;
         7EF51060 [005C14]   986  	hw_stq/p p23, PT__STACK_PC(p_temp)	; exc_addr for post, free up reg
                  [005C18]   987  
         4AC050D7 [005C18]   988  	extbl	p_misc, #2, p23			; get mces
         4ACF1616 [005C1C]   989  	zap	p_misc, #^x78, p_misc		; clean mchk_code and SCBv
                  [005C20]   990  
         4AE07686 [005C20]   991  	srl	p23, #MCES__DPC__S, p6		; get dpc
         F0C00085 [005C24]   992  	blbs	p6, sys__crd_skip_frame		; dpc => don't build frame
                  [005C28]   993  
         46E09406 [005C28]   994  	bis	p23, #<1@MCES__PCE__S>, p6		; set MCES<PCE>
         48C21726 [005C2C]   995  	sll	p6, #OSF_P_MISC__MCES__MCHK__S, p6	; shift into position
         46C60416 [005C30]   996  	bis	p_misc, p6, p_misc			; or back mces
                  [005C34]   997  
         20DF0630 [005C34]   998  	lda	p6, SCB__PROC_CORR_ERR(r31)		; SCB vector
         48C31726 [005C38]   999  	sll	p6, #OSF_P_MISC__SCBV__S, p6		; move SCBv into position
         46C60416 [005C3C]  1000  	bis	p_misc, p6, p_misc			; or back scbv
                  [005C40]  1001  
         20DF0086 [005C40]  1002  	lda	p6, MCHK__CORR_ECC(r31)			; mchk code
         48C51726 [005C44]  1003  	sll	p6, #OSF_P_MISC__MCHK_CODE__S, p6	; mchk code into position
         46C60416 [005C48]  1004  	bis	p_misc, p6, p_misc			; or back mchk code
                  [005C4C]  1005  ;
                  [005C4C]  1006  ; Now compute where the frame is.
                  [005C4C]  1007  ;
                  [005C4C]  1008  ; Current state:
                  [005C4C]  1009  ;	p7	cbox error chain info
                  [005C4C]  1010  ;	p20	cbox error chain info
                  [005C4C]  1011  ;	p23	old mces
                  [005C4C]  1012  ;
         6C951098 [005C4C]  1013  	hw_ldq/p p4, PT__WHAMI(p_temp)			; get whami
                  [005C50]  1014  
         20BF0400 [005C50]  1015  	lda	p5, PAL__LOGOUT_SPECIFIC_SIZE(r31)	; short&long size
         4C850405 [005C54]  1016  	mulq	p4, p5, p5				; * whami
                  [005C58]  1017  
                  [005C58]  1018  	GET_32CONS	p6, PAL__LOGOUT_BASE, r31	; logout base
File: ev6_pal_macros.mar
                  [005C58]   239i  ASSUME <pal__logout_base> le  <^x7FFFFFFF>
         24DF0000 [005C58]   240M 	ldah	p6,<<pal__logout_base>+32768>@-16(r31); + xxx<31:16>
         20C66000 [005C5C]   241M 	lda	p6,<<pal__logout_base> & ^XFFFF>(p6) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         40A60405 [005C60]  1019  	addq	p5, p6, p5				; (size*whami) + base
         20A50000 [005C64]  1020  	lda	p5, MCHK_CRD__BASE(p5)			; start of mchk crd area
                  [005C68]  1021  
         4AE05686 [005C68]  1022  	srl	p23, #MCES__PCE__S, p6			; get PCE
         F0C00070 [005C6C]  1023  	blbs	p6, sys__crd_second			; set => second error
                  [005C70]  1024  
                  [005C70]  1025  ;
                  [005C70]  1026  ; Now construct the cbox error registers and log them.
                  [005C70]  1027  ; Current state:
                  [005C70]  1028  ;
                  [005C70]  1029  ;	p5		base of crd logout frame
                  [005C70]  1030  ;
                  [005C70]  1031  ;	p7		c_addr
                  [005C70]  1032  ;
                  [005C70]  1033  ;	p20<59:52>	dc1_syndrome<7:0>
                  [005C70]  1034  ;	   <51:44>	dc0_syndrome<7:0>
                  [005C70]  1035  ;	   <43:39>	c_stat<4:0>
                  [005C70]  1036  ;	   <38:35>	c_sts<3:0>
                  [005C70]  1037  ;
                  [005C70]  1038  ;	p23		old mces
                  [005C70]  1039  ;
                  [005C70]  1040  ;	p_misc		updated with new mces, SCB, mchk code
                  [005C70]  1041  ;
                  [005C70]  1042  
                  [005C70]  1043  CHAIN__DC1__S	= 52
                  [005C70]  1044  CHAIN__DC1__V	= 8
                  [005C70]  1045  CHAIN__DC0__S	= 44
                  [005C70]  1046  CHAIN__DC0__V	= 8
                  [005C70]  1047  CHAIN__STAT__S	= 39
                  [005C70]  1048  CHAIN__STAT__V	= 5
                  [005C70]  1049  CHAIN__STS__S	= 35
                  [005C70]  1050  CHAIN__STS__V	= 4
                  [005C70]  1051  
                  [005C70]  1052  sys__crd_arrange_cbox:
         4A809724 [005C70]  1053  	sll	p20, #<64-<CHAIN__DC1__S+CHAIN__DC1__V>>, p4
         48871684 [005C74]  1054  	srl	p4, #<64-CHAIN__DC1__V>, p4
         7C851030 [005C78]  1055  	hw_stq/p p4, MCHK_CRD__DC1_SYNDROME(p5)			; store syn1
                  [005C7C]  1056  
         4A819724 [005C7C]  1057  	sll	p20, #<64-<CHAIN__DC0__S+CHAIN__DC0__V>>, p4
         48871684 [005C80]  1058  	srl	p4, #<64-CHAIN__DC0__V>, p4
         7C851038 [005C84]  1059  	hw_stq/p p4, MCHK_CRD__DC0_SYNDROME(p5)			; store syn0
                  [005C88]  1060  
         4A829724 [005C88]  1061  	sll	p20, #<64-<CHAIN__STAT__S+CHAIN__STAT__V>>, p4
         48877684 [005C8C]  1062  	srl	p4, #<64-CHAIN__STAT__V>, p4
         7C851040 [005C90]  1063  	hw_stq/p p4, MCHK_CRD__C_STAT(p5)			; store stat
                  [005C94]  1064  
         4A833724 [005C94]  1065  	sll	p20, #<64-<CHAIN__STS__S+CHAIN__STS__V>>, p4
         48879684 [005C98]  1066  	srl	p4, #<64-CHAIN__STS__V>, p4
         7C851048 [005C9C]  1067  	hw_stq/p p4, MCHK_CRD__C_STS(p5)			; store sts
                  [005CA0]  1068  ;
                  [005CA0]  1069  ; Now get the error address.
                  [005CA0]  1070  ;
                  [005CA0]  1071  ; Current state:
                  [005CA0]  1072  ;
                  [005CA0]  1073  ;	p5		base of crd logout frame
                  [005CA0]  1074  ;
                  [005CA0]  1075  ;	pass1
                  [005CA0]  1076  ;	-----
                  [005CA0]  1077  ;	p7 <44:08>	c_addr<6:42>
                  [005CA0]  1078  ;	   <07:06>	raz
                  [005CA0]  1079  ;	   <05:00>	UNDEFINED
                  [005CA0]  1080  ;	pass2
                  [005CA0]  1081  ;	-----
                  [005CA0]  1082  ;	p7 <40:04>	c_addr<6:42>
                  [005CA0]  1083  ;	   <03:00>	raz
                  [005CA0]  1084  ;
                  [005CA0]  1085  
                  [005CA0]  1086  .if ne ev6_p1
                  [005CA0]  1087  	C_ADDR_SHIFT = 45
                  [005CA0]  1088  	and	p7, #^x3F, p7			; zap UNDEFINED bits
                  [005CA0]  1089  .iff
                  [005CA0]  1090  	C_ADDR_SHIFT = 41
                  [005CA0]  1091  .endc
                  [005CA0]  1090I 	C_ADDR_SHIFT = 41
                  [005CA0]  1092  
         43E53406 [005CA0]  1093  	addq	r31, #C_ADDR_SHIFT, p6		; initialize shift count
         43FF0404 [005CA4]  1094  	addq	r31, r31, p4			; initialize output shift data
                  [005CA8]  1095  
                  [005CA8]  1096  sys__crd_addr:
         44E03014 [005CA8]  1097  	and	p7, #1, p20			; clear all but bit 0
         42840404 [005CAC]  1098  	addq	p20, p4, p4			; accumulate output shift data
         40C03526 [005CB0]  1099  	subq	p6, #1, p6			; decrement shift count
         E4C00003 [005CB4]  1100  	beq	p6, sys__crd_addr_done		; all done
                  [005CB8]  1101  
         48803724 [005CB8]  1102  	sll 	p4, #1, p4			; shift output data 1 bit left
         48E03687 [005CBC]  1103  	srl 	p7, #1, p7			; shift input data 1 bit right
         C3FFFFF9 [005CC0]  1104  	br	r31, sys__crd_addr		; do next shift
                  [005CC4]  1105  
                  [005CC4]  1106  sys__crd_addr_done:
         4880D724 [005CC4]  1107  	sll 	p4, #6, p4			; shift error address 6 bits left
         7C851028 [005CC8]  1108  	hw_stq/p p4, MCHK_CRD__C_ADDR(p5)	; store addr
                  [005CCC]  1109  ;
                  [005CCC]  1110  ; Save off a clean mm_state.
                  [005CCC]  1111  ;
         7FE51050 [005CCC]  1112  	hw_stq/p r31, MCHK_CRD__MM_STAT(p5)	; store 0 for mm_stat
                  [005CD0]  1113  ;
                  [005CD0]  1114  ;
                  [005CD0]  1115  ; Fetch I_STAT, DC_STAT. Clear I_STAT. Clear only crd-type errors in DC_STAT, in
                  [005CD0]  1116  ; case we need to take a delayed dstream mchk once we are out of PALmode.
                  [005CD0]  1117  ;
                  [005CD0]  1118  ; Then check to see if we need to scrub.
                  [005CD0]  1119  ; The cases:
                  [005CD0]  1120  ;	C_STAT<ISTREAM_xx_ERR>
                  [005CD0]  1121  ;	DC_STAT<ECC_ERR_LD> and C_STAT <> 0 and C_STAT <> DSTREAM_DC_ERR
                  [005CD0]  1122  ;
                  [005CD0]  1123  ; Current state:
                  [005CD0]  1124  ;	p5	base of crd logout frame
                  [005CD0]  1125  ;
                  [005CD0]  1126  ;
                  [005CD0]  1127  	EV6__DC_STAT__W1C_CRD = -
                  [005CD0]  1128  		<<1@EV6__DC_STAT__ECC_ERR_ST__S> ! -
                  [005CD0]  1129  		<1@EV6__DC_STAT__ECC_ERR_LD__S>>
                  [005CD0]  1130  
                  [005CD0]  1131  	DSTREAM_DC_ERR = 5
                  [005CD0]  1132  ;
                  [005CD0]  1133  ; The ev6_p2 definition will still work for ev6_p3. Bit ^x1e becomes
                  [005CD0]  1134  ; a RO bit for the new performance counter implementation.
                  [005CD0]  1135  ;
                  [005CD0]  1136  .if ne ev6_p3
                  [005CD0]  1137  	EV6__I_STAT__PAR__S = ^x1d
                  [005CD0]  1138  	EV6__I_STAT__W1C = -
                  [005CD0]  1139  		<<1@EV6__I_STAT__PAR__S>>
                  [005CD0]  1140  .iff
                  [005CD0]  1141  	EV6__I_STAT__TPE__S = ^x1d
                  [005CD0]  1142  	EV6__I_STAT__DPE__S = ^x1e
                  [005CD0]  1143  	EV6__I_STAT__W1C = -
                  [005CD0]  1144  		<<1@EV6__I_STAT__TPE__S> ! -
                  [005CD0]  1145  		<1@EV6__I_STAT__DPE__S>>
                  [005CD0]  1146  .endc
                  [005CD0]  1141I 	EV6__I_STAT__TPE__S = ^x1d
                  [005CD0]  1142I 	EV6__I_STAT__DPE__S = ^x1e
                  [005CD0]  1143I 	EV6__I_STAT__W1C = -
                  [005CD0]  1144I 		<<1@EV6__I_STAT__TPE__S> ! -
                  [005CD0]  1145I 		<1@EV6__I_STAT__DPE__S>>
                  [005CD0]  1147  
         649F1610 [005CD0]  1148  	hw_mfpr p4, EV6__I_STAT				; (4,0L) get i_stat
         64DF2A40 [005CD4]  1149  	hw_mfpr	p6, EV6__DC_STAT			; (6,0L) get dc_stat
         7C851018 [005CD8]  1150  	hw_stq/p p4, MCHK_CRD__I_STAT(p5)		; store i_stat
         7CC51020 [005CDC]  1151  	hw_stq/p p6, MCHK_CRD__DC_STAT(p5)		; store dc_stat
                  [005CE0]  1152  
                  [005CE0]  1153  	GET_32CONS 	p4, EV6__I_STAT__W1C, r31
File: ev6_pal_macros.mar
                  [005CE0]   239i  ASSUME <ev6__i_stat__w1c> le  <^x7FFFFFFF>
         249F6000 [005CE0]   240M 	ldah	p4,<<ev6__i_stat__w1c>+32768>@-16(r31); + xxx<31:16>
         20840000 [005CE4]   241M 	lda	p4,<<ev6__i_stat__w1c> & ^XFFFF>(p4) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E41610 [005CE8]  1154  	hw_mtpr	p4, EV6__I_STAT				; (4,0L)
                  [005CEC]  1155  
                  [005CEC]  1156  	GET_16CONS	p4, EV6__DC_STAT__W1C_CRD, r31
File: ev6_pal_macros.mar
                  [005CEC]   249M 	ASSUME <<ev6__dc_stat__w1c_crd>> le  <^x7FFF>
         209F000C [005CEC]   250M 	lda	p4,<ev6__dc_stat__w1c_crd>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E42A40 [005CF0]  1157  	hw_mtpr p4, EV6__DC_STAT			; (6,0L)
                  [005CF4]  1158  	
         6E851040 [005CF4]  1159  	hw_ldq/p p20, MCHK_CRD__C_STAT(p5)		; get c_stat back
         E6800036 [005CF8]  1160  	beq	p20, sys__crd_merge			; if zero, can't scrub
                  [005CFC]  1161  
         46811004 [005CFC]  1162  	and	p20, #<1@EV6__C_STAT__ISTREAM__S>, p4	; check for istream
         F4800005 [005D00]  1163  	bne	p4, sys__crd_do_scrub			; scrub if so
                  [005D04]  1164  
         4280B5A4 [005D04]  1165  	cmpeq	p20, #DSTREAM_DC_ERR, p4		; check for dcache
         F4800032 [005D08]  1166  	bne	p4, sys__crd_merge			; don't scrub if so
                  [005D0C]  1167  
         44C11004 [005D0C]  1168  	and	p6, #<1@EV6__DC_STAT__ECC_ERR_LD__S>, p4; check for ld
         F4800001 [005D10]  1169  	bne	p4, sys__crd_do_scrub			; scrub if so
         C3E0002F [005D14]  1170  	br	r31, sys__crd_merge			; don't scrub if not 
                  [005D18]  1171  ;
                  [005D18]  1172  ; Scrub the error.
                  [005D18]  1173  ; Current state:
                  [005D18]  1174  ;	p5	base of crd logout frame
                  [005D18]  1175  ;
                  [005D18]  1176  
                  [005D18]  1177  sys__crd_do_scrub:
         6C851028 [005D18]  1178  	hw_ldq/p p4, MCHK_CRD__C_ADDR(p5)	; get address back
                  [005D1C]  1179  
         77FFA380 [005D1C]  1180  	hw_mtpr	r31, EV6__DTB_IA		; (7,1L) flush dtb
         229F3301 [005D20]  1181  	lda	p20, ^x3301(r31)		; set WE, RE
         47FF041F [005D24]  1182  	bis	r31, r31, r31
         47FF041F [005D28]  1183  	bis	r31, r31, r31
                  [005D2C]  1184  
         77FF2780 [005D2C]  1185  	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; wait for retire
         4881B686 [005D30]  1186  	srl	p4, #13, p6			; shift byte offset
         48C41726 [005D34]  1187  	sll	p6, #EV6__DTB_PTE0__PFN__S, p6	; shift into position
         44D40406 [005D38]  1188  	bis	p6, p20, p6			; produce pte
                  [005D3C]  1189  
                  [005D3C]  1190  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
         47FF041F [005D3C]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_system_pal.mar
                  [005D40]  1191  
                  [005D40]  1192  	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [005D40]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E42044 [005D40]  1193  	hw_mtpr	p4, EV6__DTB_TAG0		; (2&6,0L) write tag0
         77E4A022 [005D44]  1194  	hw_mtpr p4, EV6__DTB_TAG1		; (1&5,1L) write tag1
         77E62155 [005D48]  1195  	hw_mtpr	p6, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
         77E6A1AA [005D4C]  1196  	hw_mtpr	p6, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [005D50]  1197  
         77FF2780 [005D50]  1198  	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; 1.41 wait for retire
                  [005D54]  1199  
         63FF4000 [005D54]  1200  	mb					; quiet before we start
                  [005D58]  1201      .if eq force_path			; 1.41
                  [005D58]  1202  	PVC_JSR scrub, bsr=1
                  [005D58]  1203  	bsr	p7, sys__crd_scrub
                  [005D58]  1204      .iff
                  [005D58]  1205  	br	p7, sys__crd_scrub
                  [005D58]  1206  	PVC_JSR scrub_hack, dest=1
                  [005D58]  1207      .endc				; 1.41
                  [005D58]  1202I 	PVC_JSR scrub, bsr=1
File: ev6_pal_macros.mar
                  [005D58]   531i  pvc_lbl \pcv_index, \pcv_jsr_scrub0, osf
File: ev6_osf_system_pal.mar
         D0E00009 [005D58]  1203I 	bsr	p7, sys__crd_scrub
                  [005D5C]  1208      
         77FFA380 [005D5C]  1209  	hw_mtpr	r31, EV6__DTB_IA		; (7,1L) flush dtb
         47FF041F [005D60]  1210  	bis	r31, r31, r31
         47FF041F [005D64]  1211  	bis	r31, r31, r31
         47FF041F [005D68]  1212  	bis	r31, r31, r31
                  [005D6C]  1213  
         77FF2780 [005D6C]  1214  	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; wait for retire
         C3E00018 [005D70]  1215  	br	r31, sys__crd_merge
                  [005D74]  1216  ;+
                  [005D74]  1217  ; sys__crd_scrub
                  [005D74]  1218  ;
                  [005D74]  1219  ; Called from above and from dpc and pce cases.
                  [005D74]  1220  ; After the scrub, read the cbox chain again.
                  [005D74]  1221  ; The scrub will cause a crd, but will get cleared along with the
                  [005D74]  1222  ; calling code's clear of hw_int_clr.
                  [005D74]  1223  ;
                  [005D74]  1224  ; Current state:
                  [005D74]  1225  ;	mb	preceded this call
                  [005D74]  1226  ;	p4	address to scrub
                  [005D74]  1227  ;	p5	base of crd logout frame
                  [005D74]  1228  ;	p7	return address
                  [005D74]  1229  ; Exit state:
                  [005D74]  1230  ;	p5	base of crd logout frame
                  [005D74]  1231  ;		calling code needs to clear hw_int_clr
                  [005D74]  1232  ;-
                  [005D74]  1233  
                  [005D74]  1234  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [005D74]   275i 	.align 6
         00000000 [005D7C]
File: ev6_osf_system_pal.mar
                  [005D80]  1235  sys__crd_scrub:
         A4C40000 [005D80]  1236  	ldq	p6, ^x00(p4)			; re-read the bad block QW #0
         A4C40008 [005D84]  1237  	ldq	p6, ^x08(p4)			; re-read the bad block QW #1
         A4C40010 [005D88]  1238  	ldq	p6, ^x10(p4)			; re-read the bad block QW #2
         A4C40018 [005D8C]  1239  	ldq	p6, ^x18(p4)			; re-read the bad block QW #3
         A4C40020 [005D90]  1240  	ldq	p6, ^x20(p4)			; re-read the bad block QW #4
         A4C40028 [005D94]  1241  	ldq	p6, ^x28(p4)			; re-read the bad block QW #5
         A4C40030 [005D98]  1242  	ldq	p6, ^x30(p4)			; re-read the bad block QW #6
         63FF4000 [005D9C]  1243  	mb					; no other mem-ops till done
         ACC40038 [005DA0]  1244  	ldq_l	p6, ^x38(p4)			; re-read the bad block QW #7
         BCC40038 [005DA4]  1245  	stq_c	p6, ^x38(p4)			; now store it to force scrub
         63FF4000 [005DA8]  1246  	mb
         44DF0006 [005DAC]  1247  	and	p6, r31, p6			; consumer of above
         E4C00001 [005DB0]  1248  	beq	p6, sys__crd_scrub_done		; these 2 lines......
                  [005DB4]  1249  	PVC_VIOLATE <1006>
File: ev6_pal_macros.mar
                  [005DB4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         C3FFFFFF [005DB4]  1250  	br	r31, .-4			; .....stop pre-fetching
                  [005DB8]  1251  sys__crd_scrub_done:
         44BF0417 [005DB8]  1252  	bis	p5, r31, p23			; save base of logout frame
         7CF510E8 [005DBC]  1253  	hw_stq/p p7, PT__R0(p_temp)		; save p7 off somewhere
                  [005DC0]  1254  
                  [005DC0]  1255      .if eq force_path				; 1.41
                  [005DC0]  1256  	PVC_JSR	cbox, bsr=1
                  [005DC0]  1257  	bsr	p5, sys__cbox			; get the cbox error chain again
                  [005DC0]  1258      .iff
                  [005DC0]  1259  	PVC_VIOLATE <1008>			; 1.42 tell pvc to skip routine
                  [005DC0]  1260  	br	p5, sys__cbox
                  [005DC0]  1261      .endc					; 1.41
                  [005DC0]  1256I 	PVC_JSR	cbox, bsr=1
File: ev6_pal_macros.mar
                  [005DC0]   531i  pvc_lbl \pcv_index, \pcv_jsr_cbox0, osf
File: ev6_osf_system_pal.mar
         D0A0018B [005DC0]  1257I 	bsr	p5, sys__cbox			; get the cbox error chain again
                  [005DC4]  1262      
         46FF0405 [005DC4]  1263  	bis	p23, r31, p5			; base of frame to p5
         6CF510E8 [005DC8]  1264  	hw_ldq/p p7, PT__R0(p_temp)		; restore p7
         44E03407 [005DCC]  1265  	bis	p7, #1, p7			; return in PALmode
                  [005DD0]  1266  
                  [005DD0]  1267      .if eq force_path				; 1.41
                  [005DD0]  1268  	PVC_JSR scrub, dest=1
                  [005DD0]  1269  	hw_ret	(p7)				; return
                  [005DD0]  1270      .iff
                  [005DD0]  1271  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align
                  [005DD0]  1272  	PVC_JSR scrub_hack
                  [005DD0]  1273  	hw_jmp	(p7)				; return with jmp
                  [005DD0]  1274  	br	r31, .-4			; stop predictor
                  [005DD0]  1275      .endc					; 1.41
                  [005DD0]  1268I 	PVC_JSR scrub, dest=1
File: ev6_pal_macros.mar
                  [005DD0]   534i  pvc_lbl \pcv_index, \pcv_jsr_scrub0, osf, \pcv_jsr_scrub0_inst
File: ev6_osf_system_pal.mar
         7BE78000 [005DD0]  1269I 	hw_ret	(p7)				; return
                  [005DD4]  1276      ;
                  [005DD4]  1277  ; Now clear the crd and dc_stat.
                  [005DD4]  1278  ;
                  [005DD4]  1279  sys__crd_merge:
         47E03407 [005DD4]  1280  	bis r31, #1, p7 			; get a 1
         48E3F727 [005DD8]  1281  	sll	p7, #EV6__HW_INT_CLR__CR__S, p7	; shift into position
                  [005DDC]  1282  	PVC_VIOLATE <35>
File: ev6_pal_macros.mar
                  [005DDC]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E70E10 [005DDC]  1283  	hw_mtpr	p7, EV6__HW_INT_CLR		; (4,0L)
                  [005DE0]  1284  
                  [005DE0]  1285  	GET_16CONS	p7, EV6__DC_STAT__W1C_CRD, r31
File: ev6_pal_macros.mar
                  [005DE0]   249M 	ASSUME <<ev6__dc_stat__w1c_crd>> le  <^x7FFF>
         20FF000C [005DE0]   250M 	lda	p7,<ev6__dc_stat__w1c_crd>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E72A40 [005DE4]  1286  	hw_mtpr p7, EV6__DC_STAT		; (6,0L)
         47FF041F [005DE8]  1287  	bis	r31, r31 ,r31
         47FF041F [005DEC]  1288  	bis	r31, r31 ,r31
         47FF041F [005DF0]  1289  	bis	r31, r31 ,r31
                  [005DF4]  1290  
         77FF2750 [005DF4]  1291  	hw_mtpr	r31, <EV6__MM_STAT ! ^x50>	; stall till they retire
                  [005DF8]  1292  ;
                  [005DF8]  1293  ; Write the first 2 quadwords of the logout area
                  [005DF8]  1294  ; Merge from system crd handling.
                  [005DF8]  1295  ;
                  [005DF8]  1296  
                  [005DF8]  1297  sys__crd_header:
         229F0001 [005DF8]  1298  	lda	p20, 1(r31)			; set retry flag
         4A87F734 [005DFC]  1299  	sll	p20, #63, p20			; shift retry into position
         22940058 [005E00]  1300  	lda	p20, MCHK_CRD__SIZE(p20)	; flag ! frame size
         7E851000 [005E04]  1301  	hw_stq/p p20, MCHK_CRD__FLAG_FRAME(p5)	; store flag ! frame size
         229F0058 [005E08]  1302  	lda	p20, MCHK_CRD__SYSTEM_BASE(r31)	; system offset ???
         4A841734 [005E0C]  1303  	sll	p20, #32, p20			; shift into position
         22940018 [005E10]  1304  	lda	p20, MCHK_CRD__CPU_BASE(p20)	; sys offset ! cpu offset
         7E851008 [005E14]  1305  	hw_stq/p p20, MCHK_CRD__OFFSETS(p5)	; store offsets
                  [005E18]  1306  ;+
                  [005E18]  1307  ; Store the pal specific information. Also add revision number.
                  [005E18]  1308  ;-
                  [005E18]  1309  ASSUME OSF_P_MISC__MCHK_CODE__S eq 40
                  [005E18]  1310  
                  [005E18]  1311  	GET_16CONS	p6, MCHK_CRD__REV, r31	; get revision
File: ev6_pal_macros.mar
                  [005E18]   249M 	ASSUME <<mchk_crd__rev>> le  <^x7FFF>
         20DF0001 [005E18]   250M 	lda	p6,<mchk_crd__rev>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         48C41726 [005E1C]  1312  	sll	p6, #32, p6			; shift into position
         4AC0B2D4 [005E20]  1313  	extwl	p_misc, #5, p20			; get mchk_code field
         46860414 [005E24]  1314  	bis	p20, p6, p20			; combine the two
         7E851010 [005E28]  1315  	hw_stq/p p20, MCHK_CRD__MCHK_CODE(p5)	; store mchk code and rev
                  [005E2C]  1316  ;+
                  [005E2C]  1317  ; Store the system-specific part of the logout frame
                  [005E2C]  1318  ;-
                  [005E2C]  1319  
                  [005E2C]  1320  ;+
                  [005E2C]  1321  ; Post machine check interrupt. This is the same as mchk.
                  [005E2C]  1322  ;-
         C3E000D7 [005E2C]  1323  	br	r31, sys__mchk_post
                  [005E30]  1324  
                  [005E30]  1325  ;+
                  [005E30]  1326  ; Second error occured.
                  [005E30]  1327  ;
                  [005E30]  1328  ; Current state:
                  [005E30]  1329  ;	p5		base of mchk_crd area
                  [005E30]  1330  ;	p7		raw c_addr
                  [005E30]  1331  ;	p20		raw c_stat
                  [005E30]  1332  ;	PT__FAULT_PC	exc_addr
                  [005E30]  1333  ;-
                  [005E30]  1334  sys__crd_second:
         20DF0003 [005E30]  1335  	lda	p6, 3(r31)			; set retry and 2nd error flags
         48C3D726 [005E34]  1336  	sll	p6, #30, p6			; move to <31:30> of flag long
         7CC50004 [005E38]  1337  	hw_stl/p p6, MCHK_CRD__FLAG_FRAME+4(p5)	; store flag longword
                  [005E3C]  1338  
                  [005E3C]  1339  ;+
                  [005E3C]  1340  ; PCE or DPC set.
                  [005E3C]  1341  ; Check to see if we need to scrub.
                  [005E3C]  1342  ; Then clear errors and dismiss.
                  [005E3C]  1343  ;
                  [005E3C]  1344  ; Current state:
                  [005E3C]  1345  ;	p7		raw c_addr
                  [005E3C]  1346  ;	p20		raw c_stat
                  [005E3C]  1347  ;	PT__STACK_PC	exc_addr
                  [005E3C]  1348  ;-
                  [005E3C]  1349  sys__crd_skip_frame:
                  [005E3C]  1350  
         64DF2A40 [005E3C]  1351  	hw_mfpr	p6, EV6__DC_STAT			; (6,0L) get dc_stat
                  [005E40]  1352  
                  [005E40]  1353  	GET_32CONS 	p4, EV6__I_STAT__W1C, r31
File: ev6_pal_macros.mar
                  [005E40]   239i  ASSUME <ev6__i_stat__w1c> le  <^x7FFFFFFF>
         249F6000 [005E40]   240M 	ldah	p4,<<ev6__i_stat__w1c>+32768>@-16(r31); + xxx<31:16>
         20840000 [005E44]   241M 	lda	p4,<<ev6__i_stat__w1c> & ^XFFFF>(p4) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E41610 [005E48]  1354  	hw_mtpr	p4, EV6__I_STAT				; (4,0L)
                  [005E4C]  1355  
                  [005E4C]  1356  	GET_16CONS	p4, EV6__DC_STAT__W1C_CRD, r31
File: ev6_pal_macros.mar
                  [005E4C]   249M 	ASSUME <<ev6__dc_stat__w1c_crd>> le  <^x7FFF>
         209F000C [005E4C]   250M 	lda	p4,<ev6__dc_stat__w1c_crd>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E42A40 [005E50]  1357  	hw_mtpr p4, EV6__DC_STAT			; (6,0L)
                  [005E54]  1358  	
         4A829734 [005E54]  1359  	sll	p20, #<64-<CHAIN__STAT__S+CHAIN__STAT__V>>, p20
         4A877694 [005E58]  1360  	srl	p20, #<64-CHAIN__STAT__V>, p20		; get c_stat
                  [005E5C]  1361  
         E6800029 [005E5C]  1362  	beq	p20, sys__crd_skip_frame_merge		; if zero, can't scrub
                  [005E60]  1363  
         46811004 [005E60]  1364  	and	p20, #<1@EV6__C_STAT__ISTREAM__S>, p4	; check for istream
         F4800005 [005E64]  1365  	bne	p4, sys__crd_skip_frame_do_scrub	; scrub if so
                  [005E68]  1366  
         4280B5A4 [005E68]  1367  	cmpeq	p20, #DSTREAM_DC_ERR, p4		; check for dcache
         F4800025 [005E6C]  1368  	bne	p4, sys__crd_skip_frame_merge		; don't scrub if so
                  [005E70]  1369  
         44C11004 [005E70]  1370  	and	p6, #<1@EV6__DC_STAT__ECC_ERR_LD__S>, p4; check for ld
         F4800001 [005E74]  1371  	bne	p4, sys__crd_skip_frame_do_scrub	; scrub if so
         C3E00022 [005E78]  1372  	br	r31, sys__crd_skip_frame_merge		; don't scrub if not
                  [005E7C]  1373  
                  [005E7C]  1374  sys__crd_skip_frame_do_scrub:
                  [005E7C]  1375  
         43E53406 [005E7C]  1376  	addq	r31, #C_ADDR_SHIFT, p6		; initialize shift count
         43FF0404 [005E80]  1377  	addq	r31, r31, p4			; initialize output shift data
                  [005E84]  1378  
                  [005E84]  1379  sys__crd_skip_frame_addr:
         44E03014 [005E84]  1380  	and	p7, #1, p20			; clear all but bit 0
         42840404 [005E88]  1381  	addq	p20, p4, p4			; accumulate output shift data
         40C03526 [005E8C]  1382  	subq	p6, #1, p6			; decrement shift count
         E4C00003 [005E90]  1383  	beq	p6, sys__crd_skip_frame_addr_done
                  [005E94]  1384  
         48803724 [005E94]  1385  	sll 	p4, #1, p4			; shift output data 1 bit left
         48E03687 [005E98]  1386  	srl 	p7, #1, p7			; shift input data 1 bit right
         C3FFFFF9 [005E9C]  1387  	br	r31, sys__crd_skip_frame_addr	; do next shift
                  [005EA0]  1388  
                  [005EA0]  1389  sys__crd_skip_frame_addr_done:
         4880D724 [005EA0]  1390  	sll 	p4, #6, p4			; shift error address 6 bits left
                  [005EA4]  1391  
         77FFA380 [005EA4]  1392  	hw_mtpr	r31, EV6__DTB_IA		; (7,1L) flush dtb
         229F3301 [005EA8]  1393  	lda	p20, ^x3301(r31)		; set WE, RE
         47FF041F [005EAC]  1394  	bis	r31, r31, r31
         47FF041F [005EB0]  1395  	bis	r31, r31, r31
                  [005EB4]  1396  
         77FF2780 [005EB4]  1397  	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; wait for retire
         4881B686 [005EB8]  1398  	srl	p4, #13, p6			; shift byte offset
         48C41726 [005EBC]  1399  	sll	p6, #EV6__DTB_PTE0__PFN__S, p6	; shift into position
         44D40406 [005EC0]  1400  	bis	p6, p20, p6			; produce pte
                  [005EC4]  1401  
                  [005EC4]  1402  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
47FF041F 47FF041F [005EC4]   265i 	.align 4, <^x47FF041F>
         47FF041F [005ECC]
File: ev6_osf_system_pal.mar
                  [005ED0]  1403  
                  [005ED0]  1404  	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [005ED0]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E42044 [005ED0]  1405  	hw_mtpr	p4, EV6__DTB_TAG0		; (2&6,0L) write tag0
         77E4A022 [005ED4]  1406  	hw_mtpr p4, EV6__DTB_TAG1		; (1&5,1L) write tag1
         77E62155 [005ED8]  1407  	hw_mtpr	p6, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
         77E6A1AA [005EDC]  1408  	hw_mtpr	p6, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [005EE0]  1409  
         77FF2780 [005EE0]  1410  	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; 1.41 wait for retire
                  [005EE4]  1411  
         63FF4000 [005EE4]  1412  	mb					; quiet before we start
                  [005EE8]  1413      .if eq force_path				; 1.41
                  [005EE8]  1414  	PVC_JSR scrub, bsr=1
                  [005EE8]  1415  	bsr	p7, sys__crd_scrub
                  [005EE8]  1416      .iff
                  [005EE8]  1417  	PVC_VIOLATE <1008>			; 1.42 tell pvc to skip routine
                  [005EE8]  1418  	br	p7, sys__crd_scrub
                  [005EE8]  1419  	ALIGN_FETCH_BLOCK <^x47FF041F>		; 1.43 separate fetch blocks
                  [005EE8]  1420      .endc					; 1.41
                  [005EE8]  1414I 	PVC_JSR scrub, bsr=1
File: ev6_pal_macros.mar
                  [005EE8]   531i  pvc_lbl \pcv_index, \pcv_jsr_scrub0, osf
File: ev6_osf_system_pal.mar
         D0FFFFA5 [005EE8]  1415I 	bsr	p7, sys__crd_scrub
                  [005EEC]  1421      
         77FFA380 [005EEC]  1422  	hw_mtpr	r31, EV6__DTB_IA		; (7,1L) flush dtb
         47FF041F [005EF0]  1423  	bis	r31, r31, r31
         47FF041F [005EF4]  1424  	bis	r31, r31, r31
         47FF041F [005EF8]  1425  	bis	r31, r31, r31
                  [005EFC]  1426  
         77FF2780 [005EFC]  1427  	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; wait for retire
         C3E00000 [005F00]  1428  	br	r31, sys__crd_skip_frame_merge
                  [005F04]  1429  ;
                  [005F04]  1430  ; Now clear the crd.
                  [005F04]  1431  ;
                  [005F04]  1432  sys__crd_skip_frame_merge:
         47E03407 [005F04]  1433  	bis	r31, #1, p7				; get a 1
         48E3F727 [005F08]  1434  	sll	p7, #EV6__HW_INT_CLR__CR__S, p7		; shift into position
                  [005F0C]  1435  
         77E70E10 [005F0C]  1436  	hw_mtpr	p7, EV6__HW_INT_CLR			; (4,0L)
         6EF51060 [005F10]  1437  	hw_ldq/p p23, PT__STACK_PC(p_temp)		; get exc_addr back
                  [005F14]  1438  
                  [005F14]  1439  	GET_16CONS	p7, EV6__DC_STAT__W1C_CRD, r31
File: ev6_pal_macros.mar
                  [005F14]   249M 	ASSUME <<ev6__dc_stat__w1c_crd>> le  <^x7FFF>
         20FF000C [005F14]   250M 	lda	p7,<ev6__dc_stat__w1c_crd>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E72A40 [005F18]  1440  	hw_mtpr p7, EV6__DC_STAT			; (6,0L) clear dc_stat
         47FF041F [005F1C]  1441  	bis	r31, r31, r31
         47FF041F [005F20]  1442  	bis	r31, r31, r31
         47FF041F [005F24]  1443  	bis	r31, r31, r31
                  [005F28]  1444  
         77E70E50 [005F28]  1445  	hw_mtpr	p7, <EV6__HW_INT_CLR ! ^x40>		; (4,0L) force retire
                  [005F2C]  1446  
                  [005F2C]  1447      .if eq force_path				; 1.41
                  [005F2C]  1448  	hw_ret_stall (p23)			; dismiss
                  [005F2C]  1449      .iff
                  [005F2C]  1450  	ALIGN_FETCH_BLOCK <^x47FF041F>
                  [005F2C]  1451  	PVC_VIOLATE <1007>
                  [005F2C]  1452  	PVC_VIOLATE <1020>			; stop permutation
                  [005F2C]  1453  	hw_jmp_stall (p23)			; dismiss with jmp
                  [005F2C]  1454  	br	r31, .-4			; stop predictor
                  [005F2C]  1455      .endc					; 1.41
         7BF7A000 [005F2C]  1448I 	hw_ret_stall (p23)			; dismiss
                  [005F30]  1456      
                  [005F30]  1457  ;+
                  [005F30]  1458  ; sys__mchk_dc_tag_perr
                  [005F30]  1459  ;
                  [005F30]  1460  ; Dcache tag parity error occured during the initial tag probe of a load
                  [005F30]  1461  ; or store instruction. This error created a synchronous fault to the dfault
                  [005F30]  1462  ; PALcode entry point, and was corrected. We start off treating the fault
                  [005F30]  1463  ; as a mchk. If we are in palmode, we halt. If no machine checks are in
                  [005F30]  1464  ; progress, we turn the fault into a crd. If a mchk is in progress, we
                  [005F30]  1465  ; dismiss.
                  [005F30]  1466  ;
                  [005F30]  1467  ; Current state:
                  [005F30]  1468  ;	p5		mm_stat
                  [005F30]  1469  ;	p23		exc_addr
                  [005F30]  1470  ;-
                  [005F30]  1471  
                  [005F30]  1472  ASSUME OSF_P_MISC__MCES__MCHK__S eq 16
                  [005F30]  1473  ASSUME OSF_P_MISC__SCBV__S eq 24
                  [005F30]  1474  ASSUME OSF_P_MISC__MCHK_CODE__S eq 40
                  [005F30]  1475  
                  [005F30]  1476  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [005F30]   275i 	.align 6
00000000 00000000 [005F38]
File: ev6_osf_system_pal.mar
                  [005F40]  1477  
                  [005F40]  1478  sys__mchk_dc_tag_perr:
         F2E00126 [005F40]  1479  	blbs	p23, sys__dc_tag_perr_while_in_pal	; halt on in pal mode
                  [005F44]  1480  
         44BF0414 [005F44]  1481  	bis	p5, r31, p20			; save off mm_stat
         4AC050C5 [005F48]  1482  	extbl	p_misc, #2, p5			; get mces
         F0A00026 [005F4C]  1483  	blbs	p5, sys__perr_dis		; dimiss if MCES<MCHK>
                  [005F50]  1484  
         7EF51060 [005F50]  1485  	hw_stq/p p23, PT__STACK_PC(p_temp)	; save for post, free up register
         4AC050D7 [005F54]  1486  	extbl	p_misc, #2, p23			; get mces
         4ACF1616 [005F58]  1487  	zap	p_misc, #^x78, p_misc		; clean mchk_code and SCBv
                  [005F5C]  1488  
         4AE07686 [005F5C]  1489  	srl	p23, #MCES__DPC__S, p6		; get dpc
         F0C00020 [005F60]  1490  	blbs	p6, sys__perr_skip_frame	; dpc => don't build frame
                  [005F64]  1491  
         46E09406 [005F64]  1492  	bis	p23, #<1@MCES__PCE__S>, p6		; set MCES<PCE>
         48C21726 [005F68]  1493  	sll	p6, #OSF_P_MISC__MCES__MCHK__S, p6	; shift into position
         46C60416 [005F6C]  1494  	bis	p_misc, p6, p_misc			; or back mces
                  [005F70]  1495  
         20DF0630 [005F70]  1496  	lda	p6, SCB__PROC_CORR_ERR(r31)		; SCB vector
         48C31726 [005F74]  1497  	sll	p6, #OSF_P_MISC__SCBV__S, p6		; SCBv into position
         46C60416 [005F78]  1498  	bis	p_misc, p6, p_misc			; or back scbv
                  [005F7C]  1499  
         20DF009E [005F7C]  1500  	lda	p6, MCHK__DC_TAG_PERR(r31)		; mchk code
         48C51726 [005F80]  1501  	sll	p6, #OSF_P_MISC__MCHK_CODE__S, p6	; mchk code into position
         46C60416 [005F84]  1502  	bis	p_misc, p6, p_misc			; or back mchk code
                  [005F88]  1503  ;
                  [005F88]  1504  ; Now compute where the frame is.
                  [005F88]  1505  ;
         6C951098 [005F88]  1506  	hw_ldq/p p4, PT__WHAMI(p_temp)			; get whami
                  [005F8C]  1507  
         20BF0400 [005F8C]  1508  	lda	p5, PAL__LOGOUT_SPECIFIC_SIZE(r31)	; short&long size
         4C850405 [005F90]  1509  	mulq	p4, p5, p5				; * whami
                  [005F94]  1510  
                  [005F94]  1511  	GET_32CONS	p6, PAL__LOGOUT_BASE, r31	; logout base
File: ev6_pal_macros.mar
                  [005F94]   239i  ASSUME <pal__logout_base> le  <^x7FFFFFFF>
         24DF0000 [005F94]   240M 	ldah	p6,<<pal__logout_base>+32768>@-16(r31); + xxx<31:16>
         20C66000 [005F98]   241M 	lda	p6,<<pal__logout_base> & ^XFFFF>(p6) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         40A60405 [005F9C]  1512  	addq	p5, p6, p5				; (size*whami) + base
         20A50100 [005FA0]  1513  	lda	p5, MCHK__BASE(p5)			; start of mchk area
                  [005FA4]  1514  
         4AE05686 [005FA4]  1515  	srl	p23, #MCES__PCE__S, p6			; get PCE
         F0C0000B [005FA8]  1516  	blbs	p6, sys__perr_second			; set => second error
                  [005FAC]  1517  ;
                  [005FAC]  1518  ; To be neat, write 0 to the cbox logout quadwords. Log ic_stat and
                  [005FAC]  1519  ; dc_stat but don't clear them.
                  [005FAC]  1520  ;
         7FE51030 [005FAC]  1521  	hw_stq/p r31, MCHK_CRD__DC1_SYNDROME(p5)	; store 0
         7FE51038 [005FB0]  1522  	hw_stq/p r31, MCHK_CRD__DC0_SYNDROME(p5)	; store 0
         7FE51040 [005FB4]  1523  	hw_stq/p r31, MCHK_CRD__C_STAT(p5)		; store 0
         7FE51048 [005FB8]  1524  	hw_stq/p r31, MCHK_CRD__C_STS(p5)		; store 0
         7FE51028 [005FBC]  1525  	hw_stq/p r31, MCHK_CRD__C_ADDR(p5)		; store 0
                  [005FC0]  1526  
         7E851050 [005FC0]  1527  	hw_stq/p p20, MCHK_CRD__MM_STAT(p5)		; store mm_stat
                  [005FC4]  1528  
         649F1610 [005FC4]  1529  	hw_mfpr p4, EV6__I_STAT				; (4,0L) get i_stat
         64DF2A40 [005FC8]  1530  	hw_mfpr	p6, EV6__DC_STAT			; (6,0L) get dc_stat
         7C851018 [005FCC]  1531  	hw_stq/p p4, MCHK_CRD__I_STAT(p5)		; store i_stat
         7CC51020 [005FD0]  1532  	hw_stq/p p6, MCHK_CRD__DC_STAT(p5)		; store dc_stat
                  [005FD4]  1533  
         C3FFFF88 [005FD4]  1534  	br	r31, sys__crd_header			; merge to finish
                  [005FD8]  1535  
                  [005FD8]  1536  ;+
                  [005FD8]  1537  ; PCE set on dc_tag_perr.
                  [005FD8]  1538  ;
                  [005FD8]  1539  ; sys__perr_second
                  [005FD8]  1540  ;
                  [005FD8]  1541  ; Current state:
                  [005FD8]  1542  ;	p5		base of mchk_crd area
                  [005FD8]  1543  ;	PT__STACK_PC	exc_addr
                  [005FD8]  1544  ;-
                  [005FD8]  1545  sys__perr_second:
         20DF0003 [005FD8]  1546  	lda	p6, 3(r31)			; set retry and 2nd error flags
         48C3D726 [005FDC]  1547  	sll	p6, #30, p6			; move to <31:30> of flag long
         7CC50004 [005FE0]  1548  	hw_stl/p p6, MCHK_CRD__FLAG_FRAME+4(p5)	; store flag longword
                  [005FE4]  1549  ;+
                  [005FE4]  1550  ; PCE or DPC set on dc_tag_perr. Dismiss.
                  [005FE4]  1551  ;-
                  [005FE4]  1552  sys__perr_skip_frame:
         6EF51060 [005FE4]  1553  	hw_ldq/p p23, PT__STACK_PC(p_temp)		; get exc_addr back
                  [005FE8]  1554  
                  [005FE8]  1555  sys__perr_dis:
                  [005FE8]  1556  
                  [005FE8]  1557      .if eq force_path				; 1.41
                  [005FE8]  1558  	hw_ret_stall (p23)			; dismiss
                  [005FE8]  1559      .iff
                  [005FE8]  1560  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align
                  [005FE8]  1561  	PVC_VIOLATE <1007>
                  [005FE8]  1562  	PVC_VIOLATE <1020>			; stop permutation
                  [005FE8]  1563  	hw_jmp_stall (p23)			; dismiss with jmp
                  [005FE8]  1564  	br	r31, .-4			; stop predictor
                  [005FE8]  1565      .endc					; 1.41
         7BF7A000 [005FE8]  1558I 	hw_ret_stall (p23)			; dismiss
                  [005FEC]  1566      
                  [005FEC]  1567  ;+
                  [005FEC]  1568  ; sys__mchk
                  [005FEC]  1569  ;
                  [005FEC]  1570  ; Current state:
                  [005FEC]  1571  ;	p23		exc_addr
                  [005FEC]  1572  ; 
                  [005FEC]  1573  ; Should we fetch any vulnerable registers earlier?
                  [005FEC]  1574  ;-
                  [005FEC]  1575  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [005FEC]   275i 	.align 6
00000000 00000000 [005FF4]
         00000000 [005FFC]
File: ev6_osf_system_pal.mar
                  [006000]  1576  
                  [006000]  1577  sys__mchk:
                  [006000]  1578  ;
                  [006000]  1579  ; First, fetch the cbox error chain, unlocking the error in the process.
                  [006000]  1580  ;
                  [006000]  1581      .if eq force_path				; 1.41
                  [006000]  1582  	PVC_JSR	cbox, bsr=1
                  [006000]  1583  	bsr	p5, sys__cbox			; get the cbox error chain
                  [006000]  1584      .iff
                  [006000]  1585  	PVC_VIOLATE <1008>			; 1.42 tell pvc to skip routine
                  [006000]  1586  	br	p5, sys__cbox
                  [006000]  1587      .endc					; 1.41
                  [006000]  1582I 	PVC_JSR	cbox, bsr=1
File: ev6_pal_macros.mar
                  [006000]   531i  pvc_lbl \pcv_index, \pcv_jsr_cbox0, osf
File: ev6_osf_system_pal.mar
         D0A000FB [006000]  1583I 	bsr	p5, sys__cbox			; get the cbox error chain
                  [006004]  1588      ;
                  [006004]  1589  ; May enter here for double bit error just after single bit error.
                  [006004]  1590  ;
                  [006004]  1591  
                  [006004]  1592  sys__mchk__double_bit:
                  [006004]  1593  
                  [006004]  1594  ;
                  [006004]  1595  ; Now continue with logout.
                  [006004]  1596  ;
                  [006004]  1597  ; Current state:
                  [006004]  1598  ;	p4		scratched
                  [006004]  1599  ;	p6		scratched
                  [006004]  1600  ;	p20<59:52>	dc1_syndrome<7:0>
                  [006004]  1601  ;	   <51:44>	dc0_syndrome<7:0>
                  [006004]  1602  ;	   <43:39>	c_stat<4:0>
                  [006004]  1603  ;	   <38:35>	c_sts<3:0>
                  [006004]  1604  ;	p23		exc_addr
                  [006004]  1605  ;
                  [006004]  1606  ;	pass1
                  [006004]  1607  ;	-----
                  [006004]  1608  ;	p7 <44:08>	c_addr<6:42>
                  [006004]  1609  ;	   <07:06>	raz
                  [006004]  1610  ;	   <05:00>	UNDEFINED
                  [006004]  1611  ;	pass2
                  [006004]  1612  ;	-----
                  [006004]  1613  ;	p7 <40:04>	c_addr<6:42>
                  [006004]  1614  ;	   <03:00>	raz
                  [006004]  1615  ;
                  [006004]  1616  
                  [006004]  1617  ASSUME OSF_P_MISC__MCES__MCHK__S eq 16
                  [006004]  1618  ASSUME OSF_P_MISC__SCBV__S eq 24
                  [006004]  1619  ASSUME OSF_P_MISC__MCHK_CODE__S eq 40
                  [006004]  1620  
         7ED51090 [006004]  1621  	hw_stq/p p_misc, PT__P_MISC(p_temp)	; save p_misc for mchk_to_crd
                  [006008]  1622  
         4AC050C5 [006008]  1623  	extbl	p_misc, #2, p5				; get mces
         4ACF1616 [00600C]  1624  	zap	p_misc, #^x78, p_misc			; clear mchk_code & SCBv
                  [006010]  1625  
         44A03406 [006010]  1626  	bis	p5, #<1@MCES__MCHK__S>, p6		; set MCES<MCHK>
         48C21726 [006014]  1627  	sll	p6, #OSF_P_MISC__MCES__MCHK__S, p6	; shift into position
         46C60416 [006018]  1628  	bis	p_misc, p6, p_misc			; or back mces
                  [00601C]  1629  
         20DF0670 [00601C]  1630  	lda	p6, SCB__PROCMCHK(r31)			; SCB vector
         48C31726 [006020]  1631  	sll	p6, #OSF_P_MISC__SCBV__S, p6		; move SCBv into position
         46C60416 [006024]  1632  	bis	p_misc, p6, p_misc			; or back scbv
                  [006028]  1633  
         20DF0098 [006028]  1634  	lda	p6, MCHK__PROC_HRD_ERR(r31)		; mchk code
         48C51726 [00602C]  1635  	sll	p6, #OSF_P_MISC__MCHK_CODE__S, p6	; mchk code into position
         46C60416 [006030]  1636  	bis	p_misc, p6, p_misc			; or back mchk code
                  [006034]  1637  
         F0A000E3 [006034]  1638  	blbs	p5, sys__double_machine_check		; halt on double
         F2E000E5 [006038]  1639  	blbs	p23, sys__machine_check_while_in_pal	; halt on in pal mode
                  [00603C]  1640  ;+
                  [00603C]  1641  ; Compute where the frame is.
                  [00603C]  1642  ;
                  [00603C]  1643  ; Current state:
                  [00603C]  1644  ;	p7	cbox error chain info
                  [00603C]  1645  ;	p20	cbox error chain info
                  [00603C]  1646  ;	p23	exc_addr
                  [00603C]  1647  ;-
         6C951098 [00603C]  1648  	hw_ldq/p p4, PT__WHAMI(p_temp)			; get whami
                  [006040]  1649  
         20BF0400 [006040]  1650  	lda	p5, PAL__LOGOUT_SPECIFIC_SIZE(r31)	; short&long size
         4C850405 [006044]  1651  	mulq	p4, p5, p5				; * whami
                  [006048]  1652  
                  [006048]  1653  	GET_32CONS	p6, PAL__LOGOUT_BASE, r31	; logout base
File: ev6_pal_macros.mar
                  [006048]   239i  ASSUME <pal__logout_base> le  <^x7FFFFFFF>
         24DF0000 [006048]   240M 	ldah	p6,<<pal__logout_base>+32768>@-16(r31); + xxx<31:16>
         20C66000 [00604C]   241M 	lda	p6,<<pal__logout_base> & ^XFFFF>(p6) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         40A60405 [006050]  1654  	addq	p5, p6, p5				; (size*whami) + base
         20A50100 [006054]  1655  	lda	p5, MCHK__BASE(p5)			; start of mchk area
                  [006058]  1656  
         7EE51058 [006058]  1657  	hw_stq/p p23, MCHK__EXC_ADDR(p5)		; store exc_addr
         7EF51060 [00605C]  1658  	hw_stq/p p23, PT__STACK_PC(p_temp)		; save fault pc
                  [006060]  1659  
         649F0D00 [006060]  1660  	hw_mfpr	p4, EV6__ISUM				; get isum here
         7C851068 [006064]  1661  	hw_stq/p p4, MCHK__ISUM(p5)			; save isum
                  [006068]  1662  
                  [006068]  1663  ;+
                  [006068]  1664  ; Now construct the cbox error registers and log them.
                  [006068]  1665  ; Current state:
                  [006068]  1666  ;
                  [006068]  1667  ;	p5		base of mchk logout frame
                  [006068]  1668  ;
                  [006068]  1669  ;	p7		c_addr
                  [006068]  1670  ;
                  [006068]  1671  ;	p20<59:52>	dc1_syndrome<7:0>
                  [006068]  1672  ;	   <51:44>	dc0_syndrome<7:0>
                  [006068]  1673  ;	   <43:39>	c_stat<4:0>
                  [006068]  1674  ;	   <38:35>	c_sts<3:0>
                  [006068]  1675  ;
                  [006068]  1676  ;	p_misc		updated with new mces, SCB, mchk code
                  [006068]  1677  ;-
                  [006068]  1678  sys__mchk_arrange_cbox:
         4A809724 [006068]  1679  	sll	p20, #<64-<CHAIN__DC1__S+CHAIN__DC1__V>>, p4
         48871684 [00606C]  1680  	srl	p4, #<64-CHAIN__DC1__V>, p4
         7C851030 [006070]  1681  	hw_stq/p p4, MCHK__DC1_SYNDROME(p5)		; store syn1
                  [006074]  1682  
         4A819724 [006074]  1683  	sll	p20, #<64-<CHAIN__DC0__S+CHAIN__DC0__V>>, p4
         48871684 [006078]  1684  	srl	p4, #<64-CHAIN__DC0__V>, p4
         7C851038 [00607C]  1685  	hw_stq/p p4, MCHK__DC0_SYNDROME(p5)		; store syn0
                  [006080]  1686  
         4A829724 [006080]  1687  	sll	p20, #<64-<CHAIN__STAT__S+CHAIN__STAT__V>>, p4
         48877684 [006084]  1688  	srl	p4, #<64-CHAIN__STAT__V>, p4
         7C851040 [006088]  1689  	hw_stq/p p4, MCHK__C_STAT(p5)			; store stat
                  [00608C]  1690  
         4A833724 [00608C]  1691  	sll	p20, #<64-<CHAIN__STS__S+CHAIN__STS__V>>, p4
         48879684 [006090]  1692  	srl	p4, #<64-CHAIN__STS__V>, p4
         7C851048 [006094]  1693  	hw_stq/p p4, MCHK__C_STS(p5)			; store sts
                  [006098]  1694  ;
                  [006098]  1695  ; Now get the error address.
                  [006098]  1696  ;
                  [006098]  1697  ; Current state:
                  [006098]  1698  ;
                  [006098]  1699  ;	p5		base of mchk logout frame
                  [006098]  1700  ;
                  [006098]  1701  ;	pass1
                  [006098]  1702  ;	-----
                  [006098]  1703  ;	p7 <44:08>	c_addr<6:42>
                  [006098]  1704  ;	   <07:06>	raz
                  [006098]  1705  ;	   <05:00>	UNDEFINED
                  [006098]  1706  ;	pass2
                  [006098]  1707  ;	-----
                  [006098]  1708  ;	p7 <40:04>	c_addr<6:42>
                  [006098]  1709  ;	   <03:00>	raz
                  [006098]  1710  ;
                  [006098]  1711  
                  [006098]  1712  .if ne ev6_p1
                  [006098]  1713  	C_ADDR_SHIFT = 45
                  [006098]  1714  	and	p7, #^x3F, p7			; zap UNDEFINED bits
                  [006098]  1715  .iff
                  [006098]  1716  	C_ADDR_SHIFT = 41
                  [006098]  1717  .endc
                  [006098]  1716I 	C_ADDR_SHIFT = 41
                  [006098]  1718  
         43E53406 [006098]  1719  	addq	r31, #C_ADDR_SHIFT, p6		; initialize shift count
         43FF0404 [00609C]  1720  	addq	r31, r31, p4			; initialize output shift data
                  [0060A0]  1721  
                  [0060A0]  1722  sys__mchk_addr:
         44E03014 [0060A0]  1723  	and	p7, #1, p20			; clear all but bit 0
         42840404 [0060A4]  1724  	addq	p20, p4, p4			; accumulate output shift data
         40C03526 [0060A8]  1725  	subq	p6, #1, p6			; decrement shift count
         E4C00003 [0060AC]  1726  	beq	p6, sys__mchk_addr_done		; all done
                  [0060B0]  1727  
         48803724 [0060B0]  1728  	sll 	p4, #1, p4			; shift output data 1 bit left
         48E03687 [0060B4]  1729  	srl 	p7, #1, p7			; shift input data 1 bit right
         C3FFFFF9 [0060B8]  1730  	br	r31, sys__mchk_addr		; do next shift
                  [0060BC]  1731  
                  [0060BC]  1732  sys__mchk_addr_done:
         4880D724 [0060BC]  1733  	sll 	p4, #6, p4			; shift error address 6 bits left
         7C851028 [0060C0]  1734  	hw_stq/p p4, MCHK__C_ADDR(p5)		; store addr
                  [0060C4]  1735  
                  [0060C4]  1736  ;+
                  [0060C4]  1737  ; Fetch rest of short frame registers
                  [0060C4]  1738  ;-
                  [0060C4]  1739  	EV6__DC_STAT__W1C = -
                  [0060C4]  1740  		<<1@EV6__DC_STAT__TPERR_P0__S> ! -
                  [0060C4]  1741  		<1@EV6__DC_STAT__TPERR_P1__S> ! -
                  [0060C4]  1742  		<1@EV6__DC_STAT__ECC_ERR_ST__S> ! -
                  [0060C4]  1743  		<1@EV6__DC_STAT__ECC_ERR_LD__S> ! -
                  [0060C4]  1744  		<1@EV6__DC_STAT__SEO__S>>
                  [0060C4]  1745  
         649F2700 [0060C4]  1746  	hw_mfpr p4, EV6__MM_STAT		; (0L) get mm_stat
         7C851050 [0060C8]  1747  	hw_stq/p p4, MCHK__MM_STAT(p5)		; store mm_stat
                  [0060CC]  1748  
         649F1610 [0060CC]  1749  	hw_mfpr p4, EV6__I_STAT			; (4,0L) get i_stat
         64DF2A40 [0060D0]  1750  	hw_mfpr	p6, EV6__DC_STAT		; (6,0L) get dc_stat
         7C851018 [0060D4]  1751  	hw_stq/p p4, MCHK__I_STAT(p5)		; store i_stat
         7CC51020 [0060D8]  1752  	hw_stq/p p6, MCHK__DC_STAT(p5)		; store dc_stat
                  [0060DC]  1753  
                  [0060DC]  1754  	GET_32CONS 	p4, EV6__I_STAT__W1C, r31
File: ev6_pal_macros.mar
                  [0060DC]   239i  ASSUME <ev6__i_stat__w1c> le  <^x7FFFFFFF>
         249F6000 [0060DC]   240M 	ldah	p4,<<ev6__i_stat__w1c>+32768>@-16(r31); + xxx<31:16>
         20840000 [0060E0]   241M 	lda	p4,<<ev6__i_stat__w1c> & ^XFFFF>(p4) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E41610 [0060E4]  1755  	hw_mtpr	p4, EV6__I_STAT			; (4,0L) clear i_stat
                  [0060E8]  1756  	GET_16CONS	p6, EV6__DC_STAT__W1C, r31
File: ev6_pal_macros.mar
                  [0060E8]   249M 	ASSUME <<ev6__dc_stat__w1c>> le  <^x7FFF>
         20DF001F [0060E8]   250M 	lda	p6,<ev6__dc_stat__w1c>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E62A40 [0060EC]  1757  	hw_mtpr p6, EV6__DC_STAT		; (6,0L) clear dc_stat
                  [0060F0]  1758  
         63FF4000 [0060F0]  1759  	mb					; protect mm_stat ??
                  [0060F4]  1760  
                  [0060F4]  1761  ;
                  [0060F4]  1762  ; Current state:
                  [0060F4]  1763  ;	p5		base of machine logout frame
                  [0060F4]  1764  ;
                  [0060F4]  1765  ; Check for re-tryable:
                  [0060F4]  1766  ;	(1) icache fill error. Hardware has flushed the icache, but the
                  [0060F4]  1767  ;		PALcode must scrub the block in the bcache.
                  [0060F4]  1768  ;
                  [0060F4]  1769  ; Decode of c_stat:
                  [0060F4]  1770  ;	0.0000		no error
                  [0060F4]  1771  ;	0.0001		BC_PERR (bcache parity error)
                  [0060F4]  1772  ;	0.0010		DC_PERR (ttag parity error)
                  [0060F4]  1773  ;	0.0011		DSTREAM_MEM_ERR
                  [0060F4]  1774  ;	0.0100		DSTREAM_BC_ERR
                  [0060F4]  1775  ;	0.0101		DSTREAM_DC_ERR
                  [0060F4]  1776  ;	0.011x		PROBE_BC_ERR (?)
                  [0060F4]  1777  ;
                  [0060F4]  1778  ;	0.1000		reserved
                  [0060F4]  1779  ;	0.1001		reserved
                  [0060F4]  1780  ;	0.1010		reserved
                  [0060F4]  1781  ;	0.1011		ISTREAM_MEM_ERR
                  [0060F4]  1782  ;	0.1100		ISTREAM_BC_ERR
                  [0060F4]  1783  ;	0.1101		reserved
                  [0060F4]  1784  ;	0.111x		reserved
                  [0060F4]  1785  ;
                  [0060F4]  1786  ;	1.xxxx		double bit error
                  [0060F4]  1787  ;	1.0011		mem double on dstream (p3)
                  [0060F4]  1788  ;	1.0100		bcache double on dstream (p3)
                  [0060F4]  1789  ;	1.1011		mem double on istream (p3)
                  [0060F4]  1790  ;	1.1100		bcache double on istream (p3)
                  [0060F4]  1791  ;
                  [0060F4]  1792  ASSUME EV6__C_STAT__ISTREAM__S eq 3
                  [0060F4]  1793  ASSUME EV6__C_STAT__DOUBLE__S eq 4
                  [0060F4]  1794  ASSUME OSF_P_MISC__MCHK_CODE__S eq 40
                  [0060F4]  1795  
         6EE51040 [0060F4]  1796  	hw_ldq/p p23, MCHK__C_STAT(p5)			; get error code back
         46E21007 [0060F8]  1797  	and	p23, #<1@EV6__C_STAT__DOUBLE__S>, p7	; check for double
         F4E00002 [0060FC]  1798  	bne	p7, sys__mchk_double			; branch if so
         46E11007 [006100]  1799  	and	p23, #<1@EV6__C_STAT__ISTREAM__S>, p7	; check for istream
         F4E00030 [006104]  1800  	bne	p7, sys__mchk_istream			; branch if so
                  [006108]  1801  sys__mchk_double:
         47FF0414 [006108]  1802  	bis	r31, r31, p20				; no retry
         47E03407 [00610C]  1803  	bis	r31, #1, p7				; get a 1
         48E39727 [006110]  1804  	sll	p7, #EV6__HW_INT_CLR__MCHK_D__S, p7	; shift into position
                  [006114]  1805  	PVC_VIOLATE <35>
File: ev6_pal_macros.mar
                  [006114]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E70E10 [006114]  1806  	hw_mtpr	p7, EV6__HW_INT_CLR			; (4,0L) clear dstream
                  [006118]  1807  ;
                  [006118]  1808  ; Write the first 2 quadwords of the logout area
                  [006118]  1809  ;
                  [006118]  1810  ; Current state:
                  [006118]  1811  ;	p5	base of mchk area
                  [006118]  1812  ;	p20	retry flag
                  [006118]  1813  ;
                  [006118]  1814  sys__mchk_header:
         4A87F734 [006118]  1815  	sll	p20, #63, p20			; shift retry into position
         229400A0 [00611C]  1816  	lda	p20, MCHK__SIZE(p20)		; flag ! frame size
         7E851000 [006120]  1817  	hw_stq/p p20, MCHK__FLAG_FRAME(p5)	; store flag ! frame size
         229F00A0 [006124]  1818  	lda	p20, MCHK__SYSTEM_BASE(r31)	; system offset ???
         4A841734 [006128]  1819  	sll	p20, #32, p20			; shift into position
         22940018 [00612C]  1820  	lda	p20, MCHK__CPU_BASE(p20)	; sys offset ! cpu offset
         7E851008 [006130]  1821  	hw_stq/p p20, MCHK__OFFSETS(p5)		; store offsets
                  [006134]  1822  
                  [006134]  1823  ;+
                  [006134]  1824  ; Fetch long frame cpu registers.
                  [006134]  1825  ;
                  [006134]  1826  ; Current state:
                  [006134]  1827  ;	p5	base of machine check logout frame
                  [006134]  1828  ;-
                  [006134]  1829  	ALIGN_FETCH_BLOCK <^x47FF041F>
File: ev6_pal_macros.mar
47FF041F 47FF041F [006134]   265i 	.align 4, <^x47FF041F>
         47FF041F [00613C]
File: ev6_osf_system_pal.mar
                  [006140]  1830  
                  [006140]  1831  sys__mchk_registers:
         64DF5F10 [006140]  1832  	hw_mfpr	p6, EV6__PROCESS_CONTEXT	; (4,0L) get process context
         47FF041F [006144]  1833  	bis	r31, r31, r31			; don't write isum here
         47FF041F [006148]  1834  	bis	r31, r31, r31			; don't write isum here
         7CC51088 [00614C]  1835  	hw_stq/p p6, MCHK__PROCESS_CONTEXT(p5)	; store process context
                  [006150]  1836  
         649F0B10 [006150]  1837  	hw_mfpr	p4, EV6__IER_CM			; (4,0L) get ier_cm
         47FF041F [006154]  1838  	bis	r31, r31, r31			; don't get isum here
         47FF041F [006158]  1839  	bis	r31, r31, r31			; don't write isum here
         7C851060 [00615C]  1840  	hw_stq/p p4, MCHK__IER_CM(p5)		; store ier_cm
                  [006160]  1841  
         649F1010 [006160]  1842  	hw_mfpr	p4, EV6__PAL_BASE		; (4,0L) get pal_base
         47FF041F [006164]  1843  	bis	r31, r31, r31			; don't get isum here
         47FF041F [006168]  1844  	bis	r31, r31, r31			; don't write isum here
         7C851078 [00616C]  1845  	hw_stq/p p4, MCHK__PAL_BASE(p5)		; store pal_base
                  [006170]  1846  
         649F1110 [006170]  1847  	hw_mfpr	p4, EV6__I_CTL			; (4,0L) get i_ctl
         7C851080 [006174]  1848  	hw_stq/p p4, MCHK__I_CTL(p5)		; store i_ctl
                  [006178]  1849  ;+
                  [006178]  1850  ; Store the pal specific information. Also add revision number.
                  [006178]  1851  ;-
                  [006178]  1852  ASSUME OSF_P_MISC__MCHK_CODE__S eq 40
                  [006178]  1853  
                  [006178]  1854  	GET_16CONS	p6, MCHK__REV, r31	; get revision
File: ev6_pal_macros.mar
                  [006178]   249M 	ASSUME <<mchk__rev>> le  <^x7FFF>
         20DF0001 [006178]   250M 	lda	p6,<mchk__rev>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         48C41726 [00617C]  1855  	sll	p6, #32, p6			; shift into position
         4AC0B2D4 [006180]  1856  	extwl	p_misc, #5, p20			; get mchk_code field
         46860414 [006184]  1857  	bis	p20, p6, p20			; combine the two
         7E851010 [006188]  1858  	hw_stq/p p20, MCHK__MCHK_CODE(p5)	; store mchk code and rev
                  [00618C]  1859  ;+
                  [00618C]  1860  ; Store the system-specific part of the logout frame
                  [00618C]  1861  ;-
                  [00618C]  1862  
                  [00618C]  1863  ;+
                  [00618C]  1864  ; Post machine check interrupt.
                  [00618C]  1865  ;
                  [00618C]  1866  ; Current state:
                  [00618C]  1867  ;	p5		logout frame address
                  [00618C]  1868  ;
                  [00618C]  1869  ;	PT__STACK_PC	current pc
                  [00618C]  1870  ;-
                  [00618C]  1871  EV6__M_CTL__SPE2__S = 3
                  [00618C]  1872  
                  [00618C]  1873  sys__mchk_post:
         20FF0002 [00618C]  1874  	lda	p7, OSF_A0_INT__MCHK(r31)	; mark machine check
         7CF51068 [006190]  1875  	hw_stq/p p7, PT__NEW_A0(p_temp)		; save new a0 away
                  [006194]  1876  
         4AC072C4 [006194]  1877  	extwl	p_misc, #3, p4			; SCBV
         7C951070 [006198]  1878  	hw_stq/p p4, PT__NEW_A1(p_temp)		; save new a1 away
                  [00619C]  1879  
         6CD510C0 [00619C]  1880  	hw_ldq/p p6, PT__M_CTL(p_temp)		; get M_CTL
         47E55404 [0061A0]  1881  	bis	r31, #42, p4			; assume 43-bit spe
         48C07686 [0061A4]  1882  	srl	p6, #EV6__M_CTL__SPE2__S, p6	; check out 48-bit spe
         44C5F284 [0061A8]  1883  	cmovlbs	p6, #47, p4			; change shift count if so
                  [0061AC]  1884  
         43E03527 [0061AC]  1885  	subq	r31, #1, p7			; get a -1
         48E40687 [0061B0]  1886  	srl	p7, p4, p7			; shift off low bits of kseg addr
         48E40727 [0061B4]  1887  	sll	p7, p4, p7			; shift back into position
         44E50407 [0061B8]  1888  	bis	p7, p5, p7			; kseg pointer to logout area
         7CF51078 [0061BC]  1889  	hw_stq/p p7, PT__NEW_A2(p_temp)		; save new a2 away
                  [0061C0]  1890  
         47E0F406 [0061C0]  1891  	bis	r31, #OSF_IPL__MCHK, p6		; new ipl
         C3FFFE6B [0061C4]  1892  	br	r31, sys__int_post		; post interrupt
                  [0061C8]  1893  
                  [0061C8]  1894  ;+
                  [0061C8]  1895  ; Istream => recoverable. The hardware has scrubbed the icache, but the
                  [0061C8]  1896  ; PALcode needs to scrub the bcache and memory.
                  [0061C8]  1897  ;
                  [0061C8]  1898  ; We do this we quadword loads to the block. The hardware will do the
                  [0061C8]  1899  ; scrub. However, a good scrubbing causes a crd. Check for a crd
                  [0061C8]  1900  ; interrupt, read the cbox chain again, and do a write to hw_int_clr.
                  [0061C8]  1901  ;
                  [0061C8]  1902  ; Question: Do I need to be aligned and do I have to be careful with
                  [0061C8]  1903  ; the istream pre-fetching? For now, use Quinn's code as is. I have added
                  [0061C8]  1904  ; an mb on the front to isolate this scrub, but it is also probably not
                  [0061C8]  1905  ; necessary.
                  [0061C8]  1906  ;
                  [0061C8]  1907  ; Also, we have a crd that occurs along with the mchk, which would allow
                  [0061C8]  1908  ; us to detect and correct a mchk down a bad path. The hw_int_clr wirte
                  [0061C8]  1909  ; clears everything up.
                  [0061C8]  1910  ;
                  [0061C8]  1911  ; Current state:
                  [0061C8]  1912  ;	p5		base of mchk logout frame
                  [0061C8]  1913  ;-
                  [0061C8]  1914  
                  [0061C8]  1915  ;+
                  [0061C8]  1916  ; 1.41
                  [0061C8]  1917  ;
                  [0061C8]  1918  ; First check for CMOV -- if exc_addr - 4 was a cmov, we must kill
                  [0061C8]  1919  ; the machine because the cmov may or may not have actually
                  [0061C8]  1920  ; been executed and we really have no way of knowing.
                  [0061C8]  1921  ;
                  [0061C8]  1922  ; Rather than compare the opcode and function of each possible 
                  [0061C8]  1923  ; type of CMOV, we'll compare the bits that are common across 
                  [0061C8]  1924  ; all of them. This may end up matching a few additional 
                  [0061C8]  1925  ; instructions but that's ok. With a quick look through the 
                  [0061C8]  1926  ; current instruction assignments, the only other instructions
                  [0061C8]  1927  ; with the same opcode as either of these are xor and ornot
                  [0061C8]  1928  ; both of which have function codes which will not match the
                  [0061C8]  1929  ; test below.
                  [0061C8]  1930  ;
                  [0061C8]  1931  ; The function encodings for the CMOVs are:
                  [0061C8]  1932  ;
                  [0061C8]  1933  ;  CMOVEQ  010.0100
                  [0061C8]  1934  ;  CMOVGE  100.0110
                  [0061C8]  1935  ;  CMOVGT  110.0110        FCMOVEQ 000.0010.1010
                  [0061C8]  1936  ;  CMOVLBC 001.0110        FCMOVGE 000.0010.1101
                  [0061C8]  1937  ;  CMOVLBS 001.0100        FCMOVGT 000.0010.1111
                  [0061C8]  1938  ;  CMOVLE  110.0100        FCMOVLE 000.0010.1110
                  [0061C8]  1939  ;  CMOVLT  100.0100        FCMOVLT 000.0010.1100
                  [0061C8]  1940  ;  CMOVNE  010.0110        FCMOVNE 000.0010.1011
                  [0061C8]  1941  ;  ----------------        ---------------------
                  [0061C8]  1942  ;          xxx.01x0                000.0010.1xxx
                  [0061C8]  1943  ;
                  [0061C8]  1944  ; All of the integer CMOV instructions are opcode 0x11 and
                  [0061C8]  1945  ; the FP CMOV instructions are opcode 0x17.
                  [0061C8]  1946  ;
                  [0061C8]  1947  ; The function for integer CMOVs (int operate format)
                  [0061C8]  1948  ; is instr<11:5> and for fp CMOVs (FP operate format) is
                  [0061C8]  1949  ; instr<15:5>. In both cases the opcode is instr<31:26>.
                  [0061C8]  1950  ;
                  [0061C8]  1951  ; So what we'll do is mask the instruction down to
                  [0061C8]  1952  ; the opcode and care function bits (2 mask ops -- 
                  [0061C8]  1953  ; int and fp) and then compare against the actual
                  [0061C8]  1954  ; opcode and care bits.
                  [0061C8]  1955  ;
                  [0061C8]  1956  ; Therefore the mask and compare values are:
                  [0061C8]  1957  ;
                  [0061C8]  1958  ;  Integer: Mask: 0xfc0001a0 Compare: 0x44000080
                  [0061C8]  1959  ;  FP:      Mask: 0xfc00ff00 Compare: 0xfc000500
                  [0061C8]  1960  ;
                  [0061C8]  1961  ; Current state:
                  [0061C8]  1962  ;	p5		base of mchk logout frame
                  [0061C8]  1963  ;	PT__STACK_PC	exc_addr
                  [0061C8]  1964  ;-
                  [0061C8]  1965  
                  [0061C8]  1966  INT_CMOV_MASK = ^xfc0001a0
                  [0061C8]  1967  INT_CMOV_CMP = ^x44000080
                  [0061C8]  1968  FP_CMOV_MASK = ^xfc00ff00 
                  [0061C8]  1969  FP_CMOV_CMP = ^x5c000500    
                  [0061C8]  1970  
                  [0061C8]  1971  sys__mchk_istream:				; 1.41
         7CB510F0 [0061C8]  1972  	hw_stq/p p5, PT__R1(p_temp)		; save off frame addr
         6E951060 [0061CC]  1973  	hw_ldq/p p20, PT__STACK_PC(p_temp)	; get back exc_addr
         42809534 [0061D0]  1974  	subq	p20, #4, p20			; subtract 4
                  [0061D4]  1975  ;
                  [0061D4]  1976  ; Get the instruction. A tb miss is okay.
                  [0061D4]  1977  ; A tnv or dfault will be a fatal mchk.
                  [0061D4]  1978  ;
                  [0061D4]  1979  ; Current state:
                  [0061D4]  1980  ;	PT__R1		saved frame addr
                  [0061D4]  1981  ;	PT__STACK_PC	save exc_addr
                  [0061D4]  1982  ;
                  [0061D4]  1983  sys__mchk_istream_check_cmov:		; 1.41
         A2940000 [0061D4]  1984  	ldl	p20, (p20)		; get instruction
         4A9E1614 [0061D8]  1985  	zap     p20, #^xf0, p20		; clean any sign extension
                  [0061DC]  1986  
                  [0061DC]  1987  	GET_32CONS	p4, INT_CMOV_MASK, r31, verify=0; int CMOV mask
File: ev6_pal_macros.mar
         249FFC00 [0061DC]   240M 	ldah	p4,<<int_cmov_mask>+32768>@-16(r31); + xxx<31:16>
         208401A0 [0061E0]   241M 	lda	p4,<<int_cmov_mask> & ^XFFFF>(p4) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         489E1604 [0061E4]  1988  	zap	p4, #^xf0, p4				; clean sign ext
                  [0061E8]  1989  	GET_32CONS	p5, INT_CMOV_CMP, r31		; int CMOV compare
File: ev6_pal_macros.mar
                  [0061E8]   239i  ASSUME <int_cmov_cmp> le  <^x7FFFFFFF>
         24BF4400 [0061E8]   240M 	ldah	p5,<<int_cmov_cmp>+32768>@-16(r31); + xxx<31:16>
         20A50080 [0061EC]   241M 	lda	p5,<<int_cmov_cmp> & ^XFFFF>(p5) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [0061F0]  1990  
         46840004 [0061F0]  1991  	and	p20, p4, p4		; mask it
         408505A6 [0061F4]  1992  	cmpeq	p4, p5, p6		; is it an int CMOV?
                  [0061F8]  1993  
                  [0061F8]  1994  	GET_32CONS	p4, FP_CMOV_MASK, r31, verify=0	; fp CMOV mask
File: ev6_pal_macros.mar
         249FFC01 [0061F8]   240M 	ldah	p4,<<fp_cmov_mask>+32768>@-16(r31); + xxx<31:16>
         2084FF00 [0061FC]   241M 	lda	p4,<<fp_cmov_mask> & ^XFFFF>(p4) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         489E1604 [006200]  1995  	zap	p4, #^xf0, p4				; clean sign ext
                  [006204]  1996  	GET_32CONS	p5, INT_CMOV_CMP, r31		; fp CMOV compare
File: ev6_pal_macros.mar
                  [006204]   239i  ASSUME <int_cmov_cmp> le  <^x7FFFFFFF>
         24BF4400 [006204]   240M 	ldah	p5,<<int_cmov_cmp>+32768>@-16(r31); + xxx<31:16>
         20A50080 [006208]   241M 	lda	p5,<<int_cmov_cmp> & ^XFFFF>(p5) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [00620C]  1997  
         46840004 [00620C]  1998  	and	p20, p4, p4		; mask it
         408505A7 [006210]  1999  	cmpeq	p4, p5, p7		; is it an fp CMOV?
                  [006214]  2000  
         44C70406 [006214]  2001  	bis	p6, p7, p6			; is it a CMOV? (merge results)
         F4C00001 [006218]  2002  	bne	p6, sys__mchk_istream_cmov_err	; branch if so
         C3E0000E [00621C]  2003  	br	r31, sys__mchk_istream_not_cmov	; branch for not
                  [006220]  2004  ;+
                  [006220]  2005  ; PC-4 is a CMOV. Make a fatal mchk.
                  [006220]  2006  ;
                  [006220]  2007  ; Current state:
                  [006220]  2008  ; 	PT__STACK_PC	exc_addr
                  [006220]  2009  ; 	PT__R1		frame addr
                  [006220]  2010  ;-
                  [006220]  2011  sys__mchk_istream_cmov_err:				; 1.41
         6CB510F0 [006220]  2012  	hw_ldq/p p5, PT__R1(p_temp)			; get back frame addr
                  [006224]  2013  
         4ACC1616 [006224]  2014  	zap	p_misc, #^x60, p_misc			; clean old code
         20DF00A0 [006228]  2015  	lda	p6, MCHK__ISTREAM_CMOV(r31)		; mchk code
         48C51726 [00622C]  2016  	sll	p6, #OSF_P_MISC__MCHK_CODE__S, p6	; into position
         46C60416 [006230]  2017  	bis	p_misc, p6, p_misc			; or in new code
                  [006234]  2018  
         47FF0414 [006234]  2019  	bis	r31, r31, p20				; no retry
         C3FFFFB7 [006238]  2020  	br	r31, sys__mchk_header			; take fatal mchk
                  [00623C]  2021  ;+
                  [00623C]  2022  ; Couldn't get the instruction for some reason.
                  [00623C]  2023  ;
                  [00623C]  2024  ; Current state:
                  [00623C]  2025  ; 	PT__STACK_PC	exc_addr
                  [00623C]  2026  ; 	PT__R1		frame addr
                  [00623C]  2027  ;-
                  [00623C]  2028  sys__mchk_istream_cmov_fault:				; 1.41
         6CB510F0 [00623C]  2029  	hw_ldq/p p5, PT__R1(p_temp)			; get back frame addr
                  [006240]  2030  
         4ACC1616 [006240]  2031  	zap	p_misc, #^x60, p_misc			; clean old code
         20DF00A2 [006244]  2032  	lda	p6, MCHK__ISTREAM_CMOV_FAULT(r31)	; mchk code
         48C51726 [006248]  2033  	sll	p6, #OSF_P_MISC__MCHK_CODE__S, p6	; into position
         46C60416 [00624C]  2034  	bis	p_misc, p6, p_misc			; or in new code
                  [006250]  2035  
         47FF0414 [006250]  2036  	bis	r31, r31, p20				; no retry
         C3FFFFB0 [006254]  2037  	br	r31, sys__mchk_header			; take fatal mchk
                  [006258]  2038  
                  [006258]  2039  ;+
                  [006258]  2040  ; PC-4 not a CMOV. Back to business. Scrub the address.
                  [006258]  2041  ;
                  [006258]  2042  ; Current state:
                  [006258]  2043  ;	PT__R1		addr of frame
                  [006258]  2044  ;	PT__STACK_PC	exc_addr
                  [006258]  2045  ;-
                  [006258]  2046  sys__mchk_istream_not_cmov:			; 1.41
         6CB510F0 [006258]  2047  	hw_ldq/p p5, PT__R1(p_temp)		; 1.41 get back frame addr
                  [00625C]  2048  
         6C851028 [00625C]  2049  	hw_ldq/p p4, MCHK__C_ADDR(p5)		; get back address
                  [006260]  2050  
         77FFA380 [006260]  2051  	hw_mtpr	r31, EV6__DTB_IA		; (7,1L) flush dtb
         229F3301 [006264]  2052  	lda	p20, ^x3301(r31)		; set WE, RE
         47FF041F [006268]  2053  	bis	r31, r31, r31
         47FF041F [00626C]  2054  	bis	r31, r31, r31
                  [006270]  2055  
         77FF2780 [006270]  2056  	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; wait for retire
         4881B686 [006274]  2057  	srl	p4, #13, p6			; shift byte offset
         48C41726 [006278]  2058  	sll	p6, #EV6__DTB_PTE0__PFN__S, p6	; shift into position
         44D40406 [00627C]  2059  	bis	p6, p20, p6			; produce pte
                  [006280]  2060  
                  [006280]  2061  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
                  [006280]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_system_pal.mar
                  [006280]  2062  
                  [006280]  2063  	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [006280]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E42044 [006280]  2064  	hw_mtpr	p4, EV6__DTB_TAG0		; (2&6,0L) write tag0
         77E4A022 [006284]  2065  	hw_mtpr p4, EV6__DTB_TAG1		; (1&5,1L) write tag1
         77E62155 [006288]  2066  	hw_mtpr	p6, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
         77E6A1AA [00628C]  2067  	hw_mtpr	p6, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [006290]  2068  
         63FF4000 [006290]  2069  	mb					; quiet before we start
         C3E0000A [006294]  2070  	br	r31, sys__mchk_scrub
                  [006298]  2071  
                  [006298]  2072  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [006298]   275i 	.align 6
00000000 00000000 [0062A0]
00000000 00000000 [0062A8]
00000000 00000000 [0062B0]
00000000 00000000 [0062B8]
File: ev6_osf_system_pal.mar
                  [0062C0]  2073  sys__mchk_scrub:
         A4C40000 [0062C0]  2074  	ldq	p6, ^x00(p4)			; re-read the bad block QW #0
         A4C40008 [0062C4]  2075  	ldq	p6, ^x08(p4)			; re-read the bad block QW #1
         A4C40010 [0062C8]  2076  	ldq	p6, ^x10(p4)			; re-read the bad block QW #2
         A4C40018 [0062CC]  2077  	ldq	p6, ^x18(p4)			; re-read the bad block QW #3
         A4C40020 [0062D0]  2078  	ldq	p6, ^x20(p4)			; re-read the bad block QW #4
         A4C40028 [0062D4]  2079  	ldq	p6, ^x28(p4)			; re-read the bad block QW #5
         A4C40030 [0062D8]  2080  	ldq	p6, ^x30(p4)			; re-read the bad block QW #6
         63FF4000 [0062DC]  2081  	mb					; no other mem-ops till done
         ACC40038 [0062E0]  2082  	ldq_l	p6, ^x38(p4)			; re-read the bad block QW #7
         BCC40038 [0062E4]  2083  	stq_c	p6, ^x38(p4)			; now store it to force scrub
         63FF4000 [0062E8]  2084  	mb
         44DF0006 [0062EC]  2085  	and	p6, r31, p6			; consumer of above
         E4C00001 [0062F0]  2086  	beq	p6, sys__mchk_scrub_done	; these 2 lines......
                  [0062F4]  2087  	PVC_VIOLATE <1006>
File: ev6_pal_macros.mar
                  [0062F4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         C3FFFFFF [0062F4]  2088  	br	r31, .-4			; .....stop pre-fetching
                  [0062F8]  2089  
                  [0062F8]  2090  sys__mchk_scrub_done:
         77FFA380 [0062F8]  2091  	hw_mtpr	r31, EV6__DTB_IA		; (7,1L) flush dtb
         47FF041F [0062FC]  2092  	bis	r31, r31, r31
         47FF041F [006300]  2093  	bis	r31, r31, r31
         47FF041F [006304]  2094  	bis	r31, r31, r31
                  [006308]  2095  
         77FF2780 [006308]  2096  	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; wait for retire
                  [00630C]  2097  ;
                  [00630C]  2098  ; Now clear the chain and the interrupt and dc_stat.
                  [00630C]  2099  ;
                  [00630C]  2100  sys__mchk_clear_crd:
         44BF0417 [00630C]  2101  	bis	p5, r31, p23			; save base of logout frame
                  [006310]  2102  
                  [006310]  2103      .if eq force_path				; 1.41
                  [006310]  2104  	PVC_JSR	cbox, bsr=1
                  [006310]  2105  	bsr	p5, sys__cbox			; get the cbox error chain again
                  [006310]  2106      .iff
                  [006310]  2107  	PVC_VIOLATE <1008>			; 1.42 tell pvc to skip routine
                  [006310]  2108  	br	p5, sys__cbox
                  [006310]  2109      .endc					; 1.41
                  [006310]  2104I 	PVC_JSR	cbox, bsr=1
File: ev6_pal_macros.mar
                  [006310]   531i  pvc_lbl \pcv_index, \pcv_jsr_cbox0, osf
File: ev6_osf_system_pal.mar
         D0A00037 [006310]  2105I 	bsr	p5, sys__cbox			; get the cbox error chain again
                  [006314]  2110      
         46FF0405 [006314]  2111  	bis	p23, r31, p5			; base of mchk frame to p5
                  [006318]  2112  ;
                  [006318]  2113  ; Current state:
                  [006318]  2114  ;	p5		base of mchk logout frame
                  [006318]  2115  ;
         47E03407 [006318]  2116  	bis	r31, #1, p7			; get a 1
         48E3F727 [00631C]  2117  	sll	p7, #EV6__HW_INT_CLR__CR__S, p7	; shift into position
                  [006320]  2118  	PVC_VIOLATE <35>
File: ev6_pal_macros.mar
                  [006320]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E70E10 [006320]  2119  	hw_mtpr	p7, EV6__HW_INT_CLR		; (4,0L)
                  [006324]  2120  
                  [006324]  2121  	GET_16CONS	p7, EV6__DC_STAT__W1C_CRD, r31
File: ev6_pal_macros.mar
                  [006324]   249M 	ASSUME <<ev6__dc_stat__w1c_crd>> le  <^x7FFF>
         20FF000C [006324]   250M 	lda	p7,<ev6__dc_stat__w1c_crd>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E72A40 [006328]  2122  	hw_mtpr p7, EV6__DC_STAT		; (6,0L)
         47FF041F [00632C]  2123  	bis	r31, r31 ,r31
         47FF041F [006330]  2124  	bis	r31, r31 ,r31
         47FF041F [006334]  2125  	bis	r31, r31 ,r31
                  [006338]  2126  
         77FF2750 [006338]  2127  	hw_mtpr	r31, <EV6__MM_STAT ! ^x50>	; stall till they retire
                  [00633C]  2128  
                  [00633C]  2129  ;+
                  [00633C]  2130  ; Now turn mchk into a processor corrected machine check.
                  [00633C]  2131  ; Re-write the mces, SCBV, and code value.
                  [00633C]  2132  ; Get the cbox registers from the machine logout frame.
                  [00633C]  2133  ;
                  [00633C]  2134  ;	p5		base of mchk logout frame
                  [00633C]  2135  ;	PT__STACK_PC	exc_addr
                  [00633C]  2136  ;-
                  [00633C]  2137  sys__mchk_to_crd:
         6ED51090 [00633C]  2138  	hw_ldq/p p_misc, PT__P_MISC(p_temp)	; recover p_misc
                  [006340]  2139  
         4AC050D7 [006340]  2140  	extbl	p_misc, #2, p23			; get mces
         4ACF1616 [006344]  2141  	zap	p_misc, #^x78, p_misc		; clean mchk_code and SCBv
                  [006348]  2142  
         4AE07686 [006348]  2143  	srl	p23, #MCES__DPC__S, p6		; get dpc
         F0DFFF25 [00634C]  2144  	blbs	p6, sys__perr_skip_frame	; dpc => don't build frame
                  [006350]  2145  
         46E09406 [006350]  2146  	bis	p23, #<1@MCES__PCE__S>, p6		; set MCES<PCE>
         48C21726 [006354]  2147  	sll	p6, #OSF_P_MISC__MCES__MCHK__S, p6	; shift into position
         46C60416 [006358]  2148  	bis	p_misc, p6, p_misc			; or back mces
                  [00635C]  2149  
         20DF0630 [00635C]  2150  	lda	p6, SCB__PROC_CORR_ERR(r31)		; SCB vector
         48C31726 [006360]  2151  	sll	p6, #OSF_P_MISC__SCBV__S, p6		; SCBv into position
         46C60416 [006364]  2152  	bis	p_misc, p6, p_misc			; or back scbv
                  [006368]  2153  
         20DF0086 [006368]  2154  	lda	p6, MCHK__CORR_ECC(r31)			; mchk code
         48C51726 [00636C]  2155  	sll	p6, #OSF_P_MISC__MCHK_CODE__S, p6	; mchk code into position
         46C60416 [006370]  2156  	bis	p_misc, p6, p_misc			; or back mchk code
                  [006374]  2157  
                  [006374]  2158  ;
                  [006374]  2159  ; Now compute where the crd frame is.
                  [006374]  2160  ; Current state:
                  [006374]  2161  ;	p5		base of mchk logout frame
                  [006374]  2162  ;
         44BF0414 [006374]  2163  	bis	p5, r31, p20				; move to p20
         20B4FF00 [006378]  2164  	lda	p5,  <MCHK_CRD__BASE - MCHK__BASE>(p20)	; compute crd base
                  [00637C]  2165  
         4AE05686 [00637C]  2166  	srl	p23, #MCES__PCE__S, p6			; get PCE
         F0DFFF15 [006380]  2167  	blbs	p6, sys__perr_second			; set => second error
                  [006384]  2168  
                  [006384]  2169  ;
                  [006384]  2170  ; Recover the cbox error registers and log them.
                  [006384]  2171  ;
                  [006384]  2172  ; Current state:
                  [006384]  2173  ;	p5	base of crd logout frame
                  [006384]  2174  ;	p20	base of mchk logout frame
                  [006384]  2175  ;
                  [006384]  2176  
         6C941030 [006384]  2177  	hw_ldq/p p4, MCHK__DC1_SYNDROME(p20)		; get syn1
         6CF41038 [006388]  2178  	hw_ldq/p p7, MCHK__DC0_SYNDROME(p20)		; get syn0
         7C851030 [00638C]  2179  	hw_stq/p p4, MCHK_CRD__DC1_SYNDROME(p5)		; store syn1
         7CE51038 [006390]  2180  	hw_stq/p p7, MCHK_CRD__DC0_SYNDROME(p5)		; store syn1
                  [006394]  2181  
         6C941040 [006394]  2182  	hw_ldq/p p4, MCHK__C_STAT(p20)			; get stat
         6CF41048 [006398]  2183  	hw_ldq/p p7, MCHK__C_STS(p20)			; get sts
         7C851040 [00639C]  2184  	hw_stq/p p4, MCHK_CRD__C_STAT(p5)		; store stat
         7CE51048 [0063A0]  2185  	hw_stq/p p7, MCHK_CRD__C_STS(p5)		; store sts
                  [0063A4]  2186  
         6C941028 [0063A4]  2187  	hw_ldq/p p4, MCHK__C_ADDR(p20)			; get addr
         7C851028 [0063A8]  2188  	hw_stq/p p4, MCHK_CRD__C_ADDR(p5)		; store addr
                  [0063AC]  2189  
         7FE51050 [0063AC]  2190  	hw_stq/p r31, MCHK_CRD__MM_STAT(p5)		; store 0 for mm_stat
                  [0063B0]  2191  
         6C941018 [0063B0]  2192  	hw_ldq/p p4, MCHK__I_STAT(p20)			; get i_stat
         6CF41020 [0063B4]  2193  	hw_ldq/p p7, MCHK__DC_STAT(p20)			; get dc_stat
         7C851018 [0063B8]  2194  	hw_stq/p p4, MCHK_CRD__I_STAT(p5)		; store i_stat
         7CE51020 [0063BC]  2195  	hw_stq/p p7, MCHK_CRD__DC_STAT(p5)		; store dc_stat
                  [0063C0]  2196  
         C3FFFE8D [0063C0]  2197  	br	r31, sys__crd_header			; merge to finish
                  [0063C4]  2198  
                  [0063C4]  2199  ;+
                  [0063C4]  2200  ; sys__double_machine_check
                  [0063C4]  2201  ;
                  [0063C4]  2202  ; A machine check was started, but mces <mchk> was already set.
                  [0063C4]  2203  ;
                  [0063C4]  2204  ; Current state:
                  [0063C4]  2205  ;	p23		exc_addr
                  [0063C4]  2206  ;-
                  [0063C4]  2207  sys__double_machine_check:				; halt on double
         229F0006 [0063C4]  2208  	lda	p20, HALT__DBL_MCHK(r31)		; halt code
         7E9510C8 [0063C8]  2209  	hw_stq/p p20, PT__HALT_CODE(p_temp)		; store code (??)
         C3FFF8EC [0063CC]  2210  	br	r31, trap__update_pcb_and_halt		; update and halt
                  [0063D0]  2211  ;+
                  [0063D0]  2212  ; sys__machine_check_while_in_pal
                  [0063D0]  2213  ;
                  [0063D0]  2214  ; A machine check exception was taken and exc_addr was a PAL PC.
                  [0063D0]  2215  ; ?? This can only occur on istream machine checks, as dstream machine
                  [0063D0]  2216  ; checks are deferred ??
                  [0063D0]  2217  ;-
                  [0063D0]  2218  sys__machine_check_while_in_pal:			; halt on in pal mode
         229F0007 [0063D0]  2219  	lda	p20, HALT__MCHK_FROM_PAL(r31)		; halt code
         7E9510C8 [0063D4]  2220  	hw_stq/p p20, PT__HALT_CODE(p_temp)		; store code (??)
         C3FFF8E9 [0063D8]  2221  	br	r31, trap__update_pcb_and_halt		; update and halt
                  [0063DC]  2222  ;+
                  [0063DC]  2223  ; sys__dc_tag_perr_while_in_pal
                  [0063DC]  2224  ;
                  [0063DC]  2225  ; A dc_tag_perr exception was taken and exc_addr was a PAL PC.
                  [0063DC]  2226  ;-
                  [0063DC]  2227  sys__dc_tag_perr_while_in_pal:			; halt on in pal mode
         229F0008 [0063DC]  2228  	lda	p20, HALT__DC_TAG_PERR_FROM_PAL(r31)	; halt code
         7E9510C8 [0063E0]  2229  	hw_stq/p p20, PT__HALT_CODE(p_temp)		; store code (??)
         C3FFF8E6 [0063E4]  2230  	br	r31, trap__update_pcb_and_halt		; update and halt
                  [0063E8]  2231  
                  [0063E8]  2232  ;+
                  [0063E8]  2233  ; sys__cbox
                  [0063E8]  2234  ;
                  [0063E8]  2235  ; Shift in cbox error register chain.
                  [0063E8]  2236  ;
                  [0063E8]  2237  ; External bus activity must be isolated from writes to the CBOX CSR.
                  [0063E8]  2238  ; This requires that all dstream and istream fills must be avoided until after
                  [0063E8]  2239  ; the MTPR update completes. An MB instruction can block dstream activity, but
                  [0063E8]  2240  ; blocking all istream fills including prefetches requires more extensive code.
                  [0063E8]  2241  ; Also, we assume that i_ctl<sbe>=3 in the normal case, and restore to that
                  [0063E8]  2242  ; value.
                  [0063E8]  2243  ;
                  [0063E8]  2244  ; The 'error' status is cleared when the first mfpr retires.
                  [0063E8]  2245  ;
                  [0063E8]  2246  ; We are going to shift 66 bits, even though the 4-bit cbox status field
                  [0063E8]  2247  ; is pass2 or later.
                  [0063E8]  2248  ;
                  [0063E8]  2249  ; Pass1
                  [0063E8]  2250  ; -----
                  [0063E8]  2251  ;  8	dc1_syndrome<7:0>	for the last fill scrubbed by dcache ECC checkers
                  [0063E8]  2252  ;  8	dc0_syndrome<7:0>	for the last fill scrubbed by dcache ECC checkers
                  [0063E8]  2253  ;  5	c_stat<4:0>		error status
                  [0063E8]  2254  ; 37	c_addr<6:42>		block address of last reported error (inverted!)
                  [0063E8]  2255  ;  2	raz<1:0>		padded zeros to get multiple of 6
                  [0063E8]  2256  ; --
                  [0063E8]  2257  ; 60 bits
                  [0063E8]  2258  ;
                  [0063E8]  2259  ; Pass2
                  [0063E8]  2260  ; -----
                  [0063E8]  2261  ;  8	dc1_syndrome<7:0>	for the last fill scrubbed by dcache ECC checkers
                  [0063E8]  2262  ;  8	dc0_syndrome<7:0>	for the last fill scrubbed by dcache ECC checkers
                  [0063E8]  2263  ;  5	c_stat<4:0>		error status
                  [0063E8]  2264  ;  4	c_sts<3:0>		captured status of bcache in init-mode
                  [0063E8]  2265  ; 37	c_addr<6:42>		block address of last reported error (inverted!)
                  [0063E8]  2266  ;  4	raz<3:0>		padded zeros to get multiple of 6
                  [0063E8]  2267  ; --
                  [0063E8]  2268  ; 66 bits
                  [0063E8]  2269  ;
                  [0063E8]  2270  ; Input:
                  [0063E8]  2271  ;	p5		return address
                  [0063E8]  2272  ;
                  [0063E8]  2273  ; Register Use:
                  [0063E8]  2274  ;	p4		scratch
                  [0063E8]  2275  ;	p6		scratch
                  [0063E8]  2276  ;	p20<59:52>	dc1_syndrome<7:0>
                  [0063E8]  2277  ;	   <51:44>	dc0_syndrome<7:0>
                  [0063E8]  2278  ;	   <43:39>	c_stat<4:0>
                  [0063E8]  2279  ;	   <38:35>	c_stst<3:0> (pass2 only)
                  [0063E8]  2280  ;
                  [0063E8]  2281  ;	pass1
                  [0063E8]  2282  ;	-----
                  [0063E8]  2283  ;	p7 <44:08>	c_addr<6:42>
                  [0063E8]  2284  ;	   <07:06>	raz
                  [0063E8]  2285  ;	   <05:00>	UNDEFINED
                  [0063E8]  2286  ;	pass2
                  [0063E8]  2287  ;	-----
                  [0063E8]  2288  ;	p7 <40:04>	c_addr<6:42>
                  [0063E8]  2289  ;	   <03:00>	raz
                  [0063E8]  2290  ;-
                  [0063E8]  2291  	ALIGN_FETCH_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [0063E8]   267i 	.align 4
File: ev6_osf_system_pal.mar
                  [0063F0]  2292  sys__cbox:
         63FF4000 [0063F0]  2293  	mb					; quiet the dstream
         64DF1110 [0063F4]  2294  	hw_mfpr	p6, EV6__I_CTL			; (4,0L) get i_ctl
         209FFCFF [0063F8]  2295  	lda	p4, ^xFCFF(r31)			; mask for clearing SBE bits
         44C40004 [0063FC]  2296  	and	p6, p4, p4			; clear SBE bits
                  [006400]  2297  
                  [006400]  2298  sbe_off_offset = <sys__cbox_sbe_off_done - sys__cbox_sbe_off>
                  [006400]  2299  
         77E41110 [006400]  2300  	hw_mtpr	p4, EV6__I_CTL			; (4,0L) write new i_ctl
         C0C00000 [006404]  2301  	br	p6, sys__cbox_sbe_off
                  [006408]  2302  sys__cbox_sbe_off:
         40C2B406 [006408]  2303  	addq	p6, #<sbe_off_offset+1>, p6	; past stall in palmode
         D3E00000 [00640C]  2304  	bsr	r31, .				; 1.50 stack push
                  [006410]  2305  	ALIGN_FETCH_BLOCK <^x47FF041F>		; 1.41 align
File: ev6_pal_macros.mar
                  [006410]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_system_pal.mar
         77FF1310 [006410]  2306  	hw_mtpr	r31, EV6__IC_FLUSH		; (4,0L) eliminate prefetches
         F7E00000 [006414]  2307  	bne	r31, .				; pvc #24
                  [006418]  2308  	PVC_JSR sbe_off				; synch and flush
File: ev6_pal_macros.mar
                  [006418]   531i  pvc_lbl \pcv_index, \pcv_jsr_sbe_off0, osf
File: ev6_osf_system_pal.mar
         7BE6A000 [006418]  2309  	hw_ret_stall (p6)			; 1.50 use ret, pop stack
                  [00641C]  2310  	PVC_JSR sbe_off, dest=1			; 1.41 br stops predictor
File: ev6_pal_macros.mar
                  [00641C]   534i  pvc_lbl \pcv_index, \pcv_jsr_sbe_off0, osf, \pcv_jsr_sbe_off0_inst
File: ev6_osf_system_pal.mar
                  [00641C]  2311  sys__cbox_sbe_off_done:
         C3E0000B [00641C]  2312  	br	r31, sys__cbox_touch1		; now pull in the next block
                  [006420]  2313  
                  [006420]  2314  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [006420]   275i 	.align 6
00000000 00000000 [006428]
00000000 00000000 [006430]
00000000 00000000 [006438]
File: ev6_osf_system_pal.mar
                  [006440]  2315  sys__cbox_over1:				; block 1
         43E17406 [006440]  2316  	addq	r31, #11, p6			; initialize shift count (11x)
         43FF0407 [006444]  2317  	addq	r31, r31, p7			; initialize shift data
         C3E00001 [006448]  2318  	br	r31, sys__cbox_over2		; go to block 2
                  [00644C]  2319  sys__cbox_touch1:				;
         C3E00003 [00644C]  2320  	br	r31, sys__cbox_touch2		; touch block 2
                  [006450]  2321  
                  [006450]  2322  sys__cbox_over2:				; block 2
         77FF2C40 [006450]  2323  	hw_mtpr	r31, EV6__SHIFT_CONTROL		; (6,0L) shift in 6 bits
         40C03526 [006454]  2324  	subq	p6, #1, p6			; decrement shift count
         C3E00001 [006458]  2325  	br	r31, sys__cbox_over3		; go to block 3
                  [00645C]  2326  sys__cbox_touch2:				;
         C3E00003 [00645C]  2327  	br	r31, sys__cbox_touch3		; touch block 3
                  [006460]  2328  
                  [006460]  2329  sys__cbox_over3:				; block 3
         77FF2740 [006460]  2330  	hw_mtpr	r31, <EV6__MM_STAT ! 64 >	; (6,0L) wait for shift
         44A03405 [006464]  2331  	bis	p5, #1, p5			; return in pal mode
         C3E00001 [006468]  2332  	br	r31, sys__cbox_over4		; go to block 4
                  [00646C]  2333  sys__cbox_touch3:				;
         C3E00003 [00646C]  2334  	br	r31, sys__cbox_touch4		; touch block 4
                  [006470]  2335  
                  [006470]  2336  sys__cbox_over4:				; block 4
         649F2B40 [006470]  2337  	hw_mfpr	p4, EV6__DATA			; (6,0L) read cbox data
         47FF041F [006474]  2338  	bis	r31, r31, r31			; nop
         C3E00001 [006478]  2339  	br	r31, sys__cbox_over5		; go to block 5
                  [00647C]  2340  sys__cbox_touch4:				;
         C3E00003 [00647C]  2341  	br	r31, sys__cbox_touch5		; touch block 5
                  [006480]  2342  
                  [006480]  2343  sys__cbox_over5:				; block 5
         4487F004 [006480]  2344  	and	p4, #^x3F, p4			; clean to <5:0>
         40870407 [006484]  2345  	addq	p4, p7, p7			; accumulate shift data
         C3E00001 [006488]  2346  	br	r31, sys__cbox_over6		; go to block 6
                  [00648C]  2347  sys__cbox_touch5:				;
         C3E00003 [00648C]  2348  	br	r31, sys__cbox_touch6		; touch block 6
                  [006490]  2349  
                  [006490]  2350  sys__cbox_over6:				; block 6
         E4C00007 [006490]  2351  	beq	p6, sys__cbox_over8		; branch if done
         47FF041F [006494]  2352  	bis	r31, r31, r31			; nop
         C3E00001 [006498]  2353  	br	r31, sys__cbox_over7		; go to block 7
                  [00649C]  2354  sys__cbox_touch6:				;
         C3E00003 [00649C]  2355  	br	r31, sys__cbox_touch7		; touch block 7
                  [0064A0]  2356  
                  [0064A0]  2357  sys__cbox_over7:				; block 7
         44FF0414 [0064A0]  2358  	bis	p7, r31, p20			; save before shifting
         48E0D727 [0064A4]  2359  	sll	p7, #6, p7			; shift data 6 bits left
         C3FFFFE9 [0064A8]  2360  	br	r31, sys__cbox_over2		; do next shift
                  [0064AC]  2361  sys__cbox_touch7:				;
         C3E00003 [0064AC]  2362  	br	r31, sys__cbox_touch8		; touch block 8
                  [0064B0]  2363  
                  [0064B0]  2364  sys__cbox_over8:				; block 8
         E7E00003 [0064B0]  2365  	beq	r31, sys__cbox_cbox_done	; predict not taken
                  [0064B4]  2366  	PVC_VIOLATE <1006>
File: ev6_pal_macros.mar
                  [0064B4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         C3FFFFFF [0064B4]  2367  	br	r31, .-4			; predict back into infinite loop
         47FF041F [0064B8]  2368  	bis	r31, r31, r31			;
                  [0064BC]  2369  sys__cbox_touch8:				;
         C3FFFFE0 [0064BC]  2370  	br	r31, sys__cbox_over1		; now start executing the shifts
                  [0064C0]  2371  
                  [0064C0]  2372  sys__cbox_cbox_done:				; now restore i_ctl
         64DF1110 [0064C0]  2373  	hw_mfpr	p6, EV6__I_CTL			; (4,0L) get i_ctl
         209F0300 [0064C4]  2374  	lda	p4, <3@EV6__I_CTL__SBE__S>(r31)	; sbe bits
         44C40404 [0064C8]  2375  	or	p6, p4, p4			; set SBE bits
         47FF041F [0064CC]  2376  	bis	r31, r31, r31
                  [0064D0]  2377  
         77E41110 [0064D0]  2378  	hw_mtpr	p4, EV6__I_CTL			; (4,0L) restore i_ctl
                  [0064D4]  2379  
                  [0064D4]  2380      .if eq force_path				; 1.41
                  [0064D4]  2381  	PVC_JSR cbox, bsr=1, dest=1
                  [0064D4]  2382  	hw_ret_stall (p5)			; return to caller with stall
                  [0064D4]  2383      .iff
                  [0064D4]  2384  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align
                  [0064D4]  2385  	PVC_JSR cbox_hack
                  [0064D4]  2386  	hw_jmp_stall (p5)			; return with jmp
                  [0064D4]  2387  	br	r31, .-4			; stop predictor
                  [0064D4]  2388      .endc					; 1.41
                  [0064D4]  2381I 	PVC_JSR cbox, bsr=1, dest=1
File: ev6_pal_macros.mar
                  [0064D4]   534i  pvc_lbl \pcv_index, \pcv_jsr_cbox0, osf, \pcv_jsr_cbox0_inst
File: ev6_osf_system_pal.mar
         7BE5A000 [0064D4]  2382I 	hw_ret_stall (p5)			; return to caller with stall
                  [0064D8]  2389      
                  [0064D8]  2390  ;+
                  [0064D8]  2391  ; sys__cserve
                  [0064D8]  2392  ;
                  [0064D8]  2393  ;-
                  [0064D8]  2394  sys__cserve:
                  [0064D8]  2395  
                  [0064D8]  2396  .if eq reference_platform
                  [0064D8]  2397  	hw_ret	(p23)
                  [0064D8]  2398  
                  [0064D8]  2399  .iff						; if eq reference_platform
                  [0064D8]  2400  
                  [0064D8]  2401      .if eq srm_console
                  [0064D8]  2402  
                  [0064D8]  2403  ;+
                  [0064D8]  2404  ; sys__cserve for non-srm_console
                  [0064D8]  2405  ;
                  [0064D8]  2406  ; Entry:
                  [0064D8]  2407  ;	r16 (a0)	function parameter
                  [0064D8]  2408  ;	r17 (a1)	function parameter
                  [0064D8]  2409  ;	r18 (a2)	function type
                  [0064D8]  2410  ;
                  [0064D8]  2411  ; Output parameters:
                  [0064D8]  2412  ;	r0 (v0)		result
                  [0064D8]  2413  ;
                  [0064D8]  2414  ;-
                  [0064D8]  2415  	cmpeq	r18, #CSERVE__JTOPAL, r0
                  [0064D8]  2416  	bne	r0, cfw__jtopal
                  [0064D8]  2417  
                  [0064D8]  2418  	cmpeq	r18, #CSERVE__RD_IMPURE, r0
                  [0064D8]  2419  	bne	r0, cfw__rd_impure
                  [0064D8]  2420  
                  [0064D8]  2421  	cmpeq	r18, #CSERVE__START, r0
                  [0064D8]  2422  	bne	r0, cfw__start
                  [0064D8]  2423  
                  [0064D8]  2424        .if ne dbm_serial_io			; dbm serial io
                  [0064D8]  2425  ;
                  [0064D8]  2426  ; The cserves below and the supporting i/o routines are called in by the
                  [0064D8]  2427  ; SROM_CSERVES and SROM_IO_FUNCTIONS macros found at the end of this module.
                  [0064D8]  2428  ;
                  [0064D8]  2429  	cmpeq	r18, #CSERVE_K_SROM_INIT, r0
                  [0064D8]  2430  	bne	r0, Sys_Cserve_Srom_Init
                  [0064D8]  2431  
                  [0064D8]  2432  	cmpeq	r18, #CSERVE_K_SROM_PUTC, r0
                  [0064D8]  2433  	bne	r0, Sys_Cserve_Srom_Putc
                  [0064D8]  2434  
                  [0064D8]  2435  	cmpeq	r18, #CSERVE_K_SROM_GETC, r0
                  [0064D8]  2436  	bne	r0, Sys_Cserve_Srom_Getc
                  [0064D8]  2437  
                  [0064D8]  2438        .endc					; if ne dbm_serial_io
                  [0064D8]  2439  
                  [0064D8]  2440  	hw_ret	(p23)				; return, nothing done
                  [0064D8]  2441  
                  [0064D8]  2442  
                  [0064D8]  2443  ;+
                  [0064D8]  2444  ; CSERVE__START
                  [0064D8]  2445  ;-
                  [0064D8]  2446  cfw__start:
                  [0064D8]  2447  	br	r31, sys__exit_console
                  [0064D8]  2448  
                  [0064D8]  2449  ;+
                  [0064D8]  2450  ; CSERVE_JTOPAL
                  [0064D8]  2451  ;
                  [0064D8]  2452  ; Function:
                  [0064D8]  2453  ;	Transfer control to the specified address, passed in
                  [0064D8]  2454  ;	r16 (a0), in PALmode.
                  [0064D8]  2455  ;
                  [0064D8]  2456  ;	Write the signature
                  [0064D8]  2457  ;	Flush Icache
                  [0064D8]  2458  ;	Dispatch to new PALcode
                  [0064D8]  2459  ;
                  [0064D8]  2460  ; Current state:
                  [0064D8]  2461  ;	r16 (a0)	transfer address
                  [0064D8]  2462  ;
                  [0064D8]  2463  ; Exit state::
                  [0064D8]  2464  ;	r1		dc_ctl
                  [0064D8]  2465  ;	r15		srom_rev
                  [0064D8]  2466  ;	r16		proc_id
                  [0064D8]  2467  ;	r17		mem_size
                  [0064D8]  2468  ;	r18		cycle_cnt
                  [0064D8]  2469  ;	r19		signature in <31:16>
                  [0064D8]  2470  ;	r20		proc_mask (note: we are stepping on shadow!)
                  [0064D8]  2471  ;	r21		sysctx (note: we are stepping on shadow!)
                  [0064D8]  2472  ;	other registers UNPREDICTABLE
                  [0064D8]  2473  ;-
                  [0064D8]  2474  	ALIGN_FETCH_BLOCK
                  [0064D8]  2475  
                  [0064D8]  2476  cfw__jtopal:
                  [0064D8]  2477  	bis	r16, #1, r27			; insure PALmode
                  [0064D8]  2478  
                  [0064D8]  2479  	hw_ldq/p r21, PT__IMPURE(p_temp)	; get pt_impure base address
                  [0064D8]  2480  
                  [0064D8]  2481  	hw_ldq/p r1, CNS__DC_CTL(r21)		; get dc_ctl value
                  [0064D8]  2482  	hw_ldq/p r2, CNS__WRITE_MANY(r21)	; get write many chain
                  [0064D8]  2483  	sll	r2, #16, r2			; shift into place
                  [0064D8]  2484  	bis	r1, r2, r1			; OR into dc_ctl parameter
                  [0064D8]  2485  
                  [0064D8]  2486  	hw_ldq/p r15, CNS__SROM_REV(r21)	; encoded srom.s RCS revision
                  [0064D8]  2487  	hw_ldq/p r16, CNS__PROC_ID(r21)		; processor identification
                  [0064D8]  2488  						; (a la SRM)
                  [0064D8]  2489  	hw_ldq/p r17, CNS__MEM_SIZE(r21)	; size of contiguous,
                  [0064D8]  2490  						; good memory in bytes
                  [0064D8]  2491  	hw_ldq/p r18, CNS__CYCLE_CNT(r21)	; cycle count in picoseconds
                  [0064D8]  2492  	hw_ldq/p r19, CNS__SIGNATURE(r21)	; signature (0xDECB) in <31:16>
                  [0064D8]  2493  						; system revision ID in <15:0>
                  [0064D8]  2494  	hw_ldq/p r20, CNS__PROC_MASK(r21)	; active processor mask
                  [0064D8]  2495  ;
                  [0064D8]  2496  ; The following load trashes p_temp, but we don't need it any more.
                  [0064D8]  2497  ;
                  [0064D8]  2498  	hw_ldq/p r21, CNS__SYSCTX(r21)		; system context value
                  [0064D8]  2499  
                  [0064D8]  2500  	mb
                  [0064D8]  2501  
                  [0064D8]  2502  	bsr	r31, .				; push prediction stack
                  [0064D8]  2503  	hw_mtpr	r31, EV6__IC_FLUSH		; (4,0L) flush icache
                  [0064D8]  2504  	bne	r31, .				; pvc #24
                  [0064D8]  2505  	PVC_VIOLATE <1007>
                  [0064D8]  2506  	hw_ret_stall (r27)			; pop prediction stack
                  [0064D8]  2507  						; go off to new PALcode
                  [0064D8]  2508  
                  [0064D8]  2509  ;+
                  [0064D8]  2510  ; CSERVE_RD_IMPURE
                  [0064D8]  2511  ;
                  [0064D8]  2512  ; Function:
                  [0064D8]  2513  ;	Return impure pointer.
                  [0064D8]  2514  ;
                  [0064D8]  2515  ; Exit state:
                  [0064D8]  2516  ;	r0 (v0)		impure pointer
                  [0064D8]  2517  ;-
                  [0064D8]  2518  
                  [0064D8]  2519  	ALIGN_FETCH_BLOCK
                  [0064D8]  2520  cfw__rd_impure:
                  [0064D8]  2521  	hw_ldq/p r0, PT__IMPURE(p_temp)		; get impure pointer
                  [0064D8]  2522  	hw_ret	(p23)
                  [0064D8]  2523  
                  [0064D8]  2524  
                  [0064D8]  2525      .iff					; if eq srm_console
                  [0064D8]  2526  ;+
                  [0064D8]  2527  ; SRM console cserve
                  [0064D8]  2528  ;
                  [0064D8]  2529  ; Entry:
                  [0064D8]  2530  ;	r16	option selector
                  [0064D8]  2531  ;	r17...	arguments
                  [0064D8]  2532  ;-
                  [0064D8]  2533  	cmpeq	r16, #CSERVE__START, r0
                  [0064D8]  2534  	bne	r0, cfw__start
                  [0064D8]  2535  	cmpeq	r16, #CSERVE__CALLBACK, r0
                  [0064D8]  2536  	bne	r0, cfw__callback
                  [0064D8]  2537  	hw_ret	(p23)				; return, nothing done
                  [0064D8]  2538  ;
                  [0064D8]  2539  ; CSERVE__START
                  [0064D8]  2540  ;
                  [0064D8]  2541  cfw__start:
                  [0064D8]  2542  	br	r31, sys__exit_console
                  [0064D8]  2543  ;
                  [0064D8]  2544  ; CSERVE__CALLBACK
                  [0064D8]  2545  ;
                  [0064D8]  2546  ; Question: Do we need to update the PCB? Some implementations do, some
                  [0064D8]  2547  ; don't, so it's probably a don't care. For now, update the pcb
                  [0064D8]  2548  ;
                  [0064D8]  2549  ; Note that previous implementations restore r16 from r1. Is this
                  [0064D8]  2550  ; a console requirement???
                  [0064D8]  2551  ;
                  [0064D8]  2552  cfw__callback:
                  [0064D8]  2553  	bis	r1, r31, r16			; restore r16 (for console??)
                  [0064D8]  2554  	lda	p20, HALT__CALLBACK(r31)	; reason for halt
                  [0064D8]  2555  	hw_stq/p p20, PT__HALT_CODE(p_temp)	; store code (??)
                  [0064D8]  2556  
                  [0064D8]  2557  	br	r31, trap__update_pcb_and_halt	; update pcb and enter console
                  [0064D8]  2558  
                  [0064D8]  2559      .endc					; if eq srm_console
                  [0064D8]  2560  .endc						; if eq reference_platform
                  [0064D8]  2400I 
                  [0064D8]  2401I     .if eq srm_console
                  [0064D8]  2402I 
                  [0064D8]  2403I ;+
                  [0064D8]  2404I ; sys__cserve for non-srm_console
                  [0064D8]  2405I ;
                  [0064D8]  2406I ; Entry:
                  [0064D8]  2407I ;	r16 (a0)	function parameter
                  [0064D8]  2408I ;	r17 (a1)	function parameter
                  [0064D8]  2409I ;	r18 (a2)	function type
                  [0064D8]  2410I ;
                  [0064D8]  2411I ; Output parameters:
                  [0064D8]  2412I ;	r0 (v0)		result
                  [0064D8]  2413I ;
                  [0064D8]  2414I ;-
                  [0064D8]  2415I 	cmpeq	r18, #CSERVE__JTOPAL, r0
                  [0064D8]  2416I 	bne	r0, cfw__jtopal
                  [0064D8]  2417I 
                  [0064D8]  2418I 	cmpeq	r18, #CSERVE__RD_IMPURE, r0
                  [0064D8]  2419I 	bne	r0, cfw__rd_impure
                  [0064D8]  2420I 
                  [0064D8]  2421I 	cmpeq	r18, #CSERVE__START, r0
                  [0064D8]  2422I 	bne	r0, cfw__start
                  [0064D8]  2423I 
                  [0064D8]  2424I       .if ne dbm_serial_io			; dbm serial io
                  [0064D8]  2425I ;
                  [0064D8]  2426I ; The cserves below and the supporting i/o routines are called in by the
                  [0064D8]  2427I ; SROM_CSERVES and SROM_IO_FUNCTIONS macros found at the end of this module.
                  [0064D8]  2428I ;
                  [0064D8]  2429I 	cmpeq	r18, #CSERVE_K_SROM_INIT, r0
                  [0064D8]  2430I 	bne	r0, Sys_Cserve_Srom_Init
                  [0064D8]  2431I 
                  [0064D8]  2432I 	cmpeq	r18, #CSERVE_K_SROM_PUTC, r0
                  [0064D8]  2433I 	bne	r0, Sys_Cserve_Srom_Putc
                  [0064D8]  2434I 
                  [0064D8]  2435I 	cmpeq	r18, #CSERVE_K_SROM_GETC, r0
                  [0064D8]  2436I 	bne	r0, Sys_Cserve_Srom_Getc
                  [0064D8]  2437I 
                  [0064D8]  2438I       .endc					; if ne dbm_serial_io
                  [0064D8]  2439I 
                  [0064D8]  2440I 	hw_ret	(p23)				; return, nothing done
                  [0064D8]  2441I 
                  [0064D8]  2442I 
                  [0064D8]  2443I ;+
                  [0064D8]  2444I ; CSERVE__START
                  [0064D8]  2445I ;-
                  [0064D8]  2446I cfw__start:
                  [0064D8]  2447I 	br	r31, sys__exit_console
                  [0064D8]  2448I 
                  [0064D8]  2449I ;+
                  [0064D8]  2450I ; CSERVE_JTOPAL
                  [0064D8]  2451I ;
                  [0064D8]  2452I ; Function:
                  [0064D8]  2453I ;	Transfer control to the specified address, passed in
                  [0064D8]  2454I ;	r16 (a0), in PALmode.
                  [0064D8]  2455I ;
                  [0064D8]  2456I ;	Write the signature
                  [0064D8]  2457I ;	Flush Icache
                  [0064D8]  2458I ;	Dispatch to new PALcode
                  [0064D8]  2459I ;
                  [0064D8]  2460I ; Current state:
                  [0064D8]  2461I ;	r16 (a0)	transfer address
                  [0064D8]  2462I ;
                  [0064D8]  2463I ; Exit state::
                  [0064D8]  2464I ;	r1		dc_ctl
                  [0064D8]  2465I ;	r15		srom_rev
                  [0064D8]  2466I ;	r16		proc_id
                  [0064D8]  2467I ;	r17		mem_size
                  [0064D8]  2468I ;	r18		cycle_cnt
                  [0064D8]  2469I ;	r19		signature in <31:16>
                  [0064D8]  2470I ;	r20		proc_mask (note: we are stepping on shadow!)
                  [0064D8]  2471I ;	r21		sysctx (note: we are stepping on shadow!)
                  [0064D8]  2472I ;	other registers UNPREDICTABLE
                  [0064D8]  2473I ;-
                  [0064D8]  2474I 	ALIGN_FETCH_BLOCK
                  [0064D8]  2475I 
                  [0064D8]  2476I cfw__jtopal:
                  [0064D8]  2477I 	bis	r16, #1, r27			; insure PALmode
                  [0064D8]  2478I 
                  [0064D8]  2479I 	hw_ldq/p r21, PT__IMPURE(p_temp)	; get pt_impure base address
                  [0064D8]  2480I 
                  [0064D8]  2481I 	hw_ldq/p r1, CNS__DC_CTL(r21)		; get dc_ctl value
                  [0064D8]  2482I 	hw_ldq/p r2, CNS__WRITE_MANY(r21)	; get write many chain
                  [0064D8]  2483I 	sll	r2, #16, r2			; shift into place
                  [0064D8]  2484I 	bis	r1, r2, r1			; OR into dc_ctl parameter
                  [0064D8]  2485I 
                  [0064D8]  2486I 	hw_ldq/p r15, CNS__SROM_REV(r21)	; encoded srom.s RCS revision
                  [0064D8]  2487I 	hw_ldq/p r16, CNS__PROC_ID(r21)		; processor identification
                  [0064D8]  2488I 						; (a la SRM)
                  [0064D8]  2489I 	hw_ldq/p r17, CNS__MEM_SIZE(r21)	; size of contiguous,
                  [0064D8]  2490I 						; good memory in bytes
                  [0064D8]  2491I 	hw_ldq/p r18, CNS__CYCLE_CNT(r21)	; cycle count in picoseconds
                  [0064D8]  2492I 	hw_ldq/p r19, CNS__SIGNATURE(r21)	; signature (0xDECB) in <31:16>
                  [0064D8]  2493I 						; system revision ID in <15:0>
                  [0064D8]  2494I 	hw_ldq/p r20, CNS__PROC_MASK(r21)	; active processor mask
                  [0064D8]  2495I ;
                  [0064D8]  2496I ; The following load trashes p_temp, but we don't need it any more.
                  [0064D8]  2497I ;
                  [0064D8]  2498I 	hw_ldq/p r21, CNS__SYSCTX(r21)		; system context value
                  [0064D8]  2499I 
                  [0064D8]  2500I 	mb
                  [0064D8]  2501I 
                  [0064D8]  2502I 	bsr	r31, .				; push prediction stack
                  [0064D8]  2503I 	hw_mtpr	r31, EV6__IC_FLUSH		; (4,0L) flush icache
                  [0064D8]  2504I 	bne	r31, .				; pvc #24
                  [0064D8]  2505I 	PVC_VIOLATE <1007>
                  [0064D8]  2506I 	hw_ret_stall (r27)			; pop prediction stack
                  [0064D8]  2507I 						; go off to new PALcode
                  [0064D8]  2508I 
                  [0064D8]  2509I ;+
                  [0064D8]  2510I ; CSERVE_RD_IMPURE
                  [0064D8]  2511I ;
                  [0064D8]  2512I ; Function:
                  [0064D8]  2513I ;	Return impure pointer.
                  [0064D8]  2514I ;
                  [0064D8]  2515I ; Exit state:
                  [0064D8]  2516I ;	r0 (v0)		impure pointer
                  [0064D8]  2517I ;-
                  [0064D8]  2518I 
                  [0064D8]  2519I 	ALIGN_FETCH_BLOCK
                  [0064D8]  2520I cfw__rd_impure:
                  [0064D8]  2521I 	hw_ldq/p r0, PT__IMPURE(p_temp)		; get impure pointer
                  [0064D8]  2522I 	hw_ret	(p23)
                  [0064D8]  2523I 
                  [0064D8]  2524I 
                  [0064D8]  2525I     .iff					; if eq srm_console
                  [0064D8]  2526I ;+
                  [0064D8]  2527I ; SRM console cserve
                  [0064D8]  2528I ;
                  [0064D8]  2529I ; Entry:
                  [0064D8]  2530I ;	r16	option selector
                  [0064D8]  2531I ;	r17...	arguments
                  [0064D8]  2532I ;-
                  [0064D8]  2533I 	cmpeq	r16, #CSERVE__START, r0
                  [0064D8]  2534I 	bne	r0, cfw__start
                  [0064D8]  2535I 	cmpeq	r16, #CSERVE__CALLBACK, r0
                  [0064D8]  2536I 	bne	r0, cfw__callback
                  [0064D8]  2537I 	hw_ret	(p23)				; return, nothing done
                  [0064D8]  2538I ;
                  [0064D8]  2539I ; CSERVE__START
                  [0064D8]  2540I ;
                  [0064D8]  2541I cfw__start:
                  [0064D8]  2542I 	br	r31, sys__exit_console
                  [0064D8]  2543I ;
                  [0064D8]  2544I ; CSERVE__CALLBACK
                  [0064D8]  2545I ;
                  [0064D8]  2546I ; Question: Do we need to update the PCB? Some implementations do, some
                  [0064D8]  2547I ; don't, so it's probably a don't care. For now, update the pcb
                  [0064D8]  2548I ;
                  [0064D8]  2549I ; Note that previous implementations restore r16 from r1. Is this
                  [0064D8]  2550I ; a console requirement???
                  [0064D8]  2551I ;
                  [0064D8]  2552I cfw__callback:
                  [0064D8]  2553I 	bis	r1, r31, r16			; restore r16 (for console??)
                  [0064D8]  2554I 	lda	p20, HALT__CALLBACK(r31)	; reason for halt
                  [0064D8]  2555I 	hw_stq/p p20, PT__HALT_CODE(p_temp)	; store code (??)
                  [0064D8]  2556I 
                  [0064D8]  2557I 	br	r31, trap__update_pcb_and_halt	; update pcb and enter console
                  [0064D8]  2558I 
                  [0064D8]  2559I     .endc					; if eq srm_console
                  [0064D8]  2402I 
                  [0064D8]  2403I ;+
                  [0064D8]  2404I ; sys__cserve for non-srm_console
                  [0064D8]  2405I ;
                  [0064D8]  2406I ; Entry:
                  [0064D8]  2407I ;	r16 (a0)	function parameter
                  [0064D8]  2408I ;	r17 (a1)	function parameter
                  [0064D8]  2409I ;	r18 (a2)	function type
                  [0064D8]  2410I ;
                  [0064D8]  2411I ; Output parameters:
                  [0064D8]  2412I ;	r0 (v0)		result
                  [0064D8]  2413I ;
                  [0064D8]  2414I ;-
         424135A0 [0064D8]  2415I 	cmpeq	r18, #CSERVE__JTOPAL, r0
         F400000C [0064DC]  2416I 	bne	r0, cfw__jtopal
                  [0064E0]  2417I 
         424175A0 [0064E0]  2418I 	cmpeq	r18, #CSERVE__RD_IMPURE, r0
         F400001E [0064E4]  2419I 	bne	r0, cfw__rd_impure
                  [0064E8]  2420I 
         424035A0 [0064E8]  2421I 	cmpeq	r18, #CSERVE__START, r0
         F4000007 [0064EC]  2422I 	bne	r0, cfw__start
                  [0064F0]  2423I 
                  [0064F0]  2424I       .if ne dbm_serial_io			; dbm serial io
                  [0064F0]  2425I ;
                  [0064F0]  2426I ; The cserves below and the supporting i/o routines are called in by the
                  [0064F0]  2427I ; SROM_CSERVES and SROM_IO_FUNCTIONS macros found at the end of this module.
                  [0064F0]  2428I ;
                  [0064F0]  2429I 	cmpeq	r18, #CSERVE_K_SROM_INIT, r0
                  [0064F0]  2430I 	bne	r0, Sys_Cserve_Srom_Init
                  [0064F0]  2431I 
                  [0064F0]  2432I 	cmpeq	r18, #CSERVE_K_SROM_PUTC, r0
                  [0064F0]  2433I 	bne	r0, Sys_Cserve_Srom_Putc
                  [0064F0]  2434I 
                  [0064F0]  2435I 	cmpeq	r18, #CSERVE_K_SROM_GETC, r0
                  [0064F0]  2436I 	bne	r0, Sys_Cserve_Srom_Getc
                  [0064F0]  2437I 
                  [0064F0]  2438I       .endc					; if ne dbm_serial_io
                  [0064F0]  2425I ;
                  [0064F0]  2426I ; The cserves below and the supporting i/o routines are called in by the
                  [0064F0]  2427I ; SROM_CSERVES and SROM_IO_FUNCTIONS macros found at the end of this module.
                  [0064F0]  2428I ;
         424315A0 [0064F0]  2429I 	cmpeq	r18, #CSERVE_K_SROM_INIT, r0
         F40001BA [0064F4]  2430I 	bne	r0, Sys_Cserve_Srom_Init
                  [0064F8]  2431I 
         424335A0 [0064F8]  2432I 	cmpeq	r18, #CSERVE_K_SROM_PUTC, r0
         F40001C0 [0064FC]  2433I 	bne	r0, Sys_Cserve_Srom_Putc
                  [006500]  2434I 
         424415A0 [006500]  2435I 	cmpeq	r18, #CSERVE_K_SROM_GETC, r0
         F40001C2 [006504]  2436I 	bne	r0, Sys_Cserve_Srom_Getc
                  [006508]  2437I 
                  [006508]  2439I       
         7BF78000 [006508]  2440I 	hw_ret	(p23)				; return, nothing done
                  [00650C]  2441I 
                  [00650C]  2442I 
                  [00650C]  2443I ;+
                  [00650C]  2444I ; CSERVE__START
                  [00650C]  2445I ;-
                  [00650C]  2446I cfw__start:
         C3E0005C [00650C]  2447I 	br	r31, sys__exit_console
                  [006510]  2448I 
                  [006510]  2449I ;+
                  [006510]  2450I ; CSERVE_JTOPAL
                  [006510]  2451I ;
                  [006510]  2452I ; Function:
                  [006510]  2453I ;	Transfer control to the specified address, passed in
                  [006510]  2454I ;	r16 (a0), in PALmode.
                  [006510]  2455I ;
                  [006510]  2456I ;	Write the signature
                  [006510]  2457I ;	Flush Icache
                  [006510]  2458I ;	Dispatch to new PALcode
                  [006510]  2459I ;
                  [006510]  2460I ; Current state:
                  [006510]  2461I ;	r16 (a0)	transfer address
                  [006510]  2462I ;
                  [006510]  2463I ; Exit state::
                  [006510]  2464I ;	r1		dc_ctl
                  [006510]  2465I ;	r15		srom_rev
                  [006510]  2466I ;	r16		proc_id
                  [006510]  2467I ;	r17		mem_size
                  [006510]  2468I ;	r18		cycle_cnt
                  [006510]  2469I ;	r19		signature in <31:16>
                  [006510]  2470I ;	r20		proc_mask (note: we are stepping on shadow!)
                  [006510]  2471I ;	r21		sysctx (note: we are stepping on shadow!)
                  [006510]  2472I ;	other registers UNPREDICTABLE
                  [006510]  2473I ;-
                  [006510]  2474I 	ALIGN_FETCH_BLOCK
File: ev6_pal_macros.mar
                  [006510]   267i 	.align 4
File: ev6_osf_system_pal.mar
                  [006510]  2475I 
                  [006510]  2476I cfw__jtopal:
         4600341B [006510]  2477I 	bis	r16, #1, r27			; insure PALmode
                  [006514]  2478I 
         6EB51088 [006514]  2479I 	hw_ldq/p r21, PT__IMPURE(p_temp)	; get pt_impure base address
                  [006518]  2480I 
         6C351398 [006518]  2481I 	hw_ldq/p r1, CNS__DC_CTL(r21)		; get dc_ctl value
         6C5513A8 [00651C]  2482I 	hw_ldq/p r2, CNS__WRITE_MANY(r21)	; get write many chain
         48421722 [006520]  2483I 	sll	r2, #16, r2			; shift into place
         44220401 [006524]  2484I 	bis	r1, r2, r1			; OR into dc_ctl parameter
                  [006528]  2485I 
         6DF51270 [006528]  2486I 	hw_ldq/p r15, CNS__SROM_REV(r21)	; encoded srom.s RCS revision
         6E151278 [00652C]  2487I 	hw_ldq/p r16, CNS__PROC_ID(r21)		; processor identification
                  [006530]  2488I 						; (a la SRM)
         6E351280 [006530]  2489I 	hw_ldq/p r17, CNS__MEM_SIZE(r21)	; size of contiguous,
                  [006534]  2490I 						; good memory in bytes
         6E551288 [006534]  2491I 	hw_ldq/p r18, CNS__CYCLE_CNT(r21)	; cycle count in picoseconds
         6E751290 [006538]  2492I 	hw_ldq/p r19, CNS__SIGNATURE(r21)	; signature (0xDECB) in <31:16>
                  [00653C]  2493I 						; system revision ID in <15:0>
         6E951298 [00653C]  2494I 	hw_ldq/p r20, CNS__PROC_MASK(r21)	; active processor mask
                  [006540]  2495I ;
                  [006540]  2496I ; The following load trashes p_temp, but we don't need it any more.
                  [006540]  2497I ;
         6EB512A0 [006540]  2498I 	hw_ldq/p r21, CNS__SYSCTX(r21)		; system context value
                  [006544]  2499I 
         63FF4000 [006544]  2500I 	mb
                  [006548]  2501I 
         D3E00000 [006548]  2502I 	bsr	r31, .				; push prediction stack
         77FF1310 [00654C]  2503I 	hw_mtpr	r31, EV6__IC_FLUSH		; (4,0L) flush icache
         F7E00000 [006550]  2504I 	bne	r31, .				; pvc #24
                  [006554]  2505I 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [006554]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         7BFBA000 [006554]  2506I 	hw_ret_stall (r27)			; pop prediction stack
                  [006558]  2507I 						; go off to new PALcode
                  [006558]  2508I 
                  [006558]  2509I ;+
                  [006558]  2510I ; CSERVE_RD_IMPURE
                  [006558]  2511I ;
                  [006558]  2512I ; Function:
                  [006558]  2513I ;	Return impure pointer.
                  [006558]  2514I ;
                  [006558]  2515I ; Exit state:
                  [006558]  2516I ;	r0 (v0)		impure pointer
                  [006558]  2517I ;-
                  [006558]  2518I 
                  [006558]  2519I 	ALIGN_FETCH_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [006558]   267i 	.align 4
File: ev6_osf_system_pal.mar
                  [006560]  2520I cfw__rd_impure:
         6C151088 [006560]  2521I 	hw_ldq/p r0, PT__IMPURE(p_temp)		; get impure pointer
         7BF78000 [006564]  2522I 	hw_ret	(p23)
                  [006568]  2523I 
                  [006568]  2524I 
                  [006568]  2561      
                  [006568]  2562  
                  [006568]  2563  ;+
                  [006568]  2564  ; sys__switch_unknown
                  [006568]  2565  ;
                  [006568]  2566  ; Entry:
                  [006568]  2567  ;	PALcode must have done a jump through 0 somehow.
                  [006568]  2568  ;-
                  [006568]  2569  sys__switch_unknown:
         229F0040 [006568]  2570  	lda	p20, HALT__JUMP0(r31)		; halt code of jump0
         7E9510C8 [00656C]  2571  	hw_stq/p p20, PT__HALT_CODE(p_temp)	; store halt code
         C3E00003 [006570]  2572  	br	r31, sys__enter_console		; enter console
                  [006574]  2573  
                  [006574]  2574  ;+
                  [006574]  2575  ; sys__enter_console
                  [006574]  2576  ;
                  [006574]  2577  ; Current state:
                  [006574]  2578  ;	p20	halt code
                  [006574]  2579  ;	p23	pc of halt or offending instruction
                  [006574]  2580  ;-
                  [006574]  2581  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [006574]   275i 	.align 6
         00000000 [00657C]
File: ev6_osf_system_pal.mar
                  [006580]  2582  sys__enter_console:
                  [006580]  2583  	PVC_JSR save_state, bsr=1
File: ev6_pal_macros.mar
                  [006580]   531i  pvc_lbl \pcv_index, \pcv_jsr_save_state0, osf
File: ev6_osf_system_pal.mar
         D0FFF88B [006580]  2584  	bsr	p7, pal__save_state		; save state
                  [006584]  2585  
         77FF0310 [006584]  2586  	hw_mtpr	r31, EV6__ITB_IA		; (4,0L) flush itb
         77FFA380 [006588]  2587  	hw_mtpr	r31, EV6__DTB_IA		; (7,1L) flush dtb
                  [00658C]  2588  ;
                  [00658C]  2589  ; Clear IER_CM, turning off interrupts, and setting mode to kernel.
                  [00658C]  2590  ; Don't bother for now with SIRR, ASTRR, HW_INT_CLR, etc.
                  [00658C]  2591  ;
                  [00658C]  2592  	NOP					; pad fetch block
File: ev6_pal_macros.mar
         47FF041F [00658C]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [006590]  2593  	NOP
File: ev6_pal_macros.mar
         47FF041F [006590]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [006594]  2594  	NOP
File: ev6_pal_macros.mar
         47FF041F [006594]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
         77FF0B10 [006598]  2595  	hw_mtpr	r31, EV6__IER_CM		; (4,0L) no interrupts
                  [00659C]  2596  	NOP
File: ev6_pal_macros.mar
         47FF041F [00659C]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0065A0]  2597  	NOP
File: ev6_pal_macros.mar
         47FF041F [0065A0]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0065A4]  2598  	NOP					; pad fetch block
File: ev6_pal_macros.mar
         47FF041F [0065A4]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0065A8]  2599  ;
                  [0065A8]  2600  ; Clear DTB_ASNx and ASN.
                  [0065A8]  2601  ;
                  [0065A8]  2602  ; There must be a scoreboard bit -> register dependency chain to prevent
                  [0065A8]  2603  ; hw_mtpr DTB_ASx from issuing while ANY of scoreboard bits <7:4> are set.
                  [0065A8]  2604  ;
         643F10F0 [0065A8]  2605  	hw_mfpr	r1, <EV6__PAL_BASE ! ^xF0>	; (4-7,0L)
         44210801 [0065AC]  2606  	xor	r1, r1, r1			; zap r1
                  [0065B0]  2607  	NOP					; ensure different block
File: ev6_pal_macros.mar
         47FF041F [0065B0]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0065B4]  2608  	NOP					; ensure different block
File: ev6_pal_macros.mar
         47FF041F [0065B4]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0065B8]  2609  
         77E12510 [0065B8]  2610  	hw_mtpr r1, EV6__DTB_ASN0		; (4,0L) clear ASN
         77E1A580 [0065BC]  2611  	hw_mtpr r1, EV6__DTB_ASN1		; (7,1L) clear ASN
                  [0065C0]  2612  	NOP
File: ev6_pal_macros.mar
         47FF041F [0065C0]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0065C4]  2613  	NOP
File: ev6_pal_macros.mar
         47FF041F [0065C4]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0065C8]  2614  
         77FF4110 [0065C8]  2615  	hw_mtpr	r31, EV6__ASN			; (4,0L) clear ASN
                  [0065CC]  2616  	NOP
File: ev6_pal_macros.mar
         47FF041F [0065CC]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0065D0]  2617  	NOP
File: ev6_pal_macros.mar
         47FF041F [0065D0]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0065D4]  2618  	NOP
File: ev6_pal_macros.mar
         47FF041F [0065D4]   283M 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0065D8]  2619  ;
                  [0065D8]  2620  ; Clear out vptb. Switch us to 48-bit mode in VA_CTL so that the 1-1 console
                  [0065D8]  2621  ; can access I/O. Write I_CTL twice (pvc #31).
                  [0065D8]  2622  ;
         647F1110 [0065D8]  2623  	hw_mfpr	r3, EV6__I_CTL				; (4,0L) get i_ctl
         48645723 [0065DC]  2624  	sll	r3, #<64 - EV6__I_CTL__VPTB__S>, r3	; clean
         48645683 [0065E0]  2625  	srl	r3, #<64 - EV6__I_CTL__VPTB__S>, r3	; move back
         7FF51000 [0065E4]  2626  	hw_stq/p r31, PT__VPTB(p_temp)			; clear pt__vptb
                  [0065E8]  2627  
         77E31110 [0065E8]  2628  	hw_mtpr	r3, EV6__I_CTL				; (4,0L) write i_ctl
                  [0065EC]  2629  
         6C3510B8 [0065EC]  2630  	hw_ldq/p r1, PT__VA_CTL(p_temp)			; fetch va_ctl part
         44205401 [0065F0]  2631  	bis	r1, #<1@EV6__VA_CTL__VA_48__S>, r1	; or in 48-bit mode!
         7C3510B8 [0065F4]  2632  	hw_stq/p r1, PT__VA_CTL(p_temp)			; store va_ctl part
         77E1C420 [0065F8]  2633  	hw_mtpr	r1, EV6__VA_CTL				; (5,1L) write it
                  [0065FC]  2634  
         77E31110 [0065FC]  2635  	hw_mtpr r3, EV6__I_CTL				; (4,0L) pvc #31
                  [006600]  2636  ;
                  [006600]  2637  ; The rest of this code is very implementation dependent. It depends
                  [006600]  2638  ; on how we got here and who we are going back to.
                  [006600]  2639  
                  [006600]  2640  .if ne srm_console
                  [006600]  2641  
                  [006600]  2642  ;
                  [006600]  2643  ; The following code assumes we have an srm_console, and we are heading
                  [006600]  2644  ; back to the vms palcode.
                  [006600]  2645  ;
                  [006600]  2646  
                  [006600]  2647  ;
                  [006600]  2648  ; Build PS (IPL=31,CM=kernel,VMM=0,SW=0), and mark 1-1 mode for console.
                  [006600]  2649  ; Note we use OSF_P_MISC values where they match P_MISC values.
                  [006600]  2650  ;
                  [006600]  2651  	lda	r3, ^x1f00(r31)				; ipl=^x1f, cm=0
                  [006600]  2652  	bis	r3, r31, p_misc				; keep in shadow
                  [006600]  2653  	bis	r31, #8, r1				; mces<dpc> = 1
                  [006600]  2654  	sll	r1, #OSF_P_MISC__MCES__MCHK__S, r1	; move into position
                  [006600]  2655  	bis	p_misc, r1, p_misc			; or new mces in
                  [006600]  2656  	lda	p4, 1(r31)				; get a 1
                  [006600]  2657  	sll	p4, #OSF_P_MISC__PHYS__S, p4		; shift into place
                  [006600]  2658  	bis	p_misc, p4, p_misc			; indicate 1-1 mapping
                  [006600]  2659  ;
                  [006600]  2660  ; 1.41 Write EV6__IER to the platform dependent IPL31
                  [006600]  2661  ;
                  [006600]  2662  	bis     r31, #^x1f, r1			; IPL = 31
                  [006600]  2663  	hw_mfpr p4, EV6__PAL_BASE		; (4,0L) get pal base
                  [006600]  2664  	s8addq  r1, p4, p4			; pal base + index
                  [006600]  2665  	lda     p4, ipl_offset(p4)		; pal base + table base + index
                  [006600]  2666  	hw_ldq/p p4, (p4)			; get new ier
                  [006600]  2667  	hw_mtpr p4, EV6__IER			; (4,0L) write new ier
                  [006600]  2668  ;
                  [006600]  2669  ; Be neat, and set PCBB back to a nice kludge spot.
                  [006600]  2670  ; Set PAL_BASE back to the vms palcode.
                  [006600]  2671  ; Questions:
                  [006600]  2672  ;	The VMS palcode base constant is used directly. Is this a
                  [006600]  2673  ;		problem on multiprocessor systems?
                  [006600]  2674  ;	What about super page enable bits? Do we need to clear them?
                  [006600]  2675  ;
                  [006600]  2676  	br	r1, sys__enter_console_get_pal_base
                  [006600]  2677  sys__enter_console_get_pal_base:
                  [006600]  2678  	GET_32ADDR r1, <trap__pal_base - sys__enter_console_get_pal_base>, r1
                  [006600]  2679  	GET_16ADDR r1, <INITIAL_PCBB - trap__pal_base>, r1
                  [006600]  2680  	hw_stq/p r1, PT__PCBB(p_temp)			; write pcbb
                  [006600]  2681  
                  [006600]  2682  	GET_32ADDR r0, <PAL__PAL_BASE>, r31
                  [006600]  2683  	hw_mtpr	r0, EV6__PAL_BASE			; (4,0L) write pal base
                  [006600]  2684  ;
                  [006600]  2685  ; Finish all IPR writes.
                  [006600]  2686  ;
                  [006600]  2687  	bis	r31, r31, r31				; 1.41
                  [006600]  2688  	bis	r31, r31, r31				; 1.41
                  [006600]  2689  	bis	r31, r31, r31				; 1.41
                  [006600]  2690  	hw_mtpr	r31, <EV6__MM_STAT ! ^xF0>		; finish everything
                  [006600]  2691  	bis	r31, r31, r31				; 1.41
                  [006600]  2692  	bis	r31, r31, r31				; 1.41
                  [006600]  2693  	bis	r31, r31, r31				; 1.41
                  [006600]  2694  
                  [006600]  2695  ;
                  [006600]  2696  ; Use an implementation dependent way to get address of console base.
                  [006600]  2697  ; Also, depending on the console, we may need to write r30, the stack pointer!
                  [006600]  2698  ;
                  [006600]  2699  	GET_32CONS 	p23, <PAL__CONSOLE_BASE>, r31	; hw_jmp_stall address
                  [006600]  2700  	NOP						; separate ipr writes
                  [006600]  2701  	bsr	r31, .					; push prediction stack
                  [006600]  2702  	hw_mtpr	r31, EV6__IC_FLUSH			; (4,0L) flush icache
                  [006600]  2703  	bne	r31, .					; pvc #24
                  [006600]  2704  	PVC_VIOLATE <1007>
                  [006600]  2705  	hw_ret_stall (p23)				; pop prediction stack
                  [006600]  2706  							; go off to console
                  [006600]  2707  
                  [006600]  2708  .endc							; if ne srm_console
                  [006600]  2709  
                  [006600]  2710  .if eq srm_console
                  [006600]  2711  
                  [006600]  2712  ;
                  [006600]  2713  ; The following code assumes we have some other kind of console
                  [006600]  2714  ; that continues to use the osf palcode.
                  [006600]  2715  ;
                  [006600]  2716  
                  [006600]  2717  ;
                  [006600]  2718  ; Build PS (IPL=7,CM=kernel), and mark 1-1 mode for console.
                  [006600]  2719  ;
                  [006600]  2720  	bis	r31, #7, p_misc				; ipl=7, cm=0	
                  [006600]  2721  	bis	r31, #8, r1				; mces<dpc> = 1
                  [006600]  2722  	sll	r1, #OSF_P_MISC__MCES__MCHK__S, r1	; move into position
                  [006600]  2723  	bis	p_misc, r1, p_misc			; or new mces in
                  [006600]  2724  	lda	p4, 1(r31)				; get a 1
                  [006600]  2725  	sll	p4, #OSF_P_MISC__PHYS__S, p4		; shift into place
                  [006600]  2726  	bis	p_misc, p4, p_misc			; indicate 1-1 mapping
                  [006600]  2727  ;
                  [006600]  2728  ; Be neat, and set PCBB back to a nice kludge spot.
                  [006600]  2729  ;
                  [006600]  2730  	br	r1, sys__enter_console_get_pal_base
                  [006600]  2731  sys__enter_console_get_pal_base:
                  [006600]  2732  	GET_32ADDR r1, <trap__pal_base - sys__enter_console_get_pal_base>, r1
                  [006600]  2733  	GET_16ADDR r1, <INITIAL_PCBB - trap__pal_base>, r1
                  [006600]  2734  	hw_stq/p r1, PT__PCBB(p_temp)			; write pcbb
                  [006600]  2735  ;
                  [006600]  2736  ; The debug monitor likes the halt code in r1.
                  [006600]  2737  ;
                  [006600]  2738  	bis	p20, r31, r1				; halt code
                  [006600]  2739  ;
                  [006600]  2740  ; Use an implementation dependent way to get address of console base.
                  [006600]  2741  ; Also, depending on the console, we may need to write r30, the stack pointer!
                  [006600]  2742  ;
                  [006600]  2743  	GET_32CONS 	p23, <PAL__CONSOLE_BASE>, r31	; hw_jmp_stall address
                  [006600]  2744  	bsr	r31, .					; push prediction stack
                  [006600]  2745  	hw_mtpr	r31, EV6__IC_FLUSH			; (4,0L) flush icache
                  [006600]  2746  	bne	r31, .					; pvc #24
                  [006600]  2747  	PVC_VIOLATE <1007>
                  [006600]  2748  	hw_ret_stall (p23)				; pop prediction stack
                  [006600]  2749  							; go off to console
                  [006600]  2750  
                  [006600]  2751  .endc							; if eq srm_console
                  [006600]  2711I 
                  [006600]  2712I ;
                  [006600]  2713I ; The following code assumes we have some other kind of console
                  [006600]  2714I ; that continues to use the osf palcode.
                  [006600]  2715I ;
                  [006600]  2716I 
                  [006600]  2717I ;
                  [006600]  2718I ; Build PS (IPL=7,CM=kernel), and mark 1-1 mode for console.
                  [006600]  2719I ;
         47E0F416 [006600]  2720I 	bis	r31, #7, p_misc				; ipl=7, cm=0	
         47E11401 [006604]  2721I 	bis	r31, #8, r1				; mces<dpc> = 1
         48221721 [006608]  2722I 	sll	r1, #OSF_P_MISC__MCES__MCHK__S, r1	; move into position
         46C10416 [00660C]  2723I 	bis	p_misc, r1, p_misc			; or new mces in
         209F0001 [006610]  2724I 	lda	p4, 1(r31)				; get a 1
         4887F724 [006614]  2725I 	sll	p4, #OSF_P_MISC__PHYS__S, p4		; shift into place
         46C40416 [006618]  2726I 	bis	p_misc, p4, p_misc			; indicate 1-1 mapping
                  [00661C]  2727I ;
                  [00661C]  2728I ; Be neat, and set PCBB back to a nice kludge spot.
                  [00661C]  2729I ;
         C0200000 [00661C]  2730I 	br	r1, sys__enter_console_get_pal_base
                  [006620]  2731I sys__enter_console_get_pal_base:
                  [006620]  2732I 	GET_32ADDR r1, <trap__pal_base - sys__enter_console_get_pal_base>, r1
File: ev6_pal_macros.mar
                  [006620]   220i 	ASSUME <trap__pal_base - sys__enter_console_get_pal_base> le  <^x7FFFFFFF>
         24210000 [006620]   221i 	ldah	r1,<<trap__pal_base - sys__enter_console_get_pal_base>+32768>@-16(r1); + xxx<31:16>
         202199E0 [006624]   222i 	lda	r1,<<trap__pal_base - sys__enter_console_get_pal_base> & ^xFFFF>(r1) ; r1+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [006628]  2733I 	GET_16ADDR r1, <INITIAL_PCBB - trap__pal_base>, r1
File: ev6_pal_macros.mar
                  [006628]   230i 	ASSUME <<INITIAL_PCBB - trap__pal_base>> le  <^x7FFF>
         20210C00 [006628]   231i 	lda	r1,<INITIAL_PCBB - trap__pal_base>(r1) ; r1+xxx<15:0>
File: ev6_osf_system_pal.mar
         7C351010 [00662C]  2734I 	hw_stq/p r1, PT__PCBB(p_temp)			; write pcbb
                  [006630]  2735I ;
                  [006630]  2736I ; The debug monitor likes the halt code in r1.
                  [006630]  2737I ;
         469F0401 [006630]  2738I 	bis	p20, r31, r1				; halt code
                  [006634]  2739I ;
                  [006634]  2740I ; Use an implementation dependent way to get address of console base.
                  [006634]  2741I ; Also, depending on the console, we may need to write r30, the stack pointer!
                  [006634]  2742I ;
                  [006634]  2743I 	GET_32CONS 	p23, <PAL__CONSOLE_BASE>, r31	; hw_jmp_stall address
File: ev6_pal_macros.mar
                  [006634]   239i  ASSUME <PAL__CONSOLE_BASE> le  <^x7FFFFFFF>
         26FF0001 [006634]   240i 	ldah	p23,<<PAL__CONSOLE_BASE>+32768>@-16(r31); + xxx<31:16>
         22F70000 [006638]   241i 	lda	p23,<<PAL__CONSOLE_BASE> & ^XFFFF>(p23) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         D3E00000 [00663C]  2744I 	bsr	r31, .					; push prediction stack
         77FF1310 [006640]  2745I 	hw_mtpr	r31, EV6__IC_FLUSH			; (4,0L) flush icache
         F7E00000 [006644]  2746I 	bne	r31, .					; pvc #24
                  [006648]  2747I 	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [006648]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         7BF7A000 [006648]  2748I 	hw_ret_stall (p23)				; pop prediction stack
                  [00664C]  2749I 							; go off to console
                  [00664C]  2750I 
                  [00664C]  2752  
                  [00664C]  2753  
                  [00664C]  2754  ;+
                  [00664C]  2755  ; sys__exit_console
                  [00664C]  2756  ;
                  [00664C]  2757  ;	restore_state (will put return address in p23)
                  [00664C]  2758  ;	clear lock and interrupt flags
                  [00664C]  2759  ;	turn off 1-1 mapping
                  [00664C]  2760  ;	flush TBs
                  [00664C]  2761  ;-
                  [00664C]  2762  	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [00664C]   275i 	.align 6
00000000 00000000 [006654]
00000000 00000000 [00665C]
00000000 00000000 [006664]
00000000 00000000 [00666C]
00000000 00000000 [006674]
         00000000 [00667C]
File: ev6_osf_system_pal.mar
                  [006680]  2763  sys__exit_console:
                  [006680]  2764  	PVC_JSR restore_state, bsr=1
File: ev6_pal_macros.mar
                  [006680]   531i  pvc_lbl \pcv_index, \pcv_jsr_restore_state0, osf
File: ev6_osf_system_pal.mar
         D0FFF92A [006680]  2765  	bsr	p7, pal__restore_state		; restore state
         77FF0310 [006684]  2766  	hw_mtpr	r31, EV6__ITB_IA		; (4,0L) flush itb
         77FFA380 [006688]  2767  	hw_mtpr	r31, EV6__DTB_IA		; (7,1L) flush dtb
         47FF041F [00668C]  2768  	bis	r31, r31, r31
                  [006690]  2769  ;
                  [006690]  2770  ; Clear the lock and interrupt flags. The load should issue only after
                  [006690]  2771  ; the scoreboard bits clear.
                  [006690]  2772  ;
                  [006690]  2773  	ASSUME_FETCH_BLOCK
         77FF27F0 [006690]  2774  	hw_mtpr	r31, <EV6__MM_STAT ! ^xF0>	; (4-7,0L) wait for retire
         63FFE000 [006694]  2775  	rc	r31				; clear int flag
         47FF041F [006698]  2776  	bis	r31, r31, r31
         47FF041F [00669C]  2777  	bis	r31, r31, r31
                  [0066A0]  2778  
         669F1010 [0066A0]  2779  	hw_mfpr	p20, EV6__PAL_BASE		; (4,0L) get pal base
         4A827725 [0066A4]  2780  	sll	p20, #<32-13>, p5		; shift into position
         209F3301 [0066A8]  2781  	lda	p4, ^x3301(r31)			; set WE, RE
         44A40405 [0066AC]  2782  	or	p5, p4, p5			; produce pte
                  [0066B0]  2783  
                  [0066B0]  2784  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
                  [0066B0]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_system_pal.mar
                  [0066B0]  2785  
                  [0066B0]  2786  	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [0066B0]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77F42044 [0066B0]  2787  	hw_mtpr	p20, EV6__DTB_TAG0		; (2&6,0L) write tag0
         77F4A022 [0066B4]  2788  	hw_mtpr p20, EV6__DTB_TAG1		; (1&5,1L) write tag1
         77E52155 [0066B8]  2789  	hw_mtpr	p5, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
         77E5A1AA [0066BC]  2790  	hw_mtpr	p5, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [0066C0]  2791  ;
                  [0066C0]  2792  ; Turn off 1-to-1 mapping
                  [0066C0]  2793  ;
         209F0001 [0066C0]  2794  	lda	p4, 1(r31)			; get a 1
         4887F724 [0066C4]  2795  	sll	p4, #OSF_P_MISC__PHYS__S, p4	; shift into physical position
         46C40116 [0066C8]  2796  	bic	p_misc, p4, p_misc		; clear 1-1 mapping
                  [0066CC]  2797  ;
                  [0066CC]  2798  ; The load will be held up until all these instructions issue.
                  [0066CC]  2799  ; Do the unlock
                  [0066CC]  2800  ;
         A7F40010 [0066CC]  2801  	ldq	r31, <trap__lock_cell - trap__pal_base>(p20)
                  [0066D0]  2802  ;
                  [0066D0]  2803  ; Clear the DTB again. The stall at the end will synch us.
                  [0066D0]  2804  ;
         77FFA380 [0066D0]  2805  	hw_mtpr	r31, EV6__DTB_IA		; (7,0L)
                  [0066D4]  2806  ;
                  [0066D4]  2807  ; Back to user
                  [0066D4]  2808  ;
         D3E00000 [0066D4]  2809  	bsr	r31, .				; push prediction stack
         77FF1310 [0066D8]  2810  	hw_mtpr	r31, EV6__IC_FLUSH		; (4,0L) flush icache
         F7E00000 [0066DC]  2811  	bne	r31, .				; pvc #24
                  [0066E0]  2812  	PVC_VIOLATE <1007>
File: ev6_pal_macros.mar
                  [0066E0]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         7BF7A000 [0066E0]  2813  	hw_ret_stall (p23)			; pop prediction stack
                  [0066E4]  2814  						; go off to user
                  [0066E4]  2815  
                  [0066E4]  2816  
                  [0066E4]  2817  .if eq srm_console
                  [0066E4]  2818  
                  [0066E4]  2819  ;+
                  [0066E4]  2820  ; System Reset code for non-srm systems.
                  [0066E4]  2821  ;
                  [0066E4]  2822  ; This code starts off as implementation dependent, because it must rely
                  [0066E4]  2823  ; on a signature to determine whether it came from the SROM. If it came
                  [0066E4]  2824  ; from the SROM, it does the normal initialization. If it didn't come from
                  [0066E4]  2825  ; the SROM, it needs to differentiate between a swap and a jump through 0.
                  [0066E4]  2826  ;
                  [0066E4]  2827  ; Check for signature. R19<31:16> contains the signature 0xDEC<letter>,
                  [0066E4]  2828  ; So just check <31:20> for 0xDEC.
                  [0066E4]  2829  ;
                  [0066E4]  2830  ; Assume also the absence of the signature says that we ABSOLUTELY
                  [0066E4]  2831  ;	did not come from a power up. Then I can check p_misc for
                  [0066E4]  2832  ;	a swap request.
                  [0066E4]  2833  ;
                  [0066E4]  2834  ; Entry:
                  [0066E4]  2835  ;	r1		dc_ctl
                  [0066E4]  2836  ;
                  [0066E4]  2837  ;	r15		srom_rev
                  [0066E4]  2838  ;	r16		proc_id
                  [0066E4]  2839  ;	r17		mem_size
                  [0066E4]  2840  ;	r18		cycle_cnt
                  [0066E4]  2841  ;	r19		signature in <31:16>
                  [0066E4]  2842  ;	r20		proc_mask (note: we are stepping on shadow!)
                  [0066E4]  2843  ;	r21		sysctx (note: we are stepping on p_temp shadow!)
                  [0066E4]  2844  ;
                  [0066E4]  2845  ;	r26		pc+4 of pal base
                  [0066E4]  2846  ;-
                  [0066E4]  2847  	ALIGN_CACHE_BLOCK
                  [0066E4]  2848  
                  [0066E4]  2849  sys__reset:
                  [0066E4]  2850  	zapnot	r19, #^xC, r4			; clear all but <31:16>
                  [0066E4]  2851  	srl	r4, #20, r4			; get signature <31:20>
                  [0066E4]  2852  	GET_32CONS r5, <^xDEC>, r31		; load validation pattern
                  [0066E4]  2853  	cmpeq	r4, r5, r6			; valid pattern?
                  [0066E4]  2854  
                  [0066E4]  2855  	beq	r6, sys__reset_check_switch	; either swap or jump through 0
                  [0066E4]  2856  
                  [0066E4]  2857  	bis	r1, r31, r27			; save off dc_ctl value
                  [0066E4]  2858  	bis	r20, r31, r28			; save off proc_mask
                  [0066E4]  2859  	bis	r21, r31, r29			; save off sysctx
                  [0066E4]  2860  
                  [0066E4]  2861  	br	r31, sys__reset_init
                  [0066E4]  2862  ;
                  [0066E4]  2863  ; Init and w1c values
                  [0066E4]  2864  ;
                  [0066E4]  2865  	EV6__DC_STAT__W1C = -
                  [0066E4]  2866  		<<1@EV6__DC_STAT__TPERR_P0__S> ! -
                  [0066E4]  2867  		<1@EV6__DC_STAT__TPERR_P1__S> ! -
                  [0066E4]  2868  		<1@EV6__DC_STAT__ECC_ERR_ST__S> ! -
                  [0066E4]  2869  		<1@EV6__DC_STAT__ECC_ERR_LD__S> ! -
                  [0066E4]  2870  		<1@EV6__DC_STAT__SEO__S>>
                  [0066E4]  2871  
                  [0066E4]  2872  ;
                  [0066E4]  2873  ; The ev6_p2 definition will still work for ev6_p3. Bit ^x1e becomes
                  [0066E4]  2874  ; a RO bit for the new performance counter implementation.
                  [0066E4]  2875  ;
                  [0066E4]  2876  .if ne ev6_p3
                  [0066E4]  2877  	EV6__I_STAT__PAR__S = ^x1d
                  [0066E4]  2878  	EV6__I_STAT__W1C = -
                  [0066E4]  2879  		<<1@EV6__I_STAT__PAR__S>>
                  [0066E4]  2880  .iff
                  [0066E4]  2881  	EV6__I_STAT__TPE__S = ^x1d
                  [0066E4]  2882  	EV6__I_STAT__DPE__S = ^x1e
                  [0066E4]  2883  	EV6__I_STAT__W1C = -
                  [0066E4]  2884  		<<1@EV6__I_STAT__TPE__S> ! -
                  [0066E4]  2885  		<1@EV6__I_STAT__DPE__S>>
                  [0066E4]  2886  .endc
                  [0066E4]  2887  
                  [0066E4]  2888  ;
                  [0066E4]  2889  ; On the reference platform, we get DC_CTL from the srom. These
                  [0066E4]  2890  ; init values are left for the convenience of other system partners.
                  [0066E4]  2891  ;
                  [0066E4]  2892    .if eq reference_platform
                  [0066E4]  2893      .if ne ev6_p1
                  [0066E4]  2894  	EV6__DC_CTL__INIT = -
                  [0066E4]  2895  		<<dcache_set_en@EV6__DC_CTL__SET_EN__S> ! -
                  [0066E4]  2896  		 <0@EV6__DC_CTL__DCTAG_PAR_EN__S> ! -
                  [0066E4]  2897  		 <0@EV6__DC_CTL__DCDAT_ERR_EN__S>>
                  [0066E4]  2898      .iff
                  [0066E4]  2899  	EV6__DC_CTL__INIT = -
                  [0066E4]  2900  		<<dcache_set_en@EV6__DC_CTL__SET_EN__S> ! -
                  [0066E4]  2901  		 <1@EV6__DC_CTL__DCTAG_PAR_EN__S> ! -
                  [0066E4]  2902  		 <1@EV6__DC_CTL__DCDAT_ERR_EN__S>>
                  [0066E4]  2903      .endc
                  [0066E4]  2904    .endc
                  [0066E4]  2905  
                  [0066E4]  2906  	EV6__IER__INIT = 0
                  [0066E4]  2907  
                  [0066E4]  2908  	EV6__PCTX__INIT = -
                  [0066E4]  2909  		<1@EV6__PROCESS_CONTEXT__FPE__S>
                  [0066E4]  2910  
                  [0066E4]  2911  	ASSUME EV6__HW_INT_CLR__MCHK_D__S lt EV6__HW_INT_CLR__PC__S 
                  [0066E4]  2912  	ASSUME EV6__HW_INT_CLR__MCHK_D__S lt EV6__HW_INT_CLR__CR__S 
                  [0066E4]  2913  	ASSUME EV6__HW_INT_CLR__MCHK_D__S lt EV6__HW_INT_CLR__SL__S 
                  [0066E4]  2914  
                  [0066E4]  2915  	EV6__HW_INT_CLR__INIT = -
                  [0066E4]  2916  	    <<1@<EV6__HW_INT_CLR__MCHK_D__S - EV6__HW_INT_CLR__MCHK_D__S>> ! -
                  [0066E4]  2917  	     <3@<EV6__HW_INT_CLR__PC__S - EV6__HW_INT_CLR__MCHK_D__S>> ! -
                  [0066E4]  2918  	     <1@<EV6__HW_INT_CLR__CR__S - EV6__HW_INT_CLR__MCHK_D__S>> ! -
                  [0066E4]  2919  	     <1@<EV6__HW_INT_CLR__SL__S - EV6__HW_INT_CLR__MCHK_D__S>>>
                  [0066E4]  2920  
                  [0066E4]  2921  	EV6__VA_CTL__INIT = <va_48@EV6__VA_CTL__VA_48__S>
                  [0066E4]  2922  
                  [0066E4]  2923  .if ne kseg_hack				; kseg hack
                  [0066E4]  2924  	EV6__M_CTL__INIT = 0
                  [0066E4]  2925  .iff
                  [0066E4]  2926  	EV6__M_CTL__INIT = <2@<EV6__M_CTL__SPE__S+va_48>>
                  [0066E4]  2927  .endc
                  [0066E4]  2928  
                  [0066E4]  2929  	EV6__I_CTL__INIT = -
                  [0066E4]  2930  		<<3@EV6__I_CTL__IC_EN__S> ! -
                  [0066E4]  2931  		<2@<EV6__I_CTL__SPE__S+va_48>> ! -
                  [0066E4]  2932  		<2@EV6__I_CTL__SDE__S> ! -
                  [0066E4]  2933  		<3@EV6__I_CTL__SBE__S> ! -
                  [0066E4]  2934  		<va_48@EV6__I_CTL__VA_48__S> ! -
                  [0066E4]  2935  		<1@EV6__I_CTL__CALL_PAL_R23__S> ! -
                  [0066E4]  2936  		<mchk_en@EV6__I_CTL__MCHK_EN__S> ! -
                  [0066E4]  2937  		<tb_mb_en@EV6__I_CTL__TB_MB_EN__S>>
                  [0066E4]  2938  
                  [0066E4]  2939  ;
                  [0066E4]  2940  ; Do the initialization. We rely on fetch blocks to separate scoreboard bits!!!
                  [0066E4]  2941  ;
                  [0066E4]  2942  ; Input:
                  [0066E4]  2943  ;	r26	pc+4 of pal base
                  [0066E4]  2944  ;
                  [0066E4]  2945  	ALIGN_FETCH_BLOCK <^x47FF041F>			; pad with NOPs
                  [0066E4]  2946  
                  [0066E4]  2947  	ASSUME_FETCH_BLOCK
                  [0066E4]  2948  	
                  [0066E4]  2949  sys__reset_init:
                  [0066E4]  2950  	hw_mtpr	r31, EV6__ITB_IA			; (4,0L) flush ITB
                  [0066E4]  2951  	hw_mtpr	r31, EV6__DTB_IA			; (7,0L) flush DTB
                  [0066E4]  2952  	srl	r26, #EV6__PAL_BASE__PAL_BASE__S, r1	; clean pal base
                  [0066E4]  2953  	sll	r1, #EV6__PAL_BASE__PAL_BASE__S, r1	; get into position
                  [0066E4]  2954  
                  [0066E4]  2955  	hw_mtpr	r1, EV6__PAL_BASE			; (4,0L) write pal base
                  [0066E4]  2956  	GET_32CONS 	r1, EV6__I_STAT__W1C, r31	; get i_stat clr value
                  [0066E4]  2957  	GET_16CONS	r3, EV6__DC_STAT__W1C, r31	; get dc_stat clr value
                  [0066E4]  2958  
                  [0066E4]  2959  	hw_mtpr	r1, EV6__I_STAT				; (4,0L) w1c I_STAT
                  [0066E4]  2960  	hw_mtpr r3, EV6__DC_STAT			; (6,0L) w1c DC_STAT
                  [0066E4]  2961  	GET_32CONS 	r1, EV6__I_CTL__INIT, r31	; get i_ctl init value
                  [0066E4]  2962  
                  [0066E4]  2963  	hw_mtpr	r1, EV6__I_CTL				; (4,0L) init I_CTL
                  [0066E4]  2964  	rc	r31					; clear intr_flag
                  [0066E4]  2965  	bis	r31, r31, r31				; fetch block
                  [0066E4]  2966  	bis	r31, r31, r31				; fetch block
                  [0066E4]  2967  
                  [0066E4]  2968  	GET_16CONS 	r1, EV6__PCTX__INIT , r31	; get pctx init value
                  [0066E4]  2969  	GET_16CONS	r3, EV6__M_CTL__INIT, r31	; get m_ctl init value
                  [0066E4]  2970  	hw_mtpr	r1, EV6__PROCESS_CONTEXT		; (4,0L) write pctx
                  [0066E4]  2971  	hw_mtpr r3, EV6__M_CTL				; (6,0L) write M_CTL
                  [0066E4]  2972  
                  [0066E4]  2973  	GET_32CONS	r1, EV6__IER__INIT, r31 	; get ier_cm init value
                  [0066E4]  2974  	hw_mtpr	r1, EV6__IER_CM				; (4,0L) clear int en
                  [0066E4]  2975  	hw_mtpr r31, EV6__CC				; (5,1L) clear offset
                  [0066E4]  2976  
                  [0066E4]  2977  	bis	r31, #1, r1				; get a 1
                  [0066E4]  2978  	sll	r1, #32, r1				; get into position
                  [0066E4]  2979  	hw_mtpr	r31, EV6__SIRR				; (4,0L) clear int req
                  [0066E4]  2980  	hw_mtpr r1, EV6__CC_CTL				; (5,1L) clr/ena ctr
                  [0066E4]  2981  
                  [0066E4]  2982  	GET_16CONS	r1, EV6__HW_INT_CLR__INIT, r31	; get w1c mask
                  [0066E4]  2983  	sll	r1, #EV6__HW_INT_CLR__MCHK_D__S, r1	; move into position
                  [0066E4]  2984  	PVC_VIOLATE <35>
                  [0066E4]  2985  	hw_mtpr	r1, EV6__HW_INT_CLR			; (4,0L)
                  [0066E4]  2986  	hw_mtpr	r31, EV6__DTB_ALT_MODE			; (6,0L) clear alt_mode
                  [0066E4]  2987  
                  [0066E4]  2988  	hw_mtpr	r31, EV6__PCTR_CTL			; (4,0L) clear pctr
                  [0066E4]  2989  	GET_16CONS	r1, EV6__VA_CTL__INIT, r31	; get va_ctl value
                  [0066E4]  2990  	hw_mtpr	r1, EV6__VA_CTL				; (5,1L) init va_ctl
                  [0066E4]  2991  	NOP						; pad fetch block
                  [0066E4]  2992  ;
                  [0066E4]  2993  ; In normal operation, there must be a scoreboard bit -> register dependency
                  [0066E4]  2994  ; chain to prevent hw_mtpr DTB_ASx from issuing while ANY of scoreboard
                  [0066E4]  2995  ; bits <7:4> are set. Since we know there are no dstream operations going on,
                  [0066E4]  2996  ; we really don't need that here.
                  [0066E4]  2997  ;
                  [0066E4]  2998  	PVC_VIOLATE <21>
                  [0066E4]  2999  	hw_mtpr r31, EV6__DTB_ASN0			; (4,0L)
                  [0066E4]  3000  	hw_mtpr r31, EV6__DTB_ASN1			; (7,1L)
                  [0066E4]  3001  	NOP						; pad fetch block
                  [0066E4]  3002  	NOP						; pad fetch block
                  [0066E4]  3003  ;
                  [0066E4]  3004  ; We need to write pctr_ctl again to clear the 2nd stage overflow flag.
                  [0066E4]  3005  ; And force other mtpr to retire while we are at it.
                  [0066E4]  3006  ;
                  [0066E4]  3007  	hw_mtpr	r31, <EV6__PCTR_CTL ! ^xF0>		; (4,0L) clr ovr flag
                  [0066E4]  3008  	NOP						; pad fetch block
                  [0066E4]  3009  	NOP
                  [0066E4]  3010  	NOP
                  [0066E4]  3011  ;
                  [0066E4]  3012  ; We need to write HW_INT_CLR to avoid a interrupt that can occur when
                  [0066E4]  3013  ; the counters come up in an unpredictable state near overflow.
                  [0066E4]  3014  ;
                  [0066E4]  3015  	lda	p7, 3(r31)			; 1.41 get a 3
                  [0066E4]  3016  	sll	p7, #EV6__HW_INT_CLR__PC__S, p7	; 1.41 move into position
                  [0066E4]  3017  	hw_mtpr	p7, EV6__HW_INT_CLR		; 1.41(4,0L) ack the int
                  [0066E4]  3018  	bis	r31, r31, r31			; 1.41
                  [0066E4]  3019  	bis	r31, r31, r31			; 1.41
                  [0066E4]  3020  	bis	r31, r31, r31			; 1.41
                  [0066E4]  3021  	PVC_VIOLATE <35>
                  [0066E4]  3022  	hw_mtpr	p7, EV6__HW_INT_CLR		; 1.41 (4,0L) ack the int
                  [0066E4]  3023  
                  [0066E4]  3024  ;
                  [0066E4]  3025  ; FPCR is unpredictable, possibly set by the srom. Should we do anything here?
                  [0066E4]  3026  ;
                  [0066E4]  3027    .if ne 0
                  [0066E4]  3028  	mt_fpcr	f31					; clear the fpcr
                  [0066E4]  3029    .endc							; (in separate block)
                  [0066E4]  3030  
                  [0066E4]  3031  ;
                  [0066E4]  3032  ; 1.41 move cbox error read down below the virtual (clear lock) operation.
                  [0066E4]  3033  ;
                  [0066E4]  3034  
                  [0066E4]  3035  ; Hardcode the whami for behavorial and
                  [0066E4]  3036  ; for not behavorial but not reference_platform.
                  [0066E4]  3037  ; the system.
                  [0066E4]  3038  ;
                  [0066E4]  3039  
                  [0066E4]  3040    .if ne beh_model
                  [0066E4]  3041  PAL__WHAMI = 0
                  [0066E4]  3042  	GET_16CONS	r0, PAL__WHAMI, r31		; set whami
                  [0066E4]  3043    .iff
                  [0066E4]  3044      .if eq reference_platform
                  [0066E4]  3045  	GET_16CONS	r0, PAL__WHAMI, r31		; set whami
                  [0066E4]  3046      .iff
                  [0066E4]  3047  ;
                  [0066E4]  3048  ; Read the MISC<CPUID> bit for this cpu.
                  [0066E4]  3049  ; The MISC CSR is at 801.A000.0080.
                  [0066E4]  3050  ; This defines the value for PT__WHAMI.
                  [0066E4]  3051  ;
                  [0066E4]  3052  	lda	p4, ^x801A(r31)			; generate 801.A000.0000
                  [0066E4]  3053  	zap	p4, #^xFC, p4			; zap extension
                  [0066E4]  3054  	sll	p4, #28, p4			; move into place
                  [0066E4]  3055  	hw_ldq/p r0, ^x80(p4)			; Read CPUID from 801.A000.0080
                  [0066E4]  3056  	and	r0, #^xF, r0			; Zap other bits.
                  [0066E4]  3057      .endc					; if eq reference_platform
                  [0066E4]  3058    .endc						; if ne beh_model
                  [0066E4]  3059  
                  [0066E4]  3060  ;
                  [0066E4]  3061  ; Initialize p_temp to base of specific pal temp area.
                  [0066E4]  3062  ; Store whami in pal temp area.
                  [0066E4]  3063  ; Compute base of specific impure area and store in pal temp area.
                  [0066E4]  3064  ;
                  [0066E4]  3065  	GET_32CONS	p_temp, PAL__TEMPS_BASE, r31		; pal_temps base
                  [0066E4]  3066  	GET_32CONS	r1, PAL__TEMPS_SPECIFIC_SIZE, r31	; specific size
                  [0066E4]  3067  	mulq	r0, r1, r1					; whami * size
                  [0066E4]  3068  	addq	p_temp, r1, p_temp				; cpu base
                  [0066E4]  3069  
                  [0066E4]  3070  	GET_32CONS	r2, <PAL__IMPURE_BASE>, r31	    ; impure area base
                  [0066E4]  3071  	GET_16CONS	r1, <PAL__IMPURE_SPECIFIC_SIZE>, r31; specific size
                  [0066E4]  3072  	GET_16CONS	r3, <PAL__IMPURE_COMMON_SIZE>, r31  ; common size
                  [0066E4]  3073  
                  [0066E4]  3074  	mulq	r0, r1, r1			; whami * specific
                  [0066E4]  3075  	addq	r1, r3, r1			; add in common
                  [0066E4]  3076  	addq	r2, r1, r2			; add to impure base
                  [0066E4]  3077  	hw_stq/p r0, PT__WHAMI(p_temp)		; store whami value
                  [0066E4]  3078  	hw_stq/p r2, PT__IMPURE(p_temp)		; store pt_impure base address
                  [0066E4]  3079  ;
                  [0066E4]  3080  ; Now store M_CTL.
                  [0066E4]  3081  ;
                  [0066E4]  3082  	GET_16CONS	r3, EV6__M_CTL__INIT, r31
                  [0066E4]  3083  	hw_stq/p r3, PT__M_CTL(p_temp)		; store m_ctl value
                  [0066E4]  3084  ;
                  [0066E4]  3085  ; For reference platform, store passed up parameters.
                  [0066E4]  3086  ; For non-reference platform, store CNS__DC_CTL from an init value.
                  [0066E4]  3087  ;	NOTE: WE DON'T WRITE DC_CTL!! This is just here so we have
                  [0066E4]  3088  ;	a sane dc_ctl value.
                  [0066E4]  3089  ;
                  [0066E4]  3090  ; Current state for reference platform:
                  [0066E4]  3091  ;	r27	dc_ctl
                  [0066E4]  3092  ;		write_many chain in <51:16>
                  [0066E4]  3093  ;	r28	proc_mask
                  [0066E4]  3094  ;	r29	sysctx
                  [0066E4]  3095  ;
                  [0066E4]  3096    .if ne reference_platform
                  [0066E4]  3097  	srl	r27, #16, r1			; get write-many chain
                  [0066E4]  3098  	hw_stq/p r1, CNS__WRITE_MANY(r2)	; store it
                  [0066E4]  3099  	and	r27, #^xFF, r27			; clean dc_ctl
                  [0066E4]  3100  	hw_stq/p r27, CNS__DC_CTL(r2)		; store dc_ctl value
                  [0066E4]  3101  
                  [0066E4]  3102  	hw_stq/p r15, CNS__SROM_REV(r2)		; encoded srom.s RCS revision
                  [0066E4]  3103  	hw_stq/p r16, CNS__PROC_ID(r2)		; processor identification
                  [0066E4]  3104  						; 	(a la SRM)
                  [0066E4]  3105  	hw_stq/p r17, CNS__MEM_SIZE(r2)		; size of contiguous,
                  [0066E4]  3106  						;	good memory in bytes
                  [0066E4]  3107  	hw_stq/p r18, CNS__CYCLE_CNT(r2)	; cycle count in picoseconds
                  [0066E4]  3108  	hw_stq/p r19, CNS__SIGNATURE(r2)	; signature (0xDECB) in <31:16>
                  [0066E4]  3109  						;	and sys rev ID in <15:0>
                  [0066E4]  3110  	bis	r31, r31, r19			; zap the signature
                  [0066E4]  3111  	hw_stq/p r28, CNS__PROC_MASK(r2)	; active processor mask
                  [0066E4]  3112  	hw_stq/p r29, CNS__SYSCTX(r2)		; system context value
                  [0066E4]  3113    .iff
                  [0066E4]  3114  	GET_16CONS	r27, EV6__DC_CTL__INIT, r31
                  [0066E4]  3115  	hw_stq/p r27, CNS__DC_CTL(r2)		; store dc_ctl value
                  [0066E4]  3116    .endc						; if ne reference_platform
                  [0066E4]  3117  ;
                  [0066E4]  3118  ; For pass1, store CNS__FPE_STATE = 1.
                  [0066E4]  3119  ;
                  [0066E4]  3120    .if ne ev6_p1
                  [0066E4]  3121  	bis	r31, #1, r1			; get a 1
                  [0066E4]  3122  	hw_stq/p r1, CNS__FPE_STATE(r2)		; start with fpe state = 1
                  [0066E4]  3123  	hw_stq/p r31, CNS__R31_EMUL(r2)		; zap r31
                  [0066E4]  3124  	hw_stq/p r31, CNS__F31_EMUL(r2)		; zap f31
                  [0066E4]  3125  	hw_stq/p r31, CNS__FPCR(r2)		; zap fpcr
                  [0066E4]  3126      .if ne fp_count
                  [0066E4]  3127  	hw_stq/p r31, PT__RSV_FOR_PAL(p_temp)	; clear counter
                  [0066E4]  3128      .endc
                  [0066E4]  3129    .endc
                  [0066E4]  3130  
                  [0066E4]  3131  ;
                  [0066E4]  3132  ; Write ps into a shadow register IPL=7,CM=0.
                  [0066E4]  3133  ; Write mces to pal temp area, with dpc set.
                  [0066E4]  3134  ;	
                  [0066E4]  3135  	bis	r31, #7, p_misc				; ipl=7, cm=0
                  [0066E4]  3136  	bis	r31, #8, r1				; mces<dpc> = 1
                  [0066E4]  3137  	sll	r1, #OSF_P_MISC__MCES__MCHK__S, r1	; move into position
                  [0066E4]  3138  	bis	p_misc, r1, p_misc			; or new mces in
                  [0066E4]  3139  
                  [0066E4]  3140  ;
                  [0066E4]  3141  ; Store lower portion in PT__VA_CTL in pal temps area.
                  [0066E4]  3142  ; Store VPTB in PT__VPTB in pal temps area.
                  [0066E4]  3143  ; Store DTB_ALT_MODE in pal temps area.
                  [0066E4]  3144  ;
                  [0066E4]  3145  	GET_16CONS	r1, EV6__VA_CTL__INIT, r31
                  [0066E4]  3146  	hw_stq/p r1, PT__VA_CTL(p_temp)		; store control part
                  [0066E4]  3147  	hw_stq/p r31, PT__VPTB(p_temp)		; store vptb base part
                  [0066E4]  3148  	hw_stq/p r31, PT__DTB_ALT_MODE(p_temp)	; clear alt_mode temp
                  [0066E4]  3149  ;
                  [0066E4]  3150  ; Miscellaneous pal temps
                  [0066E4]  3151  ;
                  [0066E4]  3152  	hw_stq/p r31, PT__SCC(p_temp)		; clear SCC
                  [0066E4]  3153  	hw_stq/p r31, PT__SCBB(p_temp)		; clear scb
                  [0066E4]  3154  	hw_stq/p r31, PT__PTBR(p_temp)		; clear ptbr
                  [0066E4]  3155  ;
                  [0066E4]  3156  ; Set up PT__PCBB to point to kludge PCB.
                  [0066E4]  3157  ;
                  [0066E4]  3158  	hw_mfpr	r1, EV6__PAL_BASE		; (4,0L) get pal base back
                  [0066E4]  3159  	GET_16ADDR 	r2, <INITIAL_PCBB - TRAP__START>, r1
                  [0066E4]  3160  	hw_stq/p r2, PT__PCBB(p_temp)		; write pcbb
                  [0066E4]  3161  ;
                  [0066E4]  3162  ; Now we need to clear the lock flag, which must be done with a LDQ.
                  [0066E4]  3163  ; So we need to set up the DTB, do the write, and re-clear the DTB.
                  [0066E4]  3164  ;
                  [0066E4]  3165  ; Currently r1=pal base That's good enough to use for our translation.
                  [0066E4]  3166  ; Write the dtb, do the reference, clear the dtb and synch up.
                  [0066E4]  3167  ;
                  [0066E4]  3168  
                  [0066E4]  3169  	sll	r1, #<32-13>, r2		; shift into position
                  [0066E4]  3170  	lda	r3, ^x1101(r31)			; set KWE, KRE
                  [0066E4]  3171  	or	r2, r3, r2			; produce pte
                  [0066E4]  3172  
                  [0066E4]  3173  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
                  [0066E4]  3174  
                  [0066E4]  3175  	PVC_VIOLATE <2>				; ignore scoreboard violation
                  [0066E4]  3176  	hw_mtpr	r1, EV6__DTB_TAG0		; (2&6,0L) write tag0
                  [0066E4]  3177  	hw_mtpr r1, EV6__DTB_TAG1		; (1&5,1L) write tag1
                  [0066E4]  3178  	hw_mtpr	r2, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
                  [0066E4]  3179  	hw_mtpr	r2, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [0066E4]  3180  ;
                  [0066E4]  3181  ; Do the unlock. Then clear the dtb.
                  [0066E4]  3182  ;
                  [0066E4]  3183  	ALIGN_FETCH_BLOCK <^x47FF041F>		; align with NOPs
                  [0066E4]  3184  	mb					; pvc restriction 28
                  [0066E4]  3185  	ldq	r31, <trap__lock_cell - trap__pal_base>(r1)
                  [0066E4]  3186  	bis	r31, r31, r31
                  [0066E4]  3187  
                  [0066E4]  3188  	hw_mtpr	r31, EV6__DTB_IA		; (7,0L)
                  [0066E4]  3189  	bis	r31, r31, r31
                  [0066E4]  3190  	bis	r31, r31, r31
                  [0066E4]  3191  	bis	r31, r31, r31
                  [0066E4]  3192  
                  [0066E4]  3193  	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; 1.41 (7,0L) wait for dtb_ia
                  [0066E4]  3194  	bis	r31, r31, r31			; 1.41
                  [0066E4]  3195  	bis	r31, r31, r31			; 1.41
                  [0066E4]  3196  	bis	r31, r31, r31			; 1.41
                  [0066E4]  3197  ;
                  [0066E4]  3198  ; Clear out the cbox error read chain
                  [0066E4]  3199  ; 1.41 Move here from above
                  [0066E4]  3200  ;
                  [0066E4]  3201  ; Register use:
                  [0066E4]  3202  ;	p4-p7	trashed
                  [0066E4]  3203  ;	p20	trashed
                  [0066E4]  3204  ;
                  [0066E4]  3205      .if eq force_path			; 1.41
                  [0066E4]  3206  	PVC_JSR cbox, bsr=1
                  [0066E4]  3207  	bsr	p5, sys__cbox
                  [0066E4]  3208      .iff
                  [0066E4]  3209  	PVC_VIOLATE <1008>		; 1.42 tell pvc to skip routine
                  [0066E4]  3210  	br	p5, sys__cbox
                  [0066E4]  3211      .endc				; 1.41
                  [0066E4]  3212  ;
                  [0066E4]  3213  ; Set up for the console
                  [0066E4]  3214  ;
                  [0066E4]  3215  
                  [0066E4]  3216  ;
                  [0066E4]  3217  ; 1.41 Write EV6__IER to the platform dependent IPL31
                  [0066E4]  3218  ;
                  [0066E4]  3219  	bis     r31, #^x1f, r1			; IPL = 31
                  [0066E4]  3220  	hw_mfpr p4, EV6__PAL_BASE		; (4,0L) get pal base
                  [0066E4]  3221  	s8addq  r1, p4, p4			; pal base + index
                  [0066E4]  3222  	lda     p4, ipl_offset(p4)		; pal base + table base + index
                  [0066E4]  3223  	hw_ldq/p p4, (p4)			; get new ier
                  [0066E4]  3224  	hw_mtpr p4, EV6__IER			; (4,0L) write new ier
                  [0066E4]  3225  	bis	r31, r31, r31
                  [0066E4]  3226  	bis	r31, r31, r31
                  [0066E4]  3227  	bis	r31, r31, r31
                  [0066E4]  3228  	hw_mtpr r31, <EV6__MM_STAT ! ^x10>	; wait for it
                  [0066E4]  3229  
                  [0066E4]  3230  	bis	r31, r31, p20			; halt code in p20
                  [0066E4]  3231  	bis	r31, r31, r31
                  [0066E4]  3232  	bis	r31, r31, r31
                  [0066E4]  3233  	hw_stq/p r31, PT__HALT_CODE(p_temp)	; store halt code
                  [0066E4]  3234  	br	r31, sys__enter_console		; enter console
                  [0066E4]  3235  
                  [0066E4]  3236  
                  [0066E4]  3237  ;+
                  [0066E4]  3238  ; The signature was not valid, so we DID NOT COME FROM THE SROM. So
                  [0066E4]  3239  ; check for swap or jump through zero.
                  [0066E4]  3240  ;-
                  [0066E4]  3241  
                  [0066E4]  3242  sys__reset_check_switch:
                  [0066E4]  3243  	srl	p_misc, #OSF_P_MISC__SWITCH__S, r1	; check the switch bit
                  [0066E4]  3244  	blbc	r1, sys__reset_noswitch			; jumped through 0
                  [0066E4]  3245  ;
                  [0066E4]  3246  ; Looks like a swppal. Do initialization, relying on fetch blocks for
                  [0066E4]  3247  ; scoreboard bit separation.
                  [0066E4]  3248  ;
                  [0066E4]  3249  
                  [0066E4]  3250  	ALIGN_FETCH_BLOCK <^x47FF041F>			; pad with NOPs
                  [0066E4]  3251  
                  [0066E4]  3252  	ASSUME_FETCH_BLOCK
                  [0066E4]  3253  
                  [0066E4]  3254  sys__switch_base:
                  [0066E4]  3255  	br	r1, sys__switch_get_pal_base
                  [0066E4]  3256  sys__switch_get_pal_base:
                  [0066E4]  3257  	GET_32ADDR r1, <trap__pal_base - sys__switch_get_pal_base>, r1
                  [0066E4]  3258  	hw_mtpr	r1, EV6__PAL_BASE			; (4,0L) pal base
                  [0066E4]  3259  
                  [0066E4]  3260  	hw_mtpr	r31, EV6__ITB_IA			; (4,0L)
                  [0066E4]  3261  	hw_mtpr	r31, EV6__DTB_IA			; (7,0L) flush DTB
                  [0066E4]  3262  	GET_32CONS 	r1, EV6__I_STAT__W1C, r31	; get i_stat clr value
                  [0066E4]  3263  
                  [0066E4]  3264  	GET_16CONS	R3, EV6__DC_STAT__W1C, R31	; get dc_stat clr value
                  [0066E4]  3265  	hw_mtpr	r1, EV6__I_STAT				; (4,0L) w1c I_STAT
                  [0066E4]  3266  	hw_mtpr r3, EV6__DC_STAT			; (6,0L) w1c DC_STAT
                  [0066E4]  3267  	rc	r31					; clear intr_flag
                  [0066E4]  3268  
                  [0066E4]  3269  	GET_32CONS	r1, EV6__IER__INIT, r31 
                  [0066E4]  3270  	hw_mtpr	r1, EV6__IER_CM				; (4,0L) clear ier_cm
                  [0066E4]  3271  	hw_mtpr	r31, EV6__DTB_ALT_MODE			; (6,0L) clear alt_mode
                  [0066E4]  3272  
                  [0066E4]  3273  	hw_stq/p r31, PT__DTB_ALT_MODE(p_temp)		; clear alt_mode temp
                  [0066E4]  3274  	zapnot	p_misc, #4, p_misc			; zap all but mces
                  [0066E4]  3275  	bis	p_misc, #7, p_misc			; cm=0,ipl=7
                  [0066E4]  3276  	hw_mtpr	r31, EV6__SIRR				; (4,0L) Clear int req
                  [0066E4]  3277  	
                  [0066E4]  3278  	GET_16CONS	r1, EV6__HW_INT_CLR__INIT, r31
                  [0066E4]  3279  	sll	r1, #EV6__HW_INT_CLR__MCHK_D__S, r1	; move into position
                  [0066E4]  3280  	PVC_VIOLATE <35>
                  [0066E4]  3281  	hw_mtpr	r1, EV6__HW_INT_CLR			; (4,0L) Clear int req
                  [0066E4]  3282  	NOP						; pad fetch block
                  [0066E4]  3283  ;
                  [0066E4]  3284  ; Current state:
                  [0066E4]  3285  ;	r17 (a1)	new PC
                  [0066E4]  3286  ;	r18 (a2)	new PCBB
                  [0066E4]  3287  ;	r19 (a3)	new VPTB
                  [0066E4]  3288  ;
                  [0066E4]  3289  	hw_ldq/p p4, OSF_PCB__FEN(r18)		; get new fen/pme
                  [0066E4]  3290  	hw_ldl/p p5, OSF_PCB__CPC(r18)		; get charged cycle counter
                  [0066E4]  3291  	hw_ldl/p p6, OSF_PCB__ASN(r18)		; get new asn
                  [0066E4]  3292  	hw_ldq/p p7, OSF_PCB__PTBR(r18)		; get new ptbr
                  [0066E4]  3293  
                  [0066E4]  3294  	sll	p7, #page_offset_size_bits, p7	; convert pfn to pa
                  [0066E4]  3295  	hw_stq/p p7, PT__PTBR(p_temp)		; store PTBR
                  [0066E4]  3296  	hw_stq/p r18, PT__PCBB(p_temp)		; store PCBB
                  [0066E4]  3297  	bic	r17, #3, p23			; clean PC to p23
                  [0066E4]  3298  ;
                  [0066E4]  3299  ; Get VPTB and write it to VA_CTL and I_CTL. At the same time, initialize
                  [0066E4]  3300  ; VA_CTL, M_CTL, and I_CTL.
                  [0066E4]  3301  ;
                  [0066E4]  3302  ; Store lower portion in PT__VA_CTL in pal temps area.
                  [0066E4]  3303  ; Store VPTB in PT__VPTB in pal temps area.
                  [0066E4]  3304  ;
                  [0066E4]  3305  ; Initialize M_CTL  a write-only register, and save it away.
                  [0066E4]  3306  ;
                  [0066E4]  3307  ; Initialize I_CTL.
                  [0066E4]  3308  ; Write I_CTL twice (pvc #31).
                  [0066E4]  3309  ;
                  [0066E4]  3310  
                  [0066E4]  3311  	GET_16CONS	r1, EV6__VA_CTL__INIT, r31
                  [0066E4]  3312  	hw_stq/p r1, PT__VA_CTL(p_temp)		; store control part
                  [0066E4]  3313  	hw_stq/p r19, PT__VPTB(p_temp)		; store vptb base part
                  [0066E4]  3314  	bis	r1, r19, r1			; or in vptb part
                  [0066E4]  3315  
                  [0066E4]  3316  	hw_mtpr	r1, EV6__VA_CTL			; (5,1L)
                  [0066E4]  3317  	GET_16CONS	r1, EV6__M_CTL__INIT, r31
                  [0066E4]  3318  	hw_mtpr r1, EV6__M_CTL			; (6,0L)
                  [0066E4]  3319  	hw_stq/p r1, PT__M_CTL(p_temp)		; save it away
                  [0066E4]  3320  
                  [0066E4]  3321  	GET_32CONS 	r1, EV6__I_CTL__INIT, r31
                  [0066E4]  3322  	bis	r1, r19, r1			; or in vptb
                  [0066E4]  3323  
                  [0066E4]  3324  	hw_mtpr	r1, EV6__I_CTL				; (4,0L) write I_CTL
                  [0066E4]  3325  	bis	r31, r31, r31
                  [0066E4]  3326  	bis	r31, r31, r31
                  [0066E4]  3327  	bis	r31, r31, r31
                  [0066E4]  3328  
                  [0066E4]  3329  	hw_mtpr	r1, EV6__I_CTL				; (4,0L) write I_CTL
                  [0066E4]  3330  ;
                  [0066E4]  3331  ; Do USP and KSP
                  [0066E4]  3332  ;
                  [0066E4]  3333  	hw_ldq/p r30, OSF_PCB__USP(r18)		; get new USP
                  [0066E4]  3334  	hw_stq/p r30, PT__USP(p_temp)		; save it away
                  [0066E4]  3335  	hw_ldq/p r30, OSF_PCB__KSP(r18)		; get KSP
                  [0066E4]  3336  ;
                  [0066E4]  3337  ; Now do DTB_ASNx.
                  [0066E4]  3338  ;
                  [0066E4]  3339  ; There must be a scoreboard bit -> register dependency chain to prevent
                  [0066E4]  3340  ; hw_mtpr DTB_ASx from issuing while ANY of scoreboard bits <7:4> are set.
                  [0066E4]  3341  ;
                  [0066E4]  3342  ; Current state:
                  [0066E4]  3343  ;	p6	ASN
                  [0066E4]  3344  ;
                  [0066E4]  3345  ASSUME OSF_PCB__ASN__M eq ^xFF
                  [0066E4]  3346  
                  [0066E4]  3347  	and	p6, #OSF_PCB__ASN__M, p6	; clean ASN quadword
                  [0066E4]  3348  	sll	p6, #EV6__DTB_ASN0__ASN__S, p20	; ASN into mbox spot
                  [0066E4]  3349  
                  [0066E4]  3350  	hw_mfpr	p7, <EV6__PAL_BASE ! ^xF0>	; (4-7, 0L)
                  [0066E4]  3351  	xor	p7, p7, p7			; zap p7
                  [0066E4]  3352  	bis	p7, p20, p20			; force register dependency
                  [0066E4]  3353  	bis	r31, r31, r31
                  [0066E4]  3354  	hw_mtpr	p20, EV6__DTB_ASN0		; (4,0L)
                  [0066E4]  3355  	hw_mtpr	p20, EV6__DTB_ASN1		; (7,1L)
                  [0066E4]  3356  
                  [0066E4]  3357  ;
                  [0066E4]  3358  ; Create Ibox Process Context IPR.
                  [0066E4]  3359  ; Fill in ASN, FPE, clearing ASTEN, ASTRR, PPCE.
                  [0066E4]  3360  ;
                  [0066E4]  3361  ; Current state:
                  [0066E4]  3362  ;	p4	fen/pme quadword
                  [0066E4]  3363  ;	p6	asn
                  [0066E4]  3364  ;
                  [0066E4]  3365  	sll	p6, #EV6__PROCESS_CONTEXT__ASN__S, p6	; shift asn into place
                  [0066E4]  3366  	and	p4, #1, p4				; get just the fen bit
                  [0066E4]  3367  	sll	p4, #EV6__PROCESS_CONTEXT__FPE__S, p7	; shift fpe into place
                  [0066E4]  3368  	bis	p7, p6, p7				; or together
                  [0066E4]  3369  	hw_mtpr	p7, EV6__PROCESS_CONTEXT		; (4,0L) write them
                  [0066E4]  3370  
                  [0066E4]  3371    .if ne ev6_p1
                  [0066E4]  3372  	hw_ldq/p p7, PT__IMPURE(p_temp)			; get impure pointer
                  [0066E4]  3373  	hw_stq/p p7, CNS__FPE_STATE(p7)			; write FPE_STATE
                  [0066E4]  3374      .if ne fp_count
                  [0066E4]  3375  	hw_stq/p r31, PT__RSV_FOR_PAL(p_temp)		; clear counter
                  [0066E4]  3376      .endc
                  [0066E4]  3377    .endc
                  [0066E4]  3378  
                  [0066E4]  3379  ;
                  [0066E4]  3380  ; Do the cycle counter.
                  [0066E4]  3381  ; Not sure we need this, but ensure 4-7 clear before any dtb writes.
                  [0066E4]  3382  ; Current state:
                  [0066E4]  3383  ;
                  [0066E4]  3384  ;	p5		CPC from PCB
                  [0066E4]  3385  
                  [0066E4]  3386  	rpcc	r1				; get cycle counter
                  [0066E4]  3387  	subl	p5, r1, r1			; gen new offset
                  [0066E4]  3388  	insll	r1, #4, r1			; shift left 32
                  [0066E4]  3389  	hw_mtpr r1, <EV6__CC ! ^xF0>		; (4-7,1L) write it
                  [0066E4]  3390  	bis	r31, r31, r31
                  [0066E4]  3391  	bis	r31, r31, r31
                  [0066E4]  3392  	bis	r31, r31, r31
                  [0066E4]  3393  ;
                  [0066E4]  3394  ; Now we need to clear the lock flag, which must be done with a LDQ.
                  [0066E4]  3395  ; So we need to set up the DTB, do the write, and re-clear the DTB.
                  [0066E4]  3396  ;
                  [0066E4]  3397  	hw_mfpr	r1, EV6__PAL_BASE		; (4,0L) get pal base back
                  [0066E4]  3398  	sll	r1, #<32-13>, r2		; shift into position
                  [0066E4]  3399  	lda	r3, ^x1101(r31)			; set KWE, KRE
                  [0066E4]  3400  	or	r2, r3, r2			; produce pte
                  [0066E4]  3401  
                  [0066E4]  3402  	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
                  [0066E4]  3403  
                  [0066E4]  3404  	PVC_VIOLATE <2>				; ignore scoreboard violation
                  [0066E4]  3405  	hw_mtpr	r1, EV6__DTB_TAG0		; (2&6,0L) write tag0
                  [0066E4]  3406  	hw_mtpr r1, EV6__DTB_TAG1		; (1&5,1L) write tag1
                  [0066E4]  3407  	hw_mtpr	r2, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
                  [0066E4]  3408  	hw_mtpr	r2, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [0066E4]  3409  ;
                  [0066E4]  3410  ; Do the unlock.
                  [0066E4]  3411  ;
                  [0066E4]  3412  	ALIGN_FETCH_BLOCK <^x47FF041F>
                  [0066E4]  3413  	ldq	r31, <trap__lock_cell - trap__pal_base>(r1)
                  [0066E4]  3414  ;
                  [0066E4]  3415  ; Now clear the dtb again.
                  [0066E4]  3416  ;
                  [0066E4]  3417  	hw_mtpr	r31, EV6__DTB_IA		; (7,0L)
                  [0066E4]  3418  ;
                  [0066E4]  3419  ; Mark success, and hw_ret_stall to pc.
                  [0066E4]  3420  ;
                  [0066E4]  3421  	or	r31, r31, r0			; success
                  [0066E4]  3422  	hw_mtpr	r31, EV6__IC_FLUSH		; flush icache
                  [0066E4]  3423  	bne	r31, .				; pvc #24
                  [0066E4]  3424  	hw_ret_stall (p23)			; switch complete
                  [0066E4]  3425  
                  [0066E4]  3426  ;+
                  [0066E4]  3427  ; We must have jumped through 0. What should we do here?
                  [0066E4]  3428  ; Hey, how about doing an enter_console?
                  [0066E4]  3429  ;-
                  [0066E4]  3430  sys__reset_noswitch:
                  [0066E4]  3431  	lda	p20, HALT__JUMP0(r31)		; halt code of jump0
                  [0066E4]  3432  	hw_stq/p p20, PT__HALT_CODE(p_temp)	; store halt code
                  [0066E4]  3433  	br	r31, sys__enter_console		; enter console
                  [0066E4]  3434  
                  [0066E4]  3435  .endc						; if eq srm_console
                  [0066E4]  2818I 
                  [0066E4]  2819I ;+
                  [0066E4]  2820I ; System Reset code for non-srm systems.
                  [0066E4]  2821I ;
                  [0066E4]  2822I ; This code starts off as implementation dependent, because it must rely
                  [0066E4]  2823I ; on a signature to determine whether it came from the SROM. If it came
                  [0066E4]  2824I ; from the SROM, it does the normal initialization. If it didn't come from
                  [0066E4]  2825I ; the SROM, it needs to differentiate between a swap and a jump through 0.
                  [0066E4]  2826I ;
                  [0066E4]  2827I ; Check for signature. R19<31:16> contains the signature 0xDEC<letter>,
                  [0066E4]  2828I ; So just check <31:20> for 0xDEC.
                  [0066E4]  2829I ;
                  [0066E4]  2830I ; Assume also the absence of the signature says that we ABSOLUTELY
                  [0066E4]  2831I ;	did not come from a power up. Then I can check p_misc for
                  [0066E4]  2832I ;	a swap request.
                  [0066E4]  2833I ;
                  [0066E4]  2834I ; Entry:
                  [0066E4]  2835I ;	r1		dc_ctl
                  [0066E4]  2836I ;
                  [0066E4]  2837I ;	r15		srom_rev
                  [0066E4]  2838I ;	r16		proc_id
                  [0066E4]  2839I ;	r17		mem_size
                  [0066E4]  2840I ;	r18		cycle_cnt
                  [0066E4]  2841I ;	r19		signature in <31:16>
                  [0066E4]  2842I ;	r20		proc_mask (note: we are stepping on shadow!)
                  [0066E4]  2843I ;	r21		sysctx (note: we are stepping on p_temp shadow!)
                  [0066E4]  2844I ;
                  [0066E4]  2845I ;	r26		pc+4 of pal base
                  [0066E4]  2846I ;-
                  [0066E4]  2847I 	ALIGN_CACHE_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [0066E4]   275i 	.align 6
00000000 00000000 [0066EC]
00000000 00000000 [0066F4]
         00000000 [0066FC]
File: ev6_osf_system_pal.mar
                  [006700]  2848I 
                  [006700]  2849I sys__reset:
         4A619624 [006700]  2850I 	zapnot	r19, #^xC, r4			; clear all but <31:16>
         48829684 [006704]  2851I 	srl	r4, #20, r4			; get signature <31:20>
                  [006708]  2852I 	GET_32CONS r5, <^xDEC>, r31		; load validation pattern
File: ev6_pal_macros.mar
                  [006708]   239i  ASSUME <^xDEC> le  <^x7FFFFFFF>
         24BF0000 [006708]   240i 	ldah	r5,<<^xDEC>+32768>@-16(r31); + xxx<31:16>
         20A50DEC [00670C]   241i 	lda	r5,<<^xDEC> & ^XFFFF>(r5) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         408505A6 [006710]  2853I 	cmpeq	r4, r5, r6			; valid pattern?
                  [006714]  2854I 
         E4C0008D [006714]  2855I 	beq	r6, sys__reset_check_switch	; either swap or jump through 0
                  [006718]  2856I 
         443F041B [006718]  2857I 	bis	r1, r31, r27			; save off dc_ctl value
         469F041C [00671C]  2858I 	bis	r20, r31, r28			; save off proc_mask
         46BF041D [006720]  2859I 	bis	r21, r31, r29			; save off sysctx
                  [006724]  2860I 
         C3E00002 [006724]  2861I 	br	r31, sys__reset_init
                  [006728]  2862I ;
                  [006728]  2863I ; Init and w1c values
                  [006728]  2864I ;
                  [006728]  2865I 	EV6__DC_STAT__W1C = -
                  [006728]  2866I 		<<1@EV6__DC_STAT__TPERR_P0__S> ! -
                  [006728]  2867I 		<1@EV6__DC_STAT__TPERR_P1__S> ! -
                  [006728]  2868I 		<1@EV6__DC_STAT__ECC_ERR_ST__S> ! -
                  [006728]  2869I 		<1@EV6__DC_STAT__ECC_ERR_LD__S> ! -
                  [006728]  2870I 		<1@EV6__DC_STAT__SEO__S>>
                  [006728]  2871I 
                  [006728]  2872I ;
                  [006728]  2873I ; The ev6_p2 definition will still work for ev6_p3. Bit ^x1e becomes
                  [006728]  2874I ; a RO bit for the new performance counter implementation.
                  [006728]  2875I ;
                  [006728]  2876I .if ne ev6_p3
                  [006728]  2877I 	EV6__I_STAT__PAR__S = ^x1d
                  [006728]  2878I 	EV6__I_STAT__W1C = -
                  [006728]  2879I 		<<1@EV6__I_STAT__PAR__S>>
                  [006728]  2880I .iff
                  [006728]  2881I 	EV6__I_STAT__TPE__S = ^x1d
                  [006728]  2882I 	EV6__I_STAT__DPE__S = ^x1e
                  [006728]  2883I 	EV6__I_STAT__W1C = -
                  [006728]  2884I 		<<1@EV6__I_STAT__TPE__S> ! -
                  [006728]  2885I 		<1@EV6__I_STAT__DPE__S>>
                  [006728]  2886I .endc
                  [006728]  2881I 	EV6__I_STAT__TPE__S = ^x1d
                  [006728]  2882I 	EV6__I_STAT__DPE__S = ^x1e
                  [006728]  2883I 	EV6__I_STAT__W1C = -
                  [006728]  2884I 		<<1@EV6__I_STAT__TPE__S> ! -
                  [006728]  2885I 		<1@EV6__I_STAT__DPE__S>>
                  [006728]  2887I 
                  [006728]  2888I ;
                  [006728]  2889I ; On the reference platform, we get DC_CTL from the srom. These
                  [006728]  2890I ; init values are left for the convenience of other system partners.
                  [006728]  2891I ;
                  [006728]  2892I   .if eq reference_platform
                  [006728]  2893I     .if ne ev6_p1
                  [006728]  2894I 	EV6__DC_CTL__INIT = -
                  [006728]  2895I 		<<dcache_set_en@EV6__DC_CTL__SET_EN__S> ! -
                  [006728]  2896I 		 <0@EV6__DC_CTL__DCTAG_PAR_EN__S> ! -
                  [006728]  2897I 		 <0@EV6__DC_CTL__DCDAT_ERR_EN__S>>
                  [006728]  2898I     .iff
                  [006728]  2899I 	EV6__DC_CTL__INIT = -
                  [006728]  2900I 		<<dcache_set_en@EV6__DC_CTL__SET_EN__S> ! -
                  [006728]  2901I 		 <1@EV6__DC_CTL__DCTAG_PAR_EN__S> ! -
                  [006728]  2902I 		 <1@EV6__DC_CTL__DCDAT_ERR_EN__S>>
                  [006728]  2903I     .endc
                  [006728]  2904I   .endc
                  [006728]  2905I 
                  [006728]  2906I 	EV6__IER__INIT = 0
                  [006728]  2907I 
                  [006728]  2908I 	EV6__PCTX__INIT = -
                  [006728]  2909I 		<1@EV6__PROCESS_CONTEXT__FPE__S>
                  [006728]  2910I 
                  [006728]  2911I 	ASSUME EV6__HW_INT_CLR__MCHK_D__S lt EV6__HW_INT_CLR__PC__S 
                  [006728]  2912I 	ASSUME EV6__HW_INT_CLR__MCHK_D__S lt EV6__HW_INT_CLR__CR__S 
                  [006728]  2913I 	ASSUME EV6__HW_INT_CLR__MCHK_D__S lt EV6__HW_INT_CLR__SL__S 
                  [006728]  2914I 
                  [006728]  2915I 	EV6__HW_INT_CLR__INIT = -
                  [006728]  2916I 	    <<1@<EV6__HW_INT_CLR__MCHK_D__S - EV6__HW_INT_CLR__MCHK_D__S>> ! -
                  [006728]  2917I 	     <3@<EV6__HW_INT_CLR__PC__S - EV6__HW_INT_CLR__MCHK_D__S>> ! -
                  [006728]  2918I 	     <1@<EV6__HW_INT_CLR__CR__S - EV6__HW_INT_CLR__MCHK_D__S>> ! -
                  [006728]  2919I 	     <1@<EV6__HW_INT_CLR__SL__S - EV6__HW_INT_CLR__MCHK_D__S>>>
                  [006728]  2920I 
                  [006728]  2921I 	EV6__VA_CTL__INIT = <va_48@EV6__VA_CTL__VA_48__S>
                  [006728]  2922I 
                  [006728]  2923I .if ne kseg_hack				; kseg hack
                  [006728]  2924I 	EV6__M_CTL__INIT = 0
                  [006728]  2925I .iff
                  [006728]  2926I 	EV6__M_CTL__INIT = <2@<EV6__M_CTL__SPE__S+va_48>>
                  [006728]  2927I .endc
                  [006728]  2926I 	EV6__M_CTL__INIT = <2@<EV6__M_CTL__SPE__S+va_48>>
                  [006728]  2928I 
                  [006728]  2929I 	EV6__I_CTL__INIT = -
                  [006728]  2930I 		<<3@EV6__I_CTL__IC_EN__S> ! -
                  [006728]  2931I 		<2@<EV6__I_CTL__SPE__S+va_48>> ! -
                  [006728]  2932I 		<2@EV6__I_CTL__SDE__S> ! -
                  [006728]  2933I 		<3@EV6__I_CTL__SBE__S> ! -
                  [006728]  2934I 		<va_48@EV6__I_CTL__VA_48__S> ! -
                  [006728]  2935I 		<1@EV6__I_CTL__CALL_PAL_R23__S> ! -
                  [006728]  2936I 		<mchk_en@EV6__I_CTL__MCHK_EN__S> ! -
                  [006728]  2937I 		<tb_mb_en@EV6__I_CTL__TB_MB_EN__S>>
                  [006728]  2938I 
                  [006728]  2939I ;
                  [006728]  2940I ; Do the initialization. We rely on fetch blocks to separate scoreboard bits!!!
                  [006728]  2941I ;
                  [006728]  2942I ; Input:
                  [006728]  2943I ;	r26	pc+4 of pal base
                  [006728]  2944I ;
                  [006728]  2945I 	ALIGN_FETCH_BLOCK <^x47FF041F>			; pad with NOPs
File: ev6_pal_macros.mar
47FF041F 47FF041F [006728]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_system_pal.mar
                  [006730]  2946I 
                  [006730]  2947I 	ASSUME_FETCH_BLOCK
                  [006730]  2948I 	
                  [006730]  2949I sys__reset_init:
         77FF0310 [006730]  2950I 	hw_mtpr	r31, EV6__ITB_IA			; (4,0L) flush ITB
         77FFA380 [006734]  2951I 	hw_mtpr	r31, EV6__DTB_IA			; (7,0L) flush DTB
         4B41F681 [006738]  2952I 	srl	r26, #EV6__PAL_BASE__PAL_BASE__S, r1	; clean pal base
         4821F721 [00673C]  2953I 	sll	r1, #EV6__PAL_BASE__PAL_BASE__S, r1	; get into position
                  [006740]  2954I 
         77E11010 [006740]  2955I 	hw_mtpr	r1, EV6__PAL_BASE			; (4,0L) write pal base
                  [006744]  2956I 	GET_32CONS 	r1, EV6__I_STAT__W1C, r31	; get i_stat clr value
File: ev6_pal_macros.mar
                  [006744]   239i  ASSUME <ev6__i_stat__w1c> le  <^x7FFFFFFF>
         243F6000 [006744]   240i 	ldah	r1,<<ev6__i_stat__w1c>+32768>@-16(r31); + xxx<31:16>
         20210000 [006748]   241i 	lda	r1,<<ev6__i_stat__w1c> & ^XFFFF>(r1) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [00674C]  2957I 	GET_16CONS	r3, EV6__DC_STAT__W1C, r31	; get dc_stat clr value
File: ev6_pal_macros.mar
                  [00674C]   249i 	ASSUME <<ev6__dc_stat__w1c>> le  <^x7FFF>
         207F001F [00674C]   250i 	lda	r3,<ev6__dc_stat__w1c>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [006750]  2958I 
         77E11610 [006750]  2959I 	hw_mtpr	r1, EV6__I_STAT				; (4,0L) w1c I_STAT
         77E32A40 [006754]  2960I 	hw_mtpr r3, EV6__DC_STAT			; (6,0L) w1c DC_STAT
                  [006758]  2961I 	GET_32CONS 	r1, EV6__I_CTL__INIT, r31	; get i_ctl init value
File: ev6_pal_macros.mar
                  [006758]   239i  ASSUME <ev6__i_ctl__init> le  <^x7FFFFFFF>
         243F0011 [006758]   240i 	ldah	r1,<<ev6__i_ctl__init>+32768>@-16(r31); + xxx<31:16>
         202183A6 [00675C]   241i 	lda	r1,<<ev6__i_ctl__init> & ^XFFFF>(r1) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [006760]  2962I 
         77E11110 [006760]  2963I 	hw_mtpr	r1, EV6__I_CTL				; (4,0L) init I_CTL
         63FFE000 [006764]  2964I 	rc	r31					; clear intr_flag
         47FF041F [006768]  2965I 	bis	r31, r31, r31				; fetch block
         47FF041F [00676C]  2966I 	bis	r31, r31, r31				; fetch block
                  [006770]  2967I 
                  [006770]  2968I 	GET_16CONS 	r1, EV6__PCTX__INIT , r31	; get pctx init value
File: ev6_pal_macros.mar
                  [006770]   249i 	ASSUME <<ev6__pctx__init>> le  <^x7FFF>
         203F0004 [006770]   250i 	lda	r1,<ev6__pctx__init>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [006774]  2969I 	GET_16CONS	r3, EV6__M_CTL__INIT, r31	; get m_ctl init value
File: ev6_pal_macros.mar
                  [006774]   249i 	ASSUME <<ev6__m_ctl__init>> le  <^x7FFF>
         207F0008 [006774]   250i 	lda	r3,<ev6__m_ctl__init>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E15F10 [006778]  2970I 	hw_mtpr	r1, EV6__PROCESS_CONTEXT		; (4,0L) write pctx
         77E32840 [00677C]  2971I 	hw_mtpr r3, EV6__M_CTL				; (6,0L) write M_CTL
                  [006780]  2972I 
                  [006780]  2973I 	GET_32CONS	r1, EV6__IER__INIT, r31 	; get ier_cm init value
File: ev6_pal_macros.mar
                  [006780]   239i  ASSUME <ev6__ier__init> le  <^x7FFFFFFF>
         243F0000 [006780]   240i 	ldah	r1,<<ev6__ier__init>+32768>@-16(r31); + xxx<31:16>
         20210000 [006784]   241i 	lda	r1,<<ev6__ier__init> & ^XFFFF>(r1) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E10B10 [006788]  2974I 	hw_mtpr	r1, EV6__IER_CM				; (4,0L) clear int en
         77FFC020 [00678C]  2975I 	hw_mtpr r31, EV6__CC				; (5,1L) clear offset
                  [006790]  2976I 
         47E03401 [006790]  2977I 	bis	r31, #1, r1				; get a 1
         48241721 [006794]  2978I 	sll	r1, #32, r1				; get into position
         77FF0C10 [006798]  2979I 	hw_mtpr	r31, EV6__SIRR				; (4,0L) clear int req
         77E1C120 [00679C]  2980I 	hw_mtpr r1, EV6__CC_CTL				; (5,1L) clr/ena ctr
                  [0067A0]  2981I 
                  [0067A0]  2982I 	GET_16CONS	r1, EV6__HW_INT_CLR__INIT, r31	; get w1c mask
File: ev6_pal_macros.mar
                  [0067A0]   249i 	ASSUME <<ev6__hw_int_clr__init>> le  <^x7FFF>
         203F001F [0067A0]   250i 	lda	r1,<ev6__hw_int_clr__init>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         48239721 [0067A4]  2983I 	sll	r1, #EV6__HW_INT_CLR__MCHK_D__S, r1	; move into position
                  [0067A8]  2984I 	PVC_VIOLATE <35>
File: ev6_pal_macros.mar
                  [0067A8]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E10E10 [0067A8]  2985I 	hw_mtpr	r1, EV6__HW_INT_CLR			; (4,0L)
         77FF2640 [0067AC]  2986I 	hw_mtpr	r31, EV6__DTB_ALT_MODE			; (6,0L) clear alt_mode
                  [0067B0]  2987I 
         77FF1410 [0067B0]  2988I 	hw_mtpr	r31, EV6__PCTR_CTL			; (4,0L) clear pctr
                  [0067B4]  2989I 	GET_16CONS	r1, EV6__VA_CTL__INIT, r31	; get va_ctl value
File: ev6_pal_macros.mar
                  [0067B4]   249i 	ASSUME <<ev6__va_ctl__init>> le  <^x7FFF>
         203F0002 [0067B4]   250i 	lda	r1,<ev6__va_ctl__init>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E1C420 [0067B8]  2990I 	hw_mtpr	r1, EV6__VA_CTL				; (5,1L) init va_ctl
                  [0067BC]  2991I 	NOP						; pad fetch block
File: ev6_pal_macros.mar
         47FF041F [0067BC]   283i 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0067C0]  2992I ;
                  [0067C0]  2993I ; In normal operation, there must be a scoreboard bit -> register dependency
                  [0067C0]  2994I ; chain to prevent hw_mtpr DTB_ASx from issuing while ANY of scoreboard
                  [0067C0]  2995I ; bits <7:4> are set. Since we know there are no dstream operations going on,
                  [0067C0]  2996I ; we really don't need that here.
                  [0067C0]  2997I ;
                  [0067C0]  2998I 	PVC_VIOLATE <21>
File: ev6_pal_macros.mar
                  [0067C0]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77FF2510 [0067C0]  2999I 	hw_mtpr r31, EV6__DTB_ASN0			; (4,0L)
         77FFA580 [0067C4]  3000I 	hw_mtpr r31, EV6__DTB_ASN1			; (7,1L)
                  [0067C8]  3001I 	NOP						; pad fetch block
File: ev6_pal_macros.mar
         47FF041F [0067C8]   283i 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0067CC]  3002I 	NOP						; pad fetch block
File: ev6_pal_macros.mar
         47FF041F [0067CC]   283i 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0067D0]  3003I ;
                  [0067D0]  3004I ; We need to write pctr_ctl again to clear the 2nd stage overflow flag.
                  [0067D0]  3005I ; And force other mtpr to retire while we are at it.
                  [0067D0]  3006I ;
         77FF14F0 [0067D0]  3007I 	hw_mtpr	r31, <EV6__PCTR_CTL ! ^xF0>		; (4,0L) clr ovr flag
                  [0067D4]  3008I 	NOP						; pad fetch block
File: ev6_pal_macros.mar
         47FF041F [0067D4]   283i 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0067D8]  3009I 	NOP
File: ev6_pal_macros.mar
         47FF041F [0067D8]   283i 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0067DC]  3010I 	NOP
File: ev6_pal_macros.mar
         47FF041F [0067DC]   283i 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0067E0]  3011I ;
                  [0067E0]  3012I ; We need to write HW_INT_CLR to avoid a interrupt that can occur when
                  [0067E0]  3013I ; the counters come up in an unpredictable state near overflow.
                  [0067E0]  3014I ;
         20FF0003 [0067E0]  3015I 	lda	p7, 3(r31)			; 1.41 get a 3
         48E3B727 [0067E4]  3016I 	sll	p7, #EV6__HW_INT_CLR__PC__S, p7	; 1.41 move into position
         77E70E10 [0067E8]  3017I 	hw_mtpr	p7, EV6__HW_INT_CLR		; 1.41(4,0L) ack the int
         47FF041F [0067EC]  3018I 	bis	r31, r31, r31			; 1.41
         47FF041F [0067F0]  3019I 	bis	r31, r31, r31			; 1.41
         47FF041F [0067F4]  3020I 	bis	r31, r31, r31			; 1.41
                  [0067F8]  3021I 	PVC_VIOLATE <35>
File: ev6_pal_macros.mar
                  [0067F8]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E70E10 [0067F8]  3022I 	hw_mtpr	p7, EV6__HW_INT_CLR		; 1.41 (4,0L) ack the int
                  [0067FC]  3023I 
                  [0067FC]  3024I ;
                  [0067FC]  3025I ; FPCR is unpredictable, possibly set by the srom. Should we do anything here?
                  [0067FC]  3026I ;
                  [0067FC]  3027I   .if ne 0
                  [0067FC]  3028I 	mt_fpcr	f31					; clear the fpcr
                  [0067FC]  3029I   .endc							; (in separate block)
                  [0067FC]  3030I 
                  [0067FC]  3031I ;
                  [0067FC]  3032I ; 1.41 move cbox error read down below the virtual (clear lock) operation.
                  [0067FC]  3033I ;
                  [0067FC]  3034I 
                  [0067FC]  3035I ; Hardcode the whami for behavorial and
                  [0067FC]  3036I ; for not behavorial but not reference_platform.
                  [0067FC]  3037I ; the system.
                  [0067FC]  3038I ;
                  [0067FC]  3039I 
                  [0067FC]  3040I   .if ne beh_model
                  [0067FC]  3041I PAL__WHAMI = 0
                  [0067FC]  3042I 	GET_16CONS	r0, PAL__WHAMI, r31		; set whami
                  [0067FC]  3043I   .iff
                  [0067FC]  3044I     .if eq reference_platform
                  [0067FC]  3045I 	GET_16CONS	r0, PAL__WHAMI, r31		; set whami
                  [0067FC]  3046I     .iff
                  [0067FC]  3047I ;
                  [0067FC]  3048I ; Read the MISC<CPUID> bit for this cpu.
                  [0067FC]  3049I ; The MISC CSR is at 801.A000.0080.
                  [0067FC]  3050I ; This defines the value for PT__WHAMI.
                  [0067FC]  3051I ;
                  [0067FC]  3052I 	lda	p4, ^x801A(r31)			; generate 801.A000.0000
                  [0067FC]  3053I 	zap	p4, #^xFC, p4			; zap extension
                  [0067FC]  3054I 	sll	p4, #28, p4			; move into place
                  [0067FC]  3055I 	hw_ldq/p r0, ^x80(p4)			; Read CPUID from 801.A000.0080
                  [0067FC]  3056I 	and	r0, #^xF, r0			; Zap other bits.
                  [0067FC]  3057I     .endc					; if eq reference_platform
                  [0067FC]  3058I   .endc						; if ne beh_model
                  [0067FC]  3044I     .if eq reference_platform
                  [0067FC]  3045I 	GET_16CONS	r0, PAL__WHAMI, r31		; set whami
                  [0067FC]  3046I     .iff
                  [0067FC]  3047I ;
                  [0067FC]  3048I ; Read the MISC<CPUID> bit for this cpu.
                  [0067FC]  3049I ; The MISC CSR is at 801.A000.0080.
                  [0067FC]  3050I ; This defines the value for PT__WHAMI.
                  [0067FC]  3051I ;
                  [0067FC]  3052I 	lda	p4, ^x801A(r31)			; generate 801.A000.0000
                  [0067FC]  3053I 	zap	p4, #^xFC, p4			; zap extension
                  [0067FC]  3054I 	sll	p4, #28, p4			; move into place
                  [0067FC]  3055I 	hw_ldq/p r0, ^x80(p4)			; Read CPUID from 801.A000.0080
                  [0067FC]  3056I 	and	r0, #^xF, r0			; Zap other bits.
                  [0067FC]  3057I     .endc					; if eq reference_platform
                  [0067FC]  3047I ;
                  [0067FC]  3048I ; Read the MISC<CPUID> bit for this cpu.
                  [0067FC]  3049I ; The MISC CSR is at 801.A000.0080.
                  [0067FC]  3050I ; This defines the value for PT__WHAMI.
                  [0067FC]  3051I ;
         209F801A [0067FC]  3052I 	lda	p4, ^x801A(r31)			; generate 801.A000.0000
         489F9604 [006800]  3053I 	zap	p4, #^xFC, p4			; zap extension
         48839724 [006804]  3054I 	sll	p4, #28, p4			; move into place
         6C041080 [006808]  3055I 	hw_ldq/p r0, ^x80(p4)			; Read CPUID from 801.A000.0080
         4401F000 [00680C]  3056I 	and	r0, #^xF, r0			; Zap other bits.
                  [006810]  3059I       
                  [006810]  3060I ;
                  [006810]  3061I ; Initialize p_temp to base of specific pal temp area.
                  [006810]  3062I ; Store whami in pal temp area.
                  [006810]  3063I ; Compute base of specific impure area and store in pal temp area.
                  [006810]  3064I ;
                  [006810]  3065I 	GET_32CONS	p_temp, PAL__TEMPS_BASE, r31		; pal_temps base
File: ev6_pal_macros.mar
                  [006810]   239i  ASSUME <pal__temps_base> le  <^x7FFFFFFF>
         26BF0000 [006810]   240i 	ldah	p_temp,<<pal__temps_base>+32768>@-16(r31); + xxx<31:16>
         22B57000 [006814]   241i 	lda	p_temp,<<pal__temps_base> & ^XFFFF>(p_temp) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [006818]  3066I 	GET_32CONS	r1, PAL__TEMPS_SPECIFIC_SIZE, r31	; specific size
File: ev6_pal_macros.mar
                  [006818]   239i  ASSUME <pal__temps_specific_size> le  <^x7FFFFFFF>
         243F0000 [006818]   240i 	ldah	r1,<<pal__temps_specific_size>+32768>@-16(r31); + xxx<31:16>
         20210200 [00681C]   241i 	lda	r1,<<pal__temps_specific_size> & ^XFFFF>(r1) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         4C010401 [006820]  3067I 	mulq	r0, r1, r1					; whami * size
         42A10415 [006824]  3068I 	addq	p_temp, r1, p_temp				; cpu base
                  [006828]  3069I 
                  [006828]  3070I 	GET_32CONS	r2, <PAL__IMPURE_BASE>, r31	    ; impure area base
File: ev6_pal_macros.mar
                  [006828]   239i  ASSUME <PAL__IMPURE_BASE> le  <^x7FFFFFFF>
         245F0000 [006828]   240i 	ldah	r2,<<PAL__IMPURE_BASE>+32768>@-16(r31); + xxx<31:16>
         20424000 [00682C]   241i 	lda	r2,<<PAL__IMPURE_BASE> & ^XFFFF>(r2) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [006830]  3071I 	GET_16CONS	r1, <PAL__IMPURE_SPECIFIC_SIZE>, r31; specific size
File: ev6_pal_macros.mar
                  [006830]   249i 	ASSUME <<PAL__IMPURE_SPECIFIC_SIZE>> le  <^x7FFF>
         203F0600 [006830]   250i 	lda	r1,<PAL__IMPURE_SPECIFIC_SIZE>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [006834]  3072I 	GET_16CONS	r3, <PAL__IMPURE_COMMON_SIZE>, r31  ; common size
File: ev6_pal_macros.mar
                  [006834]   249i 	ASSUME <<PAL__IMPURE_COMMON_SIZE>> le  <^x7FFF>
         207F0200 [006834]   250i 	lda	r3,<PAL__IMPURE_COMMON_SIZE>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [006838]  3073I 
         4C010401 [006838]  3074I 	mulq	r0, r1, r1			; whami * specific
         40230401 [00683C]  3075I 	addq	r1, r3, r1			; add in common
         40410402 [006840]  3076I 	addq	r2, r1, r2			; add to impure base
         7C151098 [006844]  3077I 	hw_stq/p r0, PT__WHAMI(p_temp)		; store whami value
         7C551088 [006848]  3078I 	hw_stq/p r2, PT__IMPURE(p_temp)		; store pt_impure base address
                  [00684C]  3079I ;
                  [00684C]  3080I ; Now store M_CTL.
                  [00684C]  3081I ;
                  [00684C]  3082I 	GET_16CONS	r3, EV6__M_CTL__INIT, r31
File: ev6_pal_macros.mar
                  [00684C]   249i 	ASSUME <<ev6__m_ctl__init>> le  <^x7FFF>
         207F0008 [00684C]   250i 	lda	r3,<ev6__m_ctl__init>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         7C7510C0 [006850]  3083I 	hw_stq/p r3, PT__M_CTL(p_temp)		; store m_ctl value
                  [006854]  3084I ;
                  [006854]  3085I ; For reference platform, store passed up parameters.
                  [006854]  3086I ; For non-reference platform, store CNS__DC_CTL from an init value.
                  [006854]  3087I ;	NOTE: WE DON'T WRITE DC_CTL!! This is just here so we have
                  [006854]  3088I ;	a sane dc_ctl value.
                  [006854]  3089I ;
                  [006854]  3090I ; Current state for reference platform:
                  [006854]  3091I ;	r27	dc_ctl
                  [006854]  3092I ;		write_many chain in <51:16>
                  [006854]  3093I ;	r28	proc_mask
                  [006854]  3094I ;	r29	sysctx
                  [006854]  3095I ;
                  [006854]  3096I   .if ne reference_platform
                  [006854]  3097I 	srl	r27, #16, r1			; get write-many chain
                  [006854]  3098I 	hw_stq/p r1, CNS__WRITE_MANY(r2)	; store it
                  [006854]  3099I 	and	r27, #^xFF, r27			; clean dc_ctl
                  [006854]  3100I 	hw_stq/p r27, CNS__DC_CTL(r2)		; store dc_ctl value
                  [006854]  3101I 
                  [006854]  3102I 	hw_stq/p r15, CNS__SROM_REV(r2)		; encoded srom.s RCS revision
                  [006854]  3103I 	hw_stq/p r16, CNS__PROC_ID(r2)		; processor identification
                  [006854]  3104I 						; 	(a la SRM)
                  [006854]  3105I 	hw_stq/p r17, CNS__MEM_SIZE(r2)		; size of contiguous,
                  [006854]  3106I 						;	good memory in bytes
                  [006854]  3107I 	hw_stq/p r18, CNS__CYCLE_CNT(r2)	; cycle count in picoseconds
                  [006854]  3108I 	hw_stq/p r19, CNS__SIGNATURE(r2)	; signature (0xDECB) in <31:16>
                  [006854]  3109I 						;	and sys rev ID in <15:0>
                  [006854]  3110I 	bis	r31, r31, r19			; zap the signature
                  [006854]  3111I 	hw_stq/p r28, CNS__PROC_MASK(r2)	; active processor mask
                  [006854]  3112I 	hw_stq/p r29, CNS__SYSCTX(r2)		; system context value
                  [006854]  3113I   .iff
                  [006854]  3114I 	GET_16CONS	r27, EV6__DC_CTL__INIT, r31
                  [006854]  3115I 	hw_stq/p r27, CNS__DC_CTL(r2)		; store dc_ctl value
                  [006854]  3116I   .endc						; if ne reference_platform
         4B621681 [006854]  3097I 	srl	r27, #16, r1			; get write-many chain
         7C2213A8 [006858]  3098I 	hw_stq/p r1, CNS__WRITE_MANY(r2)	; store it
         477FF01B [00685C]  3099I 	and	r27, #^xFF, r27			; clean dc_ctl
         7F621398 [006860]  3100I 	hw_stq/p r27, CNS__DC_CTL(r2)		; store dc_ctl value
                  [006864]  3101I 
         7DE21270 [006864]  3102I 	hw_stq/p r15, CNS__SROM_REV(r2)		; encoded srom.s RCS revision
         7E021278 [006868]  3103I 	hw_stq/p r16, CNS__PROC_ID(r2)		; processor identification
                  [00686C]  3104I 						; 	(a la SRM)
         7E221280 [00686C]  3105I 	hw_stq/p r17, CNS__MEM_SIZE(r2)		; size of contiguous,
                  [006870]  3106I 						;	good memory in bytes
         7E421288 [006870]  3107I 	hw_stq/p r18, CNS__CYCLE_CNT(r2)	; cycle count in picoseconds
         7E621290 [006874]  3108I 	hw_stq/p r19, CNS__SIGNATURE(r2)	; signature (0xDECB) in <31:16>
                  [006878]  3109I 						;	and sys rev ID in <15:0>
         47FF0413 [006878]  3110I 	bis	r31, r31, r19			; zap the signature
         7F821298 [00687C]  3111I 	hw_stq/p r28, CNS__PROC_MASK(r2)	; active processor mask
         7FA212A0 [006880]  3112I 	hw_stq/p r29, CNS__SYSCTX(r2)		; system context value
                  [006884]  3117I   ;
                  [006884]  3118I ; For pass1, store CNS__FPE_STATE = 1.
                  [006884]  3119I ;
                  [006884]  3120I   .if ne ev6_p1
                  [006884]  3121I 	bis	r31, #1, r1			; get a 1
                  [006884]  3122I 	hw_stq/p r1, CNS__FPE_STATE(r2)		; start with fpe state = 1
                  [006884]  3123I 	hw_stq/p r31, CNS__R31_EMUL(r2)		; zap r31
                  [006884]  3124I 	hw_stq/p r31, CNS__F31_EMUL(r2)		; zap f31
                  [006884]  3125I 	hw_stq/p r31, CNS__FPCR(r2)		; zap fpcr
                  [006884]  3126I     .if ne fp_count
                  [006884]  3127I 	hw_stq/p r31, PT__RSV_FOR_PAL(p_temp)	; clear counter
                  [006884]  3128I     .endc
                  [006884]  3129I   .endc
                  [006884]  3130I 
                  [006884]  3131I ;
                  [006884]  3132I ; Write ps into a shadow register IPL=7,CM=0.
                  [006884]  3133I ; Write mces to pal temp area, with dpc set.
                  [006884]  3134I ;	
         47E0F416 [006884]  3135I 	bis	r31, #7, p_misc				; ipl=7, cm=0
         47E11401 [006888]  3136I 	bis	r31, #8, r1				; mces<dpc> = 1
         48221721 [00688C]  3137I 	sll	r1, #OSF_P_MISC__MCES__MCHK__S, r1	; move into position
         46C10416 [006890]  3138I 	bis	p_misc, r1, p_misc			; or new mces in
                  [006894]  3139I 
                  [006894]  3140I ;
                  [006894]  3141I ; Store lower portion in PT__VA_CTL in pal temps area.
                  [006894]  3142I ; Store VPTB in PT__VPTB in pal temps area.
                  [006894]  3143I ; Store DTB_ALT_MODE in pal temps area.
                  [006894]  3144I ;
                  [006894]  3145I 	GET_16CONS	r1, EV6__VA_CTL__INIT, r31
File: ev6_pal_macros.mar
                  [006894]   249i 	ASSUME <<ev6__va_ctl__init>> le  <^x7FFF>
         203F0002 [006894]   250i 	lda	r1,<ev6__va_ctl__init>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         7C3510B8 [006898]  3146I 	hw_stq/p r1, PT__VA_CTL(p_temp)		; store control part
         7FF51000 [00689C]  3147I 	hw_stq/p r31, PT__VPTB(p_temp)		; store vptb base part
         7FF51148 [0068A0]  3148I 	hw_stq/p r31, PT__DTB_ALT_MODE(p_temp)	; clear alt_mode temp
                  [0068A4]  3149I ;
                  [0068A4]  3150I ; Miscellaneous pal temps
                  [0068A4]  3151I ;
         7FF510A0 [0068A4]  3152I 	hw_stq/p r31, PT__SCC(p_temp)		; clear SCC
         7FF51170 [0068A8]  3153I 	hw_stq/p r31, PT__SCBB(p_temp)		; clear scb
         7FF51008 [0068AC]  3154I 	hw_stq/p r31, PT__PTBR(p_temp)		; clear ptbr
                  [0068B0]  3155I ;
                  [0068B0]  3156I ; Set up PT__PCBB to point to kludge PCB.
                  [0068B0]  3157I ;
         643F1010 [0068B0]  3158I 	hw_mfpr	r1, EV6__PAL_BASE		; (4,0L) get pal base back
                  [0068B4]  3159I 	GET_16ADDR 	r2, <INITIAL_PCBB - TRAP__START>, r1
File: ev6_pal_macros.mar
                  [0068B4]   230i 	ASSUME <<INITIAL_PCBB - TRAP__START>> le  <^x7FFF>
         20410C00 [0068B4]   231i 	lda	r2,<INITIAL_PCBB - TRAP__START>(r1) ; r1+xxx<15:0>
File: ev6_osf_system_pal.mar
         7C551010 [0068B8]  3160I 	hw_stq/p r2, PT__PCBB(p_temp)		; write pcbb
                  [0068BC]  3161I ;
                  [0068BC]  3162I ; Now we need to clear the lock flag, which must be done with a LDQ.
                  [0068BC]  3163I ; So we need to set up the DTB, do the write, and re-clear the DTB.
                  [0068BC]  3164I ;
                  [0068BC]  3165I ; Currently r1=pal base That's good enough to use for our translation.
                  [0068BC]  3166I ; Write the dtb, do the reference, clear the dtb and synch up.
                  [0068BC]  3167I ;
                  [0068BC]  3168I 
         48227722 [0068BC]  3169I 	sll	r1, #<32-13>, r2		; shift into position
         207F1101 [0068C0]  3170I 	lda	r3, ^x1101(r31)			; set KWE, KRE
         44430402 [0068C4]  3171I 	or	r2, r3, r2			; produce pte
                  [0068C8]  3172I 
                  [0068C8]  3173I 	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
47FF041F 47FF041F [0068C8]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_system_pal.mar
                  [0068D0]  3174I 
                  [0068D0]  3175I 	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [0068D0]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E12044 [0068D0]  3176I 	hw_mtpr	r1, EV6__DTB_TAG0		; (2&6,0L) write tag0
         77E1A022 [0068D4]  3177I 	hw_mtpr r1, EV6__DTB_TAG1		; (1&5,1L) write tag1
         77E22155 [0068D8]  3178I 	hw_mtpr	r2, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
         77E2A1AA [0068DC]  3179I 	hw_mtpr	r2, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [0068E0]  3180I ;
                  [0068E0]  3181I ; Do the unlock. Then clear the dtb.
                  [0068E0]  3182I ;
                  [0068E0]  3183I 	ALIGN_FETCH_BLOCK <^x47FF041F>		; align with NOPs
File: ev6_pal_macros.mar
                  [0068E0]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_system_pal.mar
         63FF4000 [0068E0]  3184I 	mb					; pvc restriction 28
         A7E10010 [0068E4]  3185I 	ldq	r31, <trap__lock_cell - trap__pal_base>(r1)
         47FF041F [0068E8]  3186I 	bis	r31, r31, r31
                  [0068EC]  3187I 
         77FFA380 [0068EC]  3188I 	hw_mtpr	r31, EV6__DTB_IA		; (7,0L)
         47FF041F [0068F0]  3189I 	bis	r31, r31, r31
         47FF041F [0068F4]  3190I 	bis	r31, r31, r31
         47FF041F [0068F8]  3191I 	bis	r31, r31, r31
                  [0068FC]  3192I 
         77FF2780 [0068FC]  3193I 	hw_mtpr	r31, <EV6__MM_STAT ! ^x80>	; 1.41 (7,0L) wait for dtb_ia
         47FF041F [006900]  3194I 	bis	r31, r31, r31			; 1.41
         47FF041F [006904]  3195I 	bis	r31, r31, r31			; 1.41
         47FF041F [006908]  3196I 	bis	r31, r31, r31			; 1.41
                  [00690C]  3197I ;
                  [00690C]  3198I ; Clear out the cbox error read chain
                  [00690C]  3199I ; 1.41 Move here from above
                  [00690C]  3200I ;
                  [00690C]  3201I ; Register use:
                  [00690C]  3202I ;	p4-p7	trashed
                  [00690C]  3203I ;	p20	trashed
                  [00690C]  3204I ;
                  [00690C]  3205I     .if eq force_path			; 1.41
                  [00690C]  3206I 	PVC_JSR cbox, bsr=1
                  [00690C]  3207I 	bsr	p5, sys__cbox
                  [00690C]  3208I     .iff
                  [00690C]  3209I 	PVC_VIOLATE <1008>		; 1.42 tell pvc to skip routine
                  [00690C]  3210I 	br	p5, sys__cbox
                  [00690C]  3211I     .endc				; 1.41
                  [00690C]  3206I 	PVC_JSR cbox, bsr=1
File: ev6_pal_macros.mar
                  [00690C]   531i  pvc_lbl \pcv_index, \pcv_jsr_cbox0, osf
File: ev6_osf_system_pal.mar
         D0BFFEB8 [00690C]  3207I 	bsr	p5, sys__cbox
                  [006910]  3212I     ;
                  [006910]  3213I ; Set up for the console
                  [006910]  3214I ;
                  [006910]  3215I 
                  [006910]  3216I ;
                  [006910]  3217I ; 1.41 Write EV6__IER to the platform dependent IPL31
                  [006910]  3218I ;
         47E3F401 [006910]  3219I 	bis     r31, #^x1f, r1			; IPL = 31
         649F1010 [006914]  3220I 	hw_mfpr p4, EV6__PAL_BASE		; (4,0L) get pal base
         40240644 [006918]  3221I 	s8addq  r1, p4, p4			; pal base + index
         20840D00 [00691C]  3222I 	lda     p4, ipl_offset(p4)		; pal base + table base + index
         6C841000 [006920]  3223I 	hw_ldq/p p4, (p4)			; get new ier
         77E40A10 [006924]  3224I 	hw_mtpr p4, EV6__IER			; (4,0L) write new ier
         47FF041F [006928]  3225I 	bis	r31, r31, r31
         47FF041F [00692C]  3226I 	bis	r31, r31, r31
         47FF041F [006930]  3227I 	bis	r31, r31, r31
         77FF2710 [006934]  3228I 	hw_mtpr r31, <EV6__MM_STAT ! ^x10>	; wait for it
                  [006938]  3229I 
         47FF0414 [006938]  3230I 	bis	r31, r31, p20			; halt code in p20
         47FF041F [00693C]  3231I 	bis	r31, r31, r31
         47FF041F [006940]  3232I 	bis	r31, r31, r31
         7FF510C8 [006944]  3233I 	hw_stq/p r31, PT__HALT_CODE(p_temp)	; store halt code
         C3FFFF0D [006948]  3234I 	br	r31, sys__enter_console		; enter console
                  [00694C]  3235I 
                  [00694C]  3236I 
                  [00694C]  3237I ;+
                  [00694C]  3238I ; The signature was not valid, so we DID NOT COME FROM THE SROM. So
                  [00694C]  3239I ; check for swap or jump through zero.
                  [00694C]  3240I ;-
                  [00694C]  3241I 
                  [00694C]  3242I sys__reset_check_switch:
         4AC7D681 [00694C]  3243I 	srl	p_misc, #OSF_P_MISC__SWITCH__S, r1	; check the switch bit
         E0200059 [006950]  3244I 	blbc	r1, sys__reset_noswitch			; jumped through 0
                  [006954]  3245I ;
                  [006954]  3246I ; Looks like a swppal. Do initialization, relying on fetch blocks for
                  [006954]  3247I ; scoreboard bit separation.
                  [006954]  3248I ;
                  [006954]  3249I 
                  [006954]  3250I 	ALIGN_FETCH_BLOCK <^x47FF041F>			; pad with NOPs
File: ev6_pal_macros.mar
47FF041F 47FF041F [006954]   265i 	.align 4, <^x47FF041F>
         47FF041F [00695C]
File: ev6_osf_system_pal.mar
                  [006960]  3251I 
                  [006960]  3252I 	ASSUME_FETCH_BLOCK
                  [006960]  3253I 
                  [006960]  3254I sys__switch_base:
         C0200000 [006960]  3255I 	br	r1, sys__switch_get_pal_base
                  [006964]  3256I sys__switch_get_pal_base:
                  [006964]  3257I 	GET_32ADDR r1, <trap__pal_base - sys__switch_get_pal_base>, r1
File: ev6_pal_macros.mar
                  [006964]   220i 	ASSUME <trap__pal_base - sys__switch_get_pal_base> le  <^x7FFFFFFF>
         24210000 [006964]   221i 	ldah	r1,<<trap__pal_base - sys__switch_get_pal_base>+32768>@-16(r1); + xxx<31:16>
         2021969C [006968]   222i 	lda	r1,<<trap__pal_base - sys__switch_get_pal_base> & ^xFFFF>(r1) ; r1+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E11010 [00696C]  3258I 	hw_mtpr	r1, EV6__PAL_BASE			; (4,0L) pal base
                  [006970]  3259I 
         77FF0310 [006970]  3260I 	hw_mtpr	r31, EV6__ITB_IA			; (4,0L)
         77FFA380 [006974]  3261I 	hw_mtpr	r31, EV6__DTB_IA			; (7,0L) flush DTB
                  [006978]  3262I 	GET_32CONS 	r1, EV6__I_STAT__W1C, r31	; get i_stat clr value
File: ev6_pal_macros.mar
                  [006978]   239i  ASSUME <ev6__i_stat__w1c> le  <^x7FFFFFFF>
         243F6000 [006978]   240i 	ldah	r1,<<ev6__i_stat__w1c>+32768>@-16(r31); + xxx<31:16>
         20210000 [00697C]   241i 	lda	r1,<<ev6__i_stat__w1c> & ^XFFFF>(r1) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [006980]  3263I 
                  [006980]  3264I 	GET_16CONS	R3, EV6__DC_STAT__W1C, R31	; get dc_stat clr value
File: ev6_pal_macros.mar
                  [006980]   249i 	ASSUME <<ev6__dc_stat__w1c>> le  <^x7FFF>
         207F001F [006980]   250i 	lda	r3,<ev6__dc_stat__w1c>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E11610 [006984]  3265I 	hw_mtpr	r1, EV6__I_STAT				; (4,0L) w1c I_STAT
         77E32A40 [006988]  3266I 	hw_mtpr r3, EV6__DC_STAT			; (6,0L) w1c DC_STAT
         63FFE000 [00698C]  3267I 	rc	r31					; clear intr_flag
                  [006990]  3268I 
                  [006990]  3269I 	GET_32CONS	r1, EV6__IER__INIT, r31 
File: ev6_pal_macros.mar
                  [006990]   239i  ASSUME <ev6__ier__init> le  <^x7FFFFFFF>
         243F0000 [006990]   240i 	ldah	r1,<<ev6__ier__init>+32768>@-16(r31); + xxx<31:16>
         20210000 [006994]   241i 	lda	r1,<<ev6__ier__init> & ^XFFFF>(r1) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E10B10 [006998]  3270I 	hw_mtpr	r1, EV6__IER_CM				; (4,0L) clear ier_cm
         77FF2640 [00699C]  3271I 	hw_mtpr	r31, EV6__DTB_ALT_MODE			; (6,0L) clear alt_mode
                  [0069A0]  3272I 
         7FF51148 [0069A0]  3273I 	hw_stq/p r31, PT__DTB_ALT_MODE(p_temp)		; clear alt_mode temp
         4AC09636 [0069A4]  3274I 	zapnot	p_misc, #4, p_misc			; zap all but mces
         46C0F416 [0069A8]  3275I 	bis	p_misc, #7, p_misc			; cm=0,ipl=7
         77FF0C10 [0069AC]  3276I 	hw_mtpr	r31, EV6__SIRR				; (4,0L) Clear int req
                  [0069B0]  3277I 	
                  [0069B0]  3278I 	GET_16CONS	r1, EV6__HW_INT_CLR__INIT, r31
File: ev6_pal_macros.mar
                  [0069B0]   249i 	ASSUME <<ev6__hw_int_clr__init>> le  <^x7FFF>
         203F001F [0069B0]   250i 	lda	r1,<ev6__hw_int_clr__init>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         48239721 [0069B4]  3279I 	sll	r1, #EV6__HW_INT_CLR__MCHK_D__S, r1	; move into position
                  [0069B8]  3280I 	PVC_VIOLATE <35>
File: ev6_pal_macros.mar
                  [0069B8]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E10E10 [0069B8]  3281I 	hw_mtpr	r1, EV6__HW_INT_CLR			; (4,0L) Clear int req
                  [0069BC]  3282I 	NOP						; pad fetch block
File: ev6_pal_macros.mar
         47FF041F [0069BC]   283i 	bis	r31, r31, r31
File: ev6_osf_system_pal.mar
                  [0069C0]  3283I ;
                  [0069C0]  3284I ; Current state:
                  [0069C0]  3285I ;	r17 (a1)	new PC
                  [0069C0]  3286I ;	r18 (a2)	new PCBB
                  [0069C0]  3287I ;	r19 (a3)	new VPTB
                  [0069C0]  3288I ;
         6C921028 [0069C0]  3289I 	hw_ldq/p p4, OSF_PCB__FEN(r18)		; get new fen/pme
         6CB20018 [0069C4]  3290I 	hw_ldl/p p5, OSF_PCB__CPC(r18)		; get charged cycle counter
         6CD2001C [0069C8]  3291I 	hw_ldl/p p6, OSF_PCB__ASN(r18)		; get new asn
         6CF21010 [0069CC]  3292I 	hw_ldq/p p7, OSF_PCB__PTBR(r18)		; get new ptbr
                  [0069D0]  3293I 
         48E1B727 [0069D0]  3294I 	sll	p7, #page_offset_size_bits, p7	; convert pfn to pa
         7CF51008 [0069D4]  3295I 	hw_stq/p p7, PT__PTBR(p_temp)		; store PTBR
         7E551010 [0069D8]  3296I 	hw_stq/p r18, PT__PCBB(p_temp)		; store PCBB
         46207117 [0069DC]  3297I 	bic	r17, #3, p23			; clean PC to p23
                  [0069E0]  3298I ;
                  [0069E0]  3299I ; Get VPTB and write it to VA_CTL and I_CTL. At the same time, initialize
                  [0069E0]  3300I ; VA_CTL, M_CTL, and I_CTL.
                  [0069E0]  3301I ;
                  [0069E0]  3302I ; Store lower portion in PT__VA_CTL in pal temps area.
                  [0069E0]  3303I ; Store VPTB in PT__VPTB in pal temps area.
                  [0069E0]  3304I ;
                  [0069E0]  3305I ; Initialize M_CTL  a write-only register, and save it away.
                  [0069E0]  3306I ;
                  [0069E0]  3307I ; Initialize I_CTL.
                  [0069E0]  3308I ; Write I_CTL twice (pvc #31).
                  [0069E0]  3309I ;
                  [0069E0]  3310I 
                  [0069E0]  3311I 	GET_16CONS	r1, EV6__VA_CTL__INIT, r31
File: ev6_pal_macros.mar
                  [0069E0]   249i 	ASSUME <<ev6__va_ctl__init>> le  <^x7FFF>
         203F0002 [0069E0]   250i 	lda	r1,<ev6__va_ctl__init>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         7C3510B8 [0069E4]  3312I 	hw_stq/p r1, PT__VA_CTL(p_temp)		; store control part
         7E751000 [0069E8]  3313I 	hw_stq/p r19, PT__VPTB(p_temp)		; store vptb base part
         44330401 [0069EC]  3314I 	bis	r1, r19, r1			; or in vptb part
                  [0069F0]  3315I 
         77E1C420 [0069F0]  3316I 	hw_mtpr	r1, EV6__VA_CTL			; (5,1L)
                  [0069F4]  3317I 	GET_16CONS	r1, EV6__M_CTL__INIT, r31
File: ev6_pal_macros.mar
                  [0069F4]   249i 	ASSUME <<ev6__m_ctl__init>> le  <^x7FFF>
         203F0008 [0069F4]   250i 	lda	r1,<ev6__m_ctl__init>(r31) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         77E12840 [0069F8]  3318I 	hw_mtpr r1, EV6__M_CTL			; (6,0L)
         7C3510C0 [0069FC]  3319I 	hw_stq/p r1, PT__M_CTL(p_temp)		; save it away
                  [006A00]  3320I 
                  [006A00]  3321I 	GET_32CONS 	r1, EV6__I_CTL__INIT, r31
File: ev6_pal_macros.mar
                  [006A00]   239i  ASSUME <ev6__i_ctl__init> le  <^x7FFFFFFF>
         243F0011 [006A00]   240i 	ldah	r1,<<ev6__i_ctl__init>+32768>@-16(r31); + xxx<31:16>
         202183A6 [006A04]   241i 	lda	r1,<<ev6__i_ctl__init> & ^XFFFF>(r1) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         44330401 [006A08]  3322I 	bis	r1, r19, r1			; or in vptb
                  [006A0C]  3323I 
         77E11110 [006A0C]  3324I 	hw_mtpr	r1, EV6__I_CTL				; (4,0L) write I_CTL
         47FF041F [006A10]  3325I 	bis	r31, r31, r31
         47FF041F [006A14]  3326I 	bis	r31, r31, r31
         47FF041F [006A18]  3327I 	bis	r31, r31, r31
                  [006A1C]  3328I 
         77E11110 [006A1C]  3329I 	hw_mtpr	r1, EV6__I_CTL				; (4,0L) write I_CTL
                  [006A20]  3330I ;
                  [006A20]  3331I ; Do USP and KSP
                  [006A20]  3332I ;
         6FD21008 [006A20]  3333I 	hw_ldq/p r30, OSF_PCB__USP(r18)		; get new USP
         7FD51020 [006A24]  3334I 	hw_stq/p r30, PT__USP(p_temp)		; save it away
         6FD21000 [006A28]  3335I 	hw_ldq/p r30, OSF_PCB__KSP(r18)		; get KSP
                  [006A2C]  3336I ;
                  [006A2C]  3337I ; Now do DTB_ASNx.
                  [006A2C]  3338I ;
                  [006A2C]  3339I ; There must be a scoreboard bit -> register dependency chain to prevent
                  [006A2C]  3340I ; hw_mtpr DTB_ASx from issuing while ANY of scoreboard bits <7:4> are set.
                  [006A2C]  3341I ;
                  [006A2C]  3342I ; Current state:
                  [006A2C]  3343I ;	p6	ASN
                  [006A2C]  3344I ;
                  [006A2C]  3345I ASSUME OSF_PCB__ASN__M eq ^xFF
                  [006A2C]  3346I 
         44DFF006 [006A2C]  3347I 	and	p6, #OSF_PCB__ASN__M, p6	; clean ASN quadword
         48C71734 [006A30]  3348I 	sll	p6, #EV6__DTB_ASN0__ASN__S, p20	; ASN into mbox spot
                  [006A34]  3349I 
         64FF10F0 [006A34]  3350I 	hw_mfpr	p7, <EV6__PAL_BASE ! ^xF0>	; (4-7, 0L)
         44E70807 [006A38]  3351I 	xor	p7, p7, p7			; zap p7
         44F40414 [006A3C]  3352I 	bis	p7, p20, p20			; force register dependency
         47FF041F [006A40]  3353I 	bis	r31, r31, r31
         77F42510 [006A44]  3354I 	hw_mtpr	p20, EV6__DTB_ASN0		; (4,0L)
         77F4A580 [006A48]  3355I 	hw_mtpr	p20, EV6__DTB_ASN1		; (7,1L)
                  [006A4C]  3356I 
                  [006A4C]  3357I ;
                  [006A4C]  3358I ; Create Ibox Process Context IPR.
                  [006A4C]  3359I ; Fill in ASN, FPE, clearing ASTEN, ASTRR, PPCE.
                  [006A4C]  3360I ;
                  [006A4C]  3361I ; Current state:
                  [006A4C]  3362I ;	p4	fen/pme quadword
                  [006A4C]  3363I ;	p6	asn
                  [006A4C]  3364I ;
         48C4F726 [006A4C]  3365I 	sll	p6, #EV6__PROCESS_CONTEXT__ASN__S, p6	; shift asn into place
         44803004 [006A50]  3366I 	and	p4, #1, p4				; get just the fen bit
         48805727 [006A54]  3367I 	sll	p4, #EV6__PROCESS_CONTEXT__FPE__S, p7	; shift fpe into place
         44E60407 [006A58]  3368I 	bis	p7, p6, p7				; or together
         77E75F10 [006A5C]  3369I 	hw_mtpr	p7, EV6__PROCESS_CONTEXT		; (4,0L) write them
                  [006A60]  3370I 
                  [006A60]  3371I   .if ne ev6_p1
                  [006A60]  3372I 	hw_ldq/p p7, PT__IMPURE(p_temp)			; get impure pointer
                  [006A60]  3373I 	hw_stq/p p7, CNS__FPE_STATE(p7)			; write FPE_STATE
                  [006A60]  3374I     .if ne fp_count
                  [006A60]  3375I 	hw_stq/p r31, PT__RSV_FOR_PAL(p_temp)		; clear counter
                  [006A60]  3376I     .endc
                  [006A60]  3377I   .endc
                  [006A60]  3378I 
                  [006A60]  3379I ;
                  [006A60]  3380I ; Do the cycle counter.
                  [006A60]  3381I ; Not sure we need this, but ensure 4-7 clear before any dtb writes.
                  [006A60]  3382I ; Current state:
                  [006A60]  3383I ;
                  [006A60]  3384I ;	p5		CPC from PCB
                  [006A60]  3385I 
         603FC000 [006A60]  3386I 	rpcc	r1				; get cycle counter
         40A10121 [006A64]  3387I 	subl	p5, r1, r1			; gen new offset
         48209561 [006A68]  3388I 	insll	r1, #4, r1			; shift left 32
         77E1C0F0 [006A6C]  3389I 	hw_mtpr r1, <EV6__CC ! ^xF0>		; (4-7,1L) write it
         47FF041F [006A70]  3390I 	bis	r31, r31, r31
         47FF041F [006A74]  3391I 	bis	r31, r31, r31
         47FF041F [006A78]  3392I 	bis	r31, r31, r31
                  [006A7C]  3393I ;
                  [006A7C]  3394I ; Now we need to clear the lock flag, which must be done with a LDQ.
                  [006A7C]  3395I ; So we need to set up the DTB, do the write, and re-clear the DTB.
                  [006A7C]  3396I ;
         643F1010 [006A7C]  3397I 	hw_mfpr	r1, EV6__PAL_BASE		; (4,0L) get pal base back
         48227722 [006A80]  3398I 	sll	r1, #<32-13>, r2		; shift into position
         207F1101 [006A84]  3399I 	lda	r3, ^x1101(r31)			; set KWE, KRE
         44430402 [006A88]  3400I 	or	r2, r3, r2			; produce pte
                  [006A8C]  3401I 
                  [006A8C]  3402I 	ALIGN_FETCH_BLOCK <^x47FF041F>		; Edit 1.36
File: ev6_pal_macros.mar
         47FF041F [006A8C]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_system_pal.mar
                  [006A90]  3403I 
                  [006A90]  3404I 	PVC_VIOLATE <2>				; ignore scoreboard violation
File: ev6_pal_macros.mar
                  [006A90]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E12044 [006A90]  3405I 	hw_mtpr	r1, EV6__DTB_TAG0		; (2&6,0L) write tag0
         77E1A022 [006A94]  3406I 	hw_mtpr r1, EV6__DTB_TAG1		; (1&5,1L) write tag1
         77E22155 [006A98]  3407I 	hw_mtpr	r2, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6) (0L) write pte0
         77E2A1AA [006A9C]  3408I 	hw_mtpr	r2, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5) (1L) write pte1
                  [006AA0]  3409I ;
                  [006AA0]  3410I ; Do the unlock.
                  [006AA0]  3411I ;
                  [006AA0]  3412I 	ALIGN_FETCH_BLOCK <^x47FF041F>
File: ev6_pal_macros.mar
                  [006AA0]   265i 	.align 4, <^x47FF041F>
File: ev6_osf_system_pal.mar
         A7E10010 [006AA0]  3413I 	ldq	r31, <trap__lock_cell - trap__pal_base>(r1)
                  [006AA4]  3414I ;
                  [006AA4]  3415I ; Now clear the dtb again.
                  [006AA4]  3416I ;
         77FFA380 [006AA4]  3417I 	hw_mtpr	r31, EV6__DTB_IA		; (7,0L)
                  [006AA8]  3418I ;
                  [006AA8]  3419I ; Mark success, and hw_ret_stall to pc.
                  [006AA8]  3420I ;
         47FF0400 [006AA8]  3421I 	or	r31, r31, r0			; success
         77FF1310 [006AAC]  3422I 	hw_mtpr	r31, EV6__IC_FLUSH		; flush icache
         F7E00000 [006AB0]  3423I 	bne	r31, .				; pvc #24
         7BF7A000 [006AB4]  3424I 	hw_ret_stall (p23)			; switch complete
                  [006AB8]  3425I 
                  [006AB8]  3426I ;+
                  [006AB8]  3427I ; We must have jumped through 0. What should we do here?
                  [006AB8]  3428I ; Hey, how about doing an enter_console?
                  [006AB8]  3429I ;-
                  [006AB8]  3430I sys__reset_noswitch:
         229F0040 [006AB8]  3431I 	lda	p20, HALT__JUMP0(r31)		; halt code of jump0
         7E9510C8 [006ABC]  3432I 	hw_stq/p p20, PT__HALT_CODE(p_temp)	; store halt code
         C3FFFEAF [006AC0]  3433I 	br	r31, sys__enter_console		; enter console
                  [006AC4]  3434I 
                  [006AC4]  3436  
                  [006AC4]  3437  
                  [006AC4]  3438  ;+
                  [006AC4]  3439  ; sys__wakeup
                  [006AC4]  3440  ;
                  [006AC4]  3441  ; Entry:
                  [006AC4]  3442  ;	A continuation of the wakup code.
                  [006AC4]  3443  ;
                  [006AC4]  3444  ; Current state:
                  [006AC4]  3445  ;	Retirator initialized.
                  [006AC4]  3446  ;	Registers mapped.
                  [006AC4]  3447  ;	shadow registers mapped.
                  [006AC4]  3448  ;	EV6__I_CTL = <<3@EV6__I_CTL__IC_EN__S> ! -
                  [006AC4]  3449  ;			<2@EV6__I_CTL__SDE__S> ! -
                  [006AC4]  3450  ;			<1@EV6__I_CTL__CALL_PAL_R23__S>>
                  [006AC4]  3451  ;	EV6__SIRR<28:14>	cpu number
                  [006AC4]  3452  ;	EV6__PAL_BASE		PAL base
                  [006AC4]  3453  ;-
                  [006AC4]  3454  
                  [006AC4]  3455  .if ne reference_platform
                  [006AC4]  3456  
                  [006AC4]  3457  	ALIGN_CACHE_BLOCK <^x43FF0400>		; pad with addq r31, r31, r0
                  [006AC4]  3458  
                  [006AC4]  3459  sys__wakeup:
                  [006AC4]  3460  
                  [006AC4]  3461  ;+
                  [006AC4]  3462  ; Now write the correct write-many chain, enabling the bcache.
                  [006AC4]  3463  ; First pull the code into the icache.
                  [006AC4]  3464  ;
                  [006AC4]  3465  ; Current state:
                  [006AC4]  3466  ;	SBE	off
                  [006AC4]  3467  ;	Bcache	off
                  [006AC4]  3468  ;-
                  [006AC4]  3469  
                  [006AC4]  3470  sys__wakeup_write_many_chain:
                  [006AC4]  3471  	hw_mfpr	p5, EV6__SIRR			; (4,0L) get cpu number
                  [006AC4]  3472  	srl 	p5, #EV6__SIRR__SIR__S, p5	; shift down
                  [006AC4]  3473  
                  [006AC4]  3474  	GET_32CONS	p_temp, PAL__TEMPS_BASE, r31		; pal_temps base
                  [006AC4]  3475  	GET_32CONS	p4, PAL__TEMPS_SPECIFIC_SIZE, r31	; specific size
                  [006AC4]  3476  	mulq	p5, p4, p4					; whami * size
                  [006AC4]  3477  	addq	p_temp, p4, p_temp				; cpu base
                  [006AC4]  3478  
                  [006AC4]  3479  	hw_ldq/p p6, PT__IMPURE(p_temp)		; get base of impure area
                  [006AC4]  3480  	hw_ldq/p r2, CNS__WRITE_MANY(p6)	; get write-many chain value
                  [006AC4]  3481  
                  [006AC4]  3482  	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
                  [006AC4]  3483  
                  [006AC4]  3484  sys__wakeup_touch1:
                  [006AC4]  3485  	mb					; (1)
                  [006AC4]  3486  	br	r31, sys__wakeup_touch2		; (2)
                  [006AC4]  3487  	bis	r31, r31, r31			; (3)
                  [006AC4]  3488  	bis	r31, r31, r31			; (4)				
                  [006AC4]  3489  
                  [006AC4]  3490  sys__wakeup_bc_on:
                  [006AC4]  3491  	bis	r31, r31, r31			; (4)				
                  [006AC4]  3492  	addq	r31, #6, r0			; (6) shift in 6x 6-bits
                  [006AC4]  3493  sys__wakeup_bc_on_loop::
                  [006AC4]  3494  	PVC_VIOLATE<30>				;
                  [006AC4]  3495  	hw_mtpr	r2, EV6__DATA			; (7) (6,0L) shift in 6 bits
                  [006AC4]  3496  	subq	r0, #1, r0			; (8) decrement R0
                  [006AC4]  3497  
                  [006AC4]  3498  	beq	r0, sys__wakeup_bc_on_done	; (9) done if R0 is zero
                  [006AC4]  3499  	srl	r2, #6, r2			; (10) align next 6 bits
                  [006AC4]  3500  	br	r31, sys__wakeup_bc_on_loop	; (11) continue shifting
                  [006AC4]  3501  sys__wakeup_bc_on_done:
                  [006AC4]  3502  	hw_mtpr	r31, <EV6__MM_STAT ! ^x40>	; (12) IPR write - sets SCBD 6
                  [006AC4]  3503  
                  [006AC4]  3504  	hw_mtpr	r31, <EV6__MM_STAT ! ^x40>	; (13) stalls until write retires
                  [006AC4]  3505  	beq	r31, sys__wakeup_probe		; (14) predicts fall thru
                  [006AC4]  3506  	PVC_VIOLATE <1006>
                  [006AC4]  3507  	br	r31, .-4			; (15) predict infinite loop
                  [006AC4]  3508  	addq	r31, r31, r2			; (16) nop
                  [006AC4]  3509  
                  [006AC4]  3510  	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
                  [006AC4]  3511  ;+
                  [006AC4]  3512  ; Now write the Cchip PRBEN, to renable probes.
                  [006AC4]  3513  ;-
                  [006AC4]  3514  sys__wakeup_touch2:
                  [006AC4]  3515  	mb
                  [006AC4]  3516  	br	r31, sys__wakeup_bc_on
                  [006AC4]  3517  
                  [006AC4]  3518  sys__wakeup_probe:
                  [006AC4]  3519  	lda	p4, ^x801A(r31)			; start to generate csr addr
                  [006AC4]  3520  	zapnot	p4, #3, p4			; zap extension
                  [006AC4]  3521  	sll	p4, #28, p4			; now have 801.A000.0000
                  [006AC4]  3522  	hw_stq/p r31, ^x340(p4)			; write to PRBEN
                  [006AC4]  3523  ;+
                  [006AC4]  3524  ; Get the proper IICx register.
                  [006AC4]  3525  ; 
                  [006AC4]  3526  ; Current state:
                  [006AC4]  3527  ;	p5	cpu number
                  [006AC4]  3528  ;-
                  [006AC4]  3529  
                  [006AC4]  3530  sys__wakeup_get_ticks:
                  [006AC4]  3531  
                  [006AC4]  3532  ;
                  [006AC4]  3533  ; Get address of IICx register.
                  [006AC4]  3534  ;
                  [006AC4]  3535  ; IICx	cpu 0	380	00 => 0011 1000 0000
                  [006AC4]  3536  ;	cpu 1	3c0	01 => 0011 1100 0000
                  [006AC4]  3537  ;	cpu 2	700	10 => 0111 0000 0000
                  [006AC4]  3538  ;	cpu 3	740	11 => 0111 0100 0000
                  [006AC4]  3539  ;
                  [006AC4]  3540  ;So we start with ^b0011 0000 0000
                  [006AC4]  3541  ;Then OR the whami into <10:9>
                  [006AC4]  3542  ;Then we XOR whami with ^b10 and OR it into <7:6>
                  [006AC4]  3543  ;
                  [006AC4]  3544  	lda	p4, ^x801A(r31)			; start to generate csr addr
                  [006AC4]  3545  	zapnot	p4, #3, p4			; zap extension
                  [006AC4]  3546  	sll	p4, #28, p4			; now have 801.A000.0000
                  [006AC4]  3547  	lda	p4, ^x300(p4)			; now have 801.A000.0300
                  [006AC4]  3548  
                  [006AC4]  3549  	sll	p5, #9, p6			; move whami to <10:9>
                  [006AC4]  3550  	xor	p5, #^b10, p7			; xor
                  [006AC4]  3551  	sll	p7, #6, p7			; move to <7:6>
                  [006AC4]  3552  
                  [006AC4]  3553  	bis	p4, p6, p4			; OR into <10:9>
                  [006AC4]  3554  	bis	p4, p7, p4			; OR into <7:6> to get IICx
                  [006AC4]  3555  
                  [006AC4]  3556  	hw_ldq/p  p20, (p4)			; get remaining ticks
                  [006AC4]  3557  
                  [006AC4]  3558  ;+
                  [006AC4]  3559  ; Now restore state.
                  [006AC4]  3560  ;
                  [006AC4]  3561  ; Current state:
                  [006AC4]  3562  ;	p20<24>		overflow bit
                  [006AC4]  3563  ;	p20<23:0>	remaining ticks
                  [006AC4]  3564  ;	p_temp		valid
                  [006AC4]  3565  ;
                  [006AC4]  3566  ;	PT__IMPURE	valid
                  [006AC4]  3567  ;-
                  [006AC4]  3568  
                  [006AC4]  3569  	PVC_JSR	restore_state, bsr=1
                  [006AC4]  3570  	bsr	p7, pal__restore_state		; restore state
                  [006AC4]  3571  
                  [006AC4]  3572  ;+
                  [006AC4]  3573  ; Now calculate ticks skipped. The counter keeps decrementing. Should the return
                  [006AC4]  3574  ; count max out at requested ticks? Or should be add in any additional? Right
                  [006AC4]  3575  ; now we max out at requested ticks.
                  [006AC4]  3576  ;
                  [006AC4]  3577  ; Current state:
                  [006AC4]  3578  ;	p20<24>		overflow bit
                  [006AC4]  3579  ;	p20<23:0>	remaining ticks
                  [006AC4]  3580  ;	p23		return address
                  [006AC4]  3581  ;
                  [006AC4]  3582  ;	r16	number of ticks to skip
                  [006AC4]  3583  ;-
                  [006AC4]  3584  
                  [006AC4]  3585  	srl	p20, #24, p4			; overflow bit
                  [006AC4]  3586  	zapnot	p20, #7, p20			; ticks remaining
                  [006AC4]  3587  
                  [006AC4]  3588  	zapnot	r16, #7, p5			; clean original number of ticks
                  [006AC4]  3589  	subq	p5, p20, r0			; get ticks skipped
                  [006AC4]  3590  	cmovlbs	p4, p5, r0			; if overflow => all
                  [006AC4]  3591  
                  [006AC4]  3592  ;+
                  [006AC4]  3593  ; Now we are done!
                  [006AC4]  3594  ;-
                  [006AC4]  3595  	hw_ret (p23)				; we are done!
                  [006AC4]  3596  
                  [006AC4]  3597  .endc
                  [006AC4]  3456I 
                  [006AC4]  3457I 	ALIGN_CACHE_BLOCK <^x43FF0400>		; pad with addq r31, r31, r0
File: ev6_pal_macros.mar
43FF0400 43FF0400 [006AC4]   273i 	.align 6, <^x43FF0400>
43FF0400 43FF0400 [006ACC]
43FF0400 43FF0400 [006AD4]
43FF0400 43FF0400 [006ADC]
43FF0400 43FF0400 [006AE4]
43FF0400 43FF0400 [006AEC]
43FF0400 43FF0400 [006AF4]
         43FF0400 [006AFC]
File: ev6_osf_system_pal.mar
                  [006B00]  3458I 
                  [006B00]  3459I sys__wakeup:
                  [006B00]  3460I 
                  [006B00]  3461I ;+
                  [006B00]  3462I ; Now write the correct write-many chain, enabling the bcache.
                  [006B00]  3463I ; First pull the code into the icache.
                  [006B00]  3464I ;
                  [006B00]  3465I ; Current state:
                  [006B00]  3466I ;	SBE	off
                  [006B00]  3467I ;	Bcache	off
                  [006B00]  3468I ;-
                  [006B00]  3469I 
                  [006B00]  3470I sys__wakeup_write_many_chain:
         64BF0C10 [006B00]  3471I 	hw_mfpr	p5, EV6__SIRR			; (4,0L) get cpu number
         48A1D685 [006B04]  3472I 	srl 	p5, #EV6__SIRR__SIR__S, p5	; shift down
                  [006B08]  3473I 
                  [006B08]  3474I 	GET_32CONS	p_temp, PAL__TEMPS_BASE, r31		; pal_temps base
File: ev6_pal_macros.mar
                  [006B08]   239i  ASSUME <pal__temps_base> le  <^x7FFFFFFF>
         26BF0000 [006B08]   240i 	ldah	p_temp,<<pal__temps_base>+32768>@-16(r31); + xxx<31:16>
         22B57000 [006B0C]   241i 	lda	p_temp,<<pal__temps_base> & ^XFFFF>(p_temp) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
                  [006B10]  3475I 	GET_32CONS	p4, PAL__TEMPS_SPECIFIC_SIZE, r31	; specific size
File: ev6_pal_macros.mar
                  [006B10]   239i  ASSUME <pal__temps_specific_size> le  <^x7FFFFFFF>
         249F0000 [006B10]   240i 	ldah	p4,<<pal__temps_specific_size>+32768>@-16(r31); + xxx<31:16>
         20840200 [006B14]   241i 	lda	p4,<<pal__temps_specific_size> & ^XFFFF>(p4) ; r31+xxx<15:0>
File: ev6_osf_system_pal.mar
         4CA40404 [006B18]  3476I 	mulq	p5, p4, p4					; whami * size
         42A40415 [006B1C]  3477I 	addq	p_temp, p4, p_temp				; cpu base
                  [006B20]  3478I 
         6CD51088 [006B20]  3479I 	hw_ldq/p p6, PT__IMPURE(p_temp)		; get base of impure area
         6C4613A8 [006B24]  3480I 	hw_ldq/p r2, CNS__WRITE_MANY(p6)	; get write-many chain value
                  [006B28]  3481I 
                  [006B28]  3482I 	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
File: ev6_pal_macros.mar
47FF041F 47FF041F [006B28]   273i 	.align 6, <^x47FF041F>
47FF041F 47FF041F [006B30]
47FF041F 47FF041F [006B38]
File: ev6_osf_system_pal.mar
                  [006B40]  3483I 
                  [006B40]  3484I sys__wakeup_touch1:
         63FF4000 [006B40]  3485I 	mb					; (1)
         C3E0000E [006B44]  3486I 	br	r31, sys__wakeup_touch2		; (2)
         47FF041F [006B48]  3487I 	bis	r31, r31, r31			; (3)
         47FF041F [006B4C]  3488I 	bis	r31, r31, r31			; (4)				
                  [006B50]  3489I 
                  [006B50]  3490I sys__wakeup_bc_on:
         47FF041F [006B50]  3491I 	bis	r31, r31, r31			; (4)				
         43E0D400 [006B54]  3492I 	addq	r31, #6, r0			; (6) shift in 6x 6-bits
                  [006B58]  3493I sys__wakeup_bc_on_loop::
                  [006B58]  3494I 	PVC_VIOLATE<30>				;
File: ev6_pal_macros.mar
                  [006B58]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         77E22B40 [006B58]  3495I 	hw_mtpr	r2, EV6__DATA			; (7) (6,0L) shift in 6 bits
         40003520 [006B5C]  3496I 	subq	r0, #1, r0			; (8) decrement R0
                  [006B60]  3497I 
         E4000002 [006B60]  3498I 	beq	r0, sys__wakeup_bc_on_done	; (9) done if R0 is zero
         4840D682 [006B64]  3499I 	srl	r2, #6, r2			; (10) align next 6 bits
         C3FFFFFB [006B68]  3500I 	br	r31, sys__wakeup_bc_on_loop	; (11) continue shifting
                  [006B6C]  3501I sys__wakeup_bc_on_done:
         77FF2740 [006B6C]  3502I 	hw_mtpr	r31, <EV6__MM_STAT ! ^x40>	; (12) IPR write - sets SCBD 6
                  [006B70]  3503I 
         77FF2740 [006B70]  3504I 	hw_mtpr	r31, <EV6__MM_STAT ! ^x40>	; (13) stalls until write retires
         E7E00004 [006B74]  3505I 	beq	r31, sys__wakeup_probe		; (14) predicts fall thru
                  [006B78]  3506I 	PVC_VIOLATE <1006>
File: ev6_pal_macros.mar
                  [006B78]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: ev6_osf_system_pal.mar
         C3FFFFFF [006B78]  3507I 	br	r31, .-4			; (15) predict infinite loop
         43FF0402 [006B7C]  3508I 	addq	r31, r31, r2			; (16) nop
                  [006B80]  3509I 
                  [006B80]  3510I 	ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
File: ev6_pal_macros.mar
                  [006B80]   273i 	.align 6, <^x47FF041F>
File: ev6_osf_system_pal.mar
                  [006B80]  3511I ;+
                  [006B80]  3512I ; Now write the Cchip PRBEN, to renable probes.
                  [006B80]  3513I ;-
                  [006B80]  3514I sys__wakeup_touch2:
         63FF4000 [006B80]  3515I 	mb
         C3FFFFF2 [006B84]  3516I 	br	r31, sys__wakeup_bc_on
                  [006B88]  3517I 
                  [006B88]  3518I sys__wakeup_probe:
         209F801A [006B88]  3519I 	lda	p4, ^x801A(r31)			; start to generate csr addr
         48807624 [006B8C]  3520I 	zapnot	p4, #3, p4			; zap extension
         48839724 [006B90]  3521I 	sll	p4, #28, p4			; now have 801.A000.0000
         7FE41340 [006B94]  3522I 	hw_stq/p r31, ^x340(p4)			; write to PRBEN
                  [006B98]  3523I ;+
                  [006B98]  3524I ; Get the proper IICx register.
                  [006B98]  3525I ; 
                  [006B98]  3526I ; Current state:
                  [006B98]  3527I ;	p5	cpu number
                  [006B98]  3528I ;-
                  [006B98]  3529I 
                  [006B98]  3530I sys__wakeup_get_ticks:
                  [006B98]  3531I 
                  [006B98]  3532I ;
                  [006B98]  3533I ; Get address of IICx register.
                  [006B98]  3534I ;
                  [006B98]  3535I ; IICx	cpu 0	380	00 => 0011 1000 0000
                  [006B98]  3536I ;	cpu 1	3c0	01 => 0011 1100 0000
                  [006B98]  3537I ;	cpu 2	700	10 => 0111 0000 0000
                  [006B98]  3538I ;	cpu 3	740	11 => 0111 0100 0000
                  [006B98]  3539I ;
                  [006B98]  3540I ;So we start with ^b0011 0000 0000
                  [006B98]  3541I ;Then OR the whami into <10:9>
                  [006B98]  3542I ;Then we XOR whami with ^b10 and OR it into <7:6>
                  [006B98]  3543I ;
         209F801A [006B98]  3544I 	lda	p4, ^x801A(r31)			; start to generate csr addr
         48807624 [006B9C]  3545I 	zapnot	p4, #3, p4			; zap extension
         48839724 [006BA0]  3546I 	sll	p4, #28, p4			; now have 801.A000.0000
         20840300 [006BA4]  3547I 	lda	p4, ^x300(p4)			; now have 801.A000.0300
                  [006BA8]  3548I 
         48A13726 [006BA8]  3549I 	sll	p5, #9, p6			; move whami to <10:9>
         44A05807 [006BAC]  3550I 	xor	p5, #^b10, p7			; xor
         48E0D727 [006BB0]  3551I 	sll	p7, #6, p7			; move to <7:6>
                  [006BB4]  3552I 
         44860404 [006BB4]  3553I 	bis	p4, p6, p4			; OR into <10:9>
         44870404 [006BB8]  3554I 	bis	p4, p7, p4			; OR into <7:6> to get IICx
                  [006BBC]  3555I 
         6E841000 [006BBC]  3556I 	hw_ldq/p  p20, (p4)			; get remaining ticks
                  [006BC0]  3557I 
                  [006BC0]  3558I ;+
                  [006BC0]  3559I ; Now restore state.
                  [006BC0]  3560I ;
                  [006BC0]  3561I ; Current state:
                  [006BC0]  3562I ;	p20<24>		overflow bit
                  [006BC0]  3563I ;	p20<23:0>	remaining ticks
                  [006BC0]  3564I ;	p_temp		valid
                  [006BC0]  3565I ;
                  [006BC0]  3566I ;	PT__IMPURE	valid
                  [006BC0]  3567I ;-
                  [006BC0]  3568I 
                  [006BC0]  3569I 	PVC_JSR	restore_state, bsr=1
File: ev6_pal_macros.mar
                  [006BC0]   531i  pvc_lbl \pcv_index, \pcv_jsr_restore_state0, osf
File: ev6_osf_system_pal.mar
         D0FFF7DA [006BC0]  3570I 	bsr	p7, pal__restore_state		; restore state
                  [006BC4]  3571I 
                  [006BC4]  3572I ;+
                  [006BC4]  3573I ; Now calculate ticks skipped. The counter keeps decrementing. Should the return
                  [006BC4]  3574I ; count max out at requested ticks? Or should be add in any additional? Right
                  [006BC4]  3575I ; now we max out at requested ticks.
                  [006BC4]  3576I ;
                  [006BC4]  3577I ; Current state:
                  [006BC4]  3578I ;	p20<24>		overflow bit
                  [006BC4]  3579I ;	p20<23:0>	remaining ticks
                  [006BC4]  3580I ;	p23		return address
                  [006BC4]  3581I ;
                  [006BC4]  3582I ;	r16	number of ticks to skip
                  [006BC4]  3583I ;-
                  [006BC4]  3584I 
         4A831684 [006BC4]  3585I 	srl	p20, #24, p4			; overflow bit
         4A80F634 [006BC8]  3586I 	zapnot	p20, #7, p20			; ticks remaining
                  [006BCC]  3587I 
         4A00F625 [006BCC]  3588I 	zapnot	r16, #7, p5			; clean original number of ticks
         40B40520 [006BD0]  3589I 	subq	p5, p20, r0			; get ticks skipped
         44850280 [006BD4]  3590I 	cmovlbs	p4, p5, r0			; if overflow => all
                  [006BD8]  3591I 
                  [006BD8]  3592I ;+
                  [006BD8]  3593I ; Now we are done!
                  [006BD8]  3594I ;-
         7BF78000 [006BD8]  3595I 	hw_ret (p23)				; we are done!
                  [006BDC]  3596I 
                  [006BDC]  3598  
                  [006BDC]  3599  
                  [006BDC]  3600  ;+
                  [006BDC]  3601  ; Routines for non-srm console on reference platform to do
                  [006BDC]  3602  ; i/o on the serial port.
                  [006BDC]  3603  ;-
                  [006BDC]  3604  
                  [006BDC]  3605  .if ne reference_platform
                  [006BDC]  3606    .if eq srm_console
                  [006BDC]  3607      .if ne dbm_serial_io
                  [006BDC]  3608  
                  [006BDC]  3609  	SROM_CSERVES
                  [006BDC]  3610  
                  [006BDC]  3611  	SROM_IO_FUNCTIONS
                  [006BDC]  3612  
                  [006BDC]  3613      .endc
                  [006BDC]  3614    .endc
                  [006BDC]  3615  .endc
                  [006BDC]  3606I   .if eq srm_console
                  [006BDC]  3607I     .if ne dbm_serial_io
                  [006BDC]  3608I 
                  [006BDC]  3609I 	SROM_CSERVES
                  [006BDC]  3610I 
                  [006BDC]  3611I 	SROM_IO_FUNCTIONS
                  [006BDC]  3612I 
                  [006BDC]  3613I     .endc
                  [006BDC]  3614I   .endc
                  [006BDC]  3607I     .if ne dbm_serial_io
                  [006BDC]  3608I 
                  [006BDC]  3609I 	SROM_CSERVES
                  [006BDC]  3610I 
                  [006BDC]  3611I 	SROM_IO_FUNCTIONS
                  [006BDC]  3612I 
                  [006BDC]  3613I     .endc
                  [006BDC]  3608I 
                  [006BDC]  3609I 	SROM_CSERVES
File: sromcsrv.mar
                  [006BDC]   112i 	ALIGN_FETCH_BLOCK
File: ev6_pal_macros.mar
         00000000 [006BDC]   267i 	.align 4
File: sromcsrv.mar
                  [006BE0]   114i Sys_Cserve_Srom_Init:
                  [006BE0]   115i 	PVC_JSR	auto, bsr=1
File: ev6_pal_macros.mar
                  [006BE0]   531i  pvc_lbl \pcv_index, \pcv_jsr_auto0, osf
File: sromcsrv.mar
         D0E00058 [006BE0]   116i 	bsr	p7, autobaud_sync	; do the autobaud thing	
         201F0100 [006BE4]   117i 	lda	r0, mc_m_echo(r31)	; get ^x100
         47000418 [006BE8]   118i 	bis	r24, r0, r24		; Enable echo 	
         471F0400 [006BEC]   119i 	bis	r24, r31, r0		; Return Line Status	
         7BF78000 [006BF0]   120i 	hw_ret	(p23)
                  [006BF4]   140i 	ALIGN_FETCH_BLOCK
File: ev6_pal_macros.mar
00000000 00000000 [006BF4]   267i 	.align 4
         00000000 [006BFC]
File: sromcsrv.mar
                  [006C00]   142i Sys_Cserve_Srom_Putc:
         467F0418 [006C00]   143i 	bis	r19, r31, r24
                  [006C04]   144i 	PVC_JSR putchar, bsr=1
File: ev6_pal_macros.mar
                  [006C04]   531i  pvc_lbl \pcv_index, \pcv_jsr_putchar0, osf
File: sromcsrv.mar
         D0E0002B [006C04]   145i 	bsr	p7, putChar
         7BF78000 [006C08]   146i 	hw_ret	(p23)
                  [006C0C]   166i 	ALIGN_FETCH_BLOCK
File: ev6_pal_macros.mar
         00000000 [006C0C]   267i 	.align 4
File: sromcsrv.mar
                  [006C10]   168i Sys_Cserve_Srom_Getc:
         467F0418 [006C10]   169i 	bis	r19, r31, r24
                  [006C14]   170i 	PVC_JSR	getchar, bsr=1
File: ev6_pal_macros.mar
                  [006C14]   531i  pvc_lbl \pcv_index, \pcv_jsr_getchar0, osf
File: sromcsrv.mar
         D0E00008 [006C14]   171i 	bsr	p7, getChar
         7BF78000 [006C18]   172i 	hw_ret	(p23)
File: ev6_osf_system_pal.mar
                  [006C1C]  3610I 
                  [006C1C]  3611I 	SROM_IO_FUNCTIONS
File: sromio.mar
                  [006C1C]    89i keypressed:
         641F0D00 [006C1C]    90i 	hw_mfpr	r0, ev6__isum 			; read Interrupt Summary Register 
         48041680 [006C20]    91i 	srl	r0, #ev6__isum__sl__s, r0	; r0<0> <- Serial Line Intrpt bit 
         44003000 [006C24]    92i 	and	r0, #ev6__isum__sl__m, r0	; :				 
         48041720 [006C28]    93i 	sll	r0, #ev6__hw_int_clr__sl__s, r0	; put into position		 
                  [006C2C]    94i 	PVC_VIOLATE <11>			; EJS -- ignore lack of stall
File: ev6_pal_macros.mar
                  [006C2C]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
                  [006C2C]    95i 	PVC_VIOLATE <35>			; EJS -- ignore not writing twice
File: ev6_pal_macros.mar
                  [006C2C]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
         77E00E10 [006C2C]    96i 	hw_mtpr	r0, ev6__hw_int_clr		; Clear any serial line intrpt 
         440034C0 [006C30]    97i 	cmovne	r0, #1, r0			; Return 1 if a key was pressed  
                  [006C34]    99i 	PVC_VIOLATE <29>
File: ev6_pal_macros.mar
                  [006C34]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
                  [006C34]   100i 	PVC_JSR	key, bsr=1, dest=1
File: ev6_pal_macros.mar
                  [006C34]   534i  pvc_lbl \pcv_index, \pcv_jsr_key0, osf, \pcv_jsr_key0_inst
File: sromio.mar
         6BF48000 [006C34]   101i 	ret	r31, (r20)
                  [006C38]   131i getChar:
         205F0008 [006C38]   132i 	lda	r2, <0+8>(r31)			; Set the bit count to 0.	 
         47F41403 [006C3C]   134i 	bis	r31, #<20*8>, r3		; Character timeout 20 characters
                  [006C40]   138i char_start:
         641F1110 [006C40]   139i 	hw_mfpr	r0, ev6__i_ctl			; Poll the serial line		 
         4801D680 [006C44]   140i         srl     r0, #ev6__i_ctl__sl_rcv__s, r0	;
         E0000005 [006C48]   141i 	blbc	r0, start_bit			; until low -> start bit is '0'
                  [006C4C]   143i 	PVC_JSR	wait, bsr=1
File: ev6_pal_macros.mar
                  [006C4C]   531i  pvc_lbl \pcv_index, \pcv_jsr_wait0, osf
File: sromio.mar
         D2800030 [006C4C]   144i 	bsr	r20, waitBitEighth		; Wait for a Eighth bit time	 
         40610523 [006C50]   146i 	subq	r3, 1, r3			; decrement timout
                  [006C54]   147i 	PVC_VIOLATE <1008>			; EJS -- dont follow branch
File: ev6_pal_macros.mar
                  [006C54]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
         F47FFFFA [006C54]   148i 	bne	r3, char_start			; branch until timeout reached
         201FFFFF [006C58]   149i 	lda	r0, -1(r31)			; Return failure code
                  [006C5C]   151i 	PVC_VIOLATE <29>
File: ev6_pal_macros.mar
                  [006C5C]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
                  [006C5C]   152i 	PVC_JSR	getchar, bsr=1, dest=1
File: ev6_pal_macros.mar
                  [006C5C]   534i  pvc_lbl \pcv_index, \pcv_jsr_getchar0, osf, \pcv_jsr_getchar0_inst
File: sromio.mar
         6BE78000 [006C5C]   153i 	ret	r31, (p7)			; return to caller		 
                  [006C60]   155i start_bit:
                  [006C60]   156i 	PVC_JSR	wait, bsr=1
File: ev6_pal_macros.mar
                  [006C60]   531i  pvc_lbl \pcv_index, \pcv_jsr_wait0, osf
File: sromio.mar
         D2800027 [006C60]   157i 	bsr	r20, waitBitHalf		; Wait for a half bit time	 
                  [006C64]   159i get_bits:					; DO				 
                  [006C64]   160i 	PVC_JSR wait, bsr=1
File: ev6_pal_macros.mar
                  [006C64]   531i  pvc_lbl \pcv_index, \pcv_jsr_wait0, osf
File: sromio.mar
         D2800024 [006C64]   161i 	bsr	r20, waitBitTime		; : wait for one bit time	 
         641F1110 [006C68]   163i 	hw_mfpr	r0, ev6__i_ctl			; : Get the current data bit.	 
         4801D680 [006C6C]   164i 	srl 	r0, #ev6__i_ctl__sl_rcv__s, r0	; : r0<0> <- current data bit	 
         44003000 [006C70]   165i         and     r0, #1, r0			; :
         48020720 [006C74]   166i 	sll	r0, r2, r0			; : r0<r2> <- current data bit  
         44020402 [006C78]   167i 	bis	r0, r2, r2			; : r2 <- r2 .bit_or. r0	 
         20420001 [006C7C]   168i 	lda	r2, 1(r2)			; : Increment bit countr.	 
         445FF000 [006C80]   169i 	and	r2, #^xFF, r0			; : Ignore character in comp.	 
         400213A1 [006C84]   170i 	cmpult	r0, #16, r1			; : Do we have a byte now?
                  [006C88]   171i 	PVC_VIOLATE <1008>			; EJS -- dont follow branch
File: ev6_pal_macros.mar
                  [006C88]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
         F43FFFF6 [006C88]   172i 	bne	r1, get_bits			; WHILE bit count .NE. 8	 
                  [006C8C]   174i 	PVC_JSR wait, bsr=1
File: ev6_pal_macros.mar
                  [006C8C]   531i  pvc_lbl \pcv_index, \pcv_jsr_wait0, osf
File: sromio.mar
         D280001A [006C8C]   175i 	bsr	r20, waitBitTime		; Wait for the middle of the 	 
                  [006C90]   177i 	PVC_JSR	key, bsr=1
File: ev6_pal_macros.mar
                  [006C90]   531i  pvc_lbl \pcv_index, \pcv_jsr_key0, osf
File: sromio.mar
         D29FFFE2 [006C90]   178i 	bsr	r20, keypressed			; Clear serial line interrupts	 
         484030C0 [006C94]   180i 	extbl	r2, #1, r0			; Place character in R0.	 
         4B011681 [006C98]   181i 	srl	r24, #mc_v_echo, r1		; IF echo_flag set		 
         E0200004 [006C9C]   182i 	blbc	r1, exit_getchar		; THEN				 
         440B1801 [006CA0]   183i 	xor	r0, #ascii_X, r1		; : IF user sent X		 
         F4200002 [006CA4]   184i 	bne	r1, exit_getchar		; : THEN			 
         203F0100 [006CA8]   185i 	lda	r1, mc_m_echo(r31)
         47010118 [006CAC]   186i 	bic	r24, r1, r24			; : : clear the echo flag	 
                  [006CB0]   188i exit_getchar:					; ENDIF			 
                  [006CB0]   189i 	PVC_VIOLATE <29>
File: ev6_pal_macros.mar
                  [006CB0]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
                  [006CB0]   190i 	PVC_JSR	getchar, bsr=1, dest=1
File: ev6_pal_macros.mar
                  [006CB0]   534i  pvc_lbl \pcv_index, \pcv_jsr_getchar0, osf, \pcv_jsr_getchar0_inst
File: sromio.mar
         6BE78000 [006CB0]   191i 	ret	r31, (p7)			; return to caller		 
                  [006CB4]   227i putChar:
         4B011682 [006CB4]   228i 	srl	r24, #mc_v_echo, r2		; IF echo flag is clear THEN	 
         E040000E [006CB8]   229i 	blbc	r2, exit_putChar		; Output is disabled, exit	 
         205F0010 [006CBC]   233i 	lda	r2, 16(r31)			; 1 high + 1 start + 8 data + 	 
         22313F00 [006CC0]   235i 	lda	r17, ^x3F00(r17)		; add stop bits at the end and	 
         42203451 [006CC4]   236i 	s4addq	r17, #1, r17			; then add start and high bit	 
                  [006CC8]   238i data_bit:					; REPEAT			
         641F1110 [006CC8]   239i 	hw_mfpr	r0, ev6__i_ctl			; get current I_CTL value	
         203F0001 [006CCC]   240i 	lda	r1, 1(r31)			; r1 = mask for sl_xmit bit	
         4821B721 [006CD0]   241i 	sll	r1, #ev6__i_ctl__sl_xmit__s, r1 ; move to correct position 
         44010100 [006CD4]   242i 	bic	r0, r1, r0			; clear sl_xmit bit in old I_CTL value 
         E2200001 [006CD8]   243i 	blbc	r17, send_bit			; check the new sl_xmit bit	
         44010400 [006CDC]   244i 	bis	r0, r1, r0			; set sl_xmit bit in old I_CTL value 
                  [006CE0]   245i send_bit:					; continue			
         77E01110 [006CE0]   246i 	hw_mtpr	r0, ev6__i_ctl			; EV6 Send the data bit.	
         4A203691 [006CE4]   248i 	srl	r17, #1, r17			; Shift right, to the next bit. 
         40403522 [006CE8]   249i 	subq	r2, #1, r2			; Decrement the bit count.
                  [006CEC]   251i 	PVC_JSR	wait, bsr=1
File: ev6_pal_macros.mar
                  [006CEC]   531i  pvc_lbl \pcv_index, \pcv_jsr_wait0, osf
File: sromio.mar
         D2800002 [006CEC]   252i 	bsr	r20, waitBitTime		; wait for a bit time	   	 
                  [006CF0]   254i 	PVC_VIOLATE <1008>			; EJS -- dont follow branch
File: ev6_pal_macros.mar
                  [006CF0]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
         F45FFFF5 [006CF0]   255i 	bne	r2, data_bit			; UNTIL all data sent		 
                  [006CF4]   257i exit_putChar:
                  [006CF4]   258i 	PVC_JSR	putchar, bsr=1, dest=1
File: ev6_pal_macros.mar
                  [006CF4]   534i  pvc_lbl \pcv_index, \pcv_jsr_putchar0, osf, \pcv_jsr_putchar0_inst
File: sromio.mar
                  [006CF4]   259i 	PVC_VIOLATE <29>
File: ev6_pal_macros.mar
                  [006CF4]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
         6BE78000 [006CF4]   260i 	ret	r31, (p7)			; return to caller		 
                  [006CF8]   285i waitBitTime:
         4B041680 [006CF8]   286i 	srl	r24, #32, r0			; Get the timing info.		 
         C3E00005 [006CFC]   287i 	br	r31, waitBitCont
                  [006D00]   288i waitBitHalf:
         4B043680 [006D00]   289i 	srl	r24, #<32+1>, r0		; Divide timing info by 2.	 
         C3E00003 [006D04]   290i 	br	r31, waitBitCont
                  [006D08]   291i waitBitQuarter:
         4B045680 [006D08]   292i 	srl	r24, #<32+2>, r0		; Divide timing info by 4.	 
         C3E00001 [006D0C]   293i 	br	r31, waitBitCont
                  [006D10]   294i waitBitEighth:
         4B047680 [006D10]   295i 	srl	r24, #<32+3>, r0		; Divide timing info by 8.
                  [006D14]   296i waitBitCont:
                  [006D14]   298i wait_init:
         203F0001 [006D14]   299i 	lda	r1, 1(r31)			;  				 
         48241721 [006D18]   300i 	sll	r1, #ev6__cc_ctl__cc_ena__s, r1	; Move the cc_ena bit into correct position
         77E1C120 [006D1C]   301i 	hw_mtpr	r1, ev6__cc_ctl			; clear and enable cycle counter
         43FF041F [006D20]   302i 	addq	r31, r31, r31			; nop
         43FF041F [006D24]   303i 	addq	r31, r31, r31			; nop
         43FF041F [006D28]   304i 	addq	r31, r31, r31			; nop
         77FF2720 [006D2C]   305i         hw_mtpr r31, <ev6__mm_stat ! 32> 	; dummy IPR write
                  [006D30]   309i wait:						; REPEAT 			 
         603FC000 [006D30]   310i 	rpcc	r1				; : read the cycle count 	 
         4821F621 [006D34]   311i 	zapnot	r1, #^x0f, r1			; : clear the high longword 	 
         400109A1 [006D38]   312i 	cmplt	r0, r1, r1			; :  				 
                  [006D3C]   313i 	PVC_VIOLATE <1008>			; EJS -- dont take branch
File: ev6_pal_macros.mar
                  [006D3C]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
         E43FFFFC [006D3C]   314i 	beq	r1, wait			; UNTIL we have waited time 	 
                  [006D40]   316i 	PVC_VIOLATE <29>
File: ev6_pal_macros.mar
                  [006D40]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
                  [006D40]   317i 	PVC_JSR wait, bsr=1, dest=1
File: ev6_pal_macros.mar
                  [006D40]   534i  pvc_lbl \pcv_index, \pcv_jsr_wait0, osf, \pcv_jsr_wait0_inst
File: sromio.mar
         6BF48000 [006D40]   318i 	ret	r31, (r20)			; RETURN 			 
                  [006D44]   352i autobaud_sync:
         203F0001 [006D44]   353i 	lda	r1, 1(r31)			; r1 <- cc_ctl enable bit 	 
         48241721 [006D48]   354i 	sll	r1, #ev6__cc_ctl__cc_ena__s, r1	; Move the cc_ena bit into correct position
                  [006D4C]   356i 	PVC_JSR	key, bsr=1
File: ev6_pal_macros.mar
                  [006D4C]   531i  pvc_lbl \pcv_index, \pcv_jsr_key0, osf
File: sromio.mar
         D29FFFB3 [006D4C]   357i 	bsr	r20, keypressed			; Clear serial line interrupts	 
                  [006D50]   361i poll_start:					; DO 				 
         641F1110 [006D50]   362i 	hw_mfpr	r0, ev6__i_ctl			; : r0 <- sl_rcv 		 
         4801D680 [006D54]   363i 	srl 	r0, #ev6__i_ctl__sl_rcv__s, r0	; : r0<0> <- current data bit	 
                  [006D58]   364i 	PVC_VIOLATE <1008>			; EJS -- do not follow branch
File: ev6_pal_macros.mar
                  [006D58]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
         F01FFFFD [006D58]   365i     	blbs	r0, poll_start			; WHILE sl_rcv remains high
         77E1C120 [006D5C]   366i 	hw_mtpr	r1, ev6__cc_ctl			; Enable/clear the cycle counter.  
                  [006D60]   370i poll_h:                   			; : REPEAT 			 
         641F1110 [006D60]   371i 	hw_mfpr	r0, ev6__i_ctl			; : r0 <- sl_rcv 		 
         4801D680 [006D64]   372i 	srl 	r0, #ev6__i_ctl__sl_rcv__s, r0	; : r0<0> <- current data bit
                  [006D68]   373i 	PVC_VIOLATE <1008>			; EJS -- do not follow branch	 
File: ev6_pal_macros.mar
                  [006D68]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
         E01FFFFD [006D68]   374i         blbc	r0, poll_h			; : UNTIL sl_rcv goes HI 	 
         603FC000 [006D6C]   376i 	rpcc	r1				; Record low-to-hi transition.  
         483E1601 [006D70]   377i 	zap	r1, #^xF0, r1			; blow off the high longword	 
                  [006D74]   381i poll_l:						; : REPEAT 			 
         601FC000 [006D74]   382i 	rpcc	r0
         481E1600 [006D78]   383i 	zap	r0, #^xF0, r0			; blow off the high longword	 
         48207722 [006D7C]   384i 	sll	r1, #3, r2			; 8 times low-to-high time.	 
         404003A0 [006D80]   385i 	cmpult  r2, r0, r0			; Have reached stop bit?	 
         F4000004 [006D84]   386i 	bne	r0, end_sync
         641F1110 [006D88]   387i 	hw_mfpr	r0, ev6__i_ctl			; : r0 <- sl_rcv 		 
         4801D680 [006D8C]   388i 	srl 	r0, #ev6__i_ctl__sl_rcv__s, r0	; : r0<0> <- current data bit
                  [006D90]   389i 	PVC_VIOLATE <1008>			; EJS -- do not follow branch	 
File: ev6_pal_macros.mar
                  [006D90]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
         F01FFFF8 [006D90]   390i         blbs	r0, poll_l			; : UNTIL sl_rcv goes LO 	
                  [006D94]   391i 	PVC_VIOLATE <1008> 
File: ev6_pal_macros.mar
                  [006D94]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
         C3FFFFF2 [006D94]   392i 	br	r31, poll_h			; Wait for next low-to-hi trans
                  [006D98]   394i end_sync:
         201F0000 [006D98]   395i 	lda	r0, 0(r31)			; Divide total cycle count (r1) 
                  [006D9C]   396i simple_div:
         4C013402 [006D9C]   397i 	mulq	r0, #9, r2			; by 9 (8 data + 1 start bit)	 
         404103A2 [006DA0]   398i 	cmpult	r2, r1, r2			; This is a simple divide.
         E4400002 [006DA4]   399i 	beq	r2, set_baud			; R0 = R1/9
         40003400 [006DA8]   400i 	addq	r0, #1, r0
         C3FFFFFB [006DAC]   401i 	br	r31, simple_div
                  [006DB0]   403i set_baud:
         48041720 [006DB0]   404i 	sll	r0,  #32, r0			; move to hi longword 		 
         23000100 [006DB4]   405i 	lda	r24, mc_m_echo(r0)		; r24 <- cycles-per-bit  	 
                  [006DB8]   407i 	PVC_JSR	auto, bsr=1, dest=1
File: ev6_pal_macros.mar
                  [006DB8]   534i  pvc_lbl \pcv_index, \pcv_jsr_auto0, osf, \pcv_jsr_auto0_inst
File: sromio.mar
                  [006DB8]   408i 	PVC_VIOLATE <29>
File: ev6_pal_macros.mar
                  [006DB8]   548i  pvc_lbl \pcv_index, \pcv_rule, osf
File: sromio.mar
         6BE78000 [006DB8]   409i 	ret	r31, (p7)
File: ev6_osf_system_pal.mar
                  [006DBC]  3612I 
                  [006DBC]  3616        
         00000000 [006DBC]  3617  .align 6
                  [006DC0]  3618  
                  [006DC0]  3619  	END_FREE_CODE


			SYMBOL TABLE
			------------
_new_code_space                = [00000000 00006DC0]  
_pal_func_cont                 = [00000000 00000001]  
_pal_func_in_prog              = [00000000 00000000]  
_pal_vec_cont                  = [00000000 00000000]  
_start_of_last_pal_func        = [00000000 00003B80]  
_start_of_last_vec             = [00000000 00000780]  
add_extra_ret                  = [00000000 00000000]  
arith_cm_offset                = [00000000 00000010]  
arith_fpcr_offset              = [00000000 00000010]  
ascii_x                        = [00000000 00000058]  
asn_shift                      = [00000000 00000011]  
autobaud_sync                  = [00000000 00006D44]  Branch Displacement at 00006BE0 in PSECT 0000
bcache_size                    = [00000000 00000016]  
beh_model                      = [00000000 00000000]  
bpt_cm_offset                  = [00000000 00000010]  
c_addr_shift                   = [00000000 00000029]  
call_pal__bpt                  = [00000000 00003000]  
call_pal__bpt_post_if          = [00000000 00005540]  Branch Displacement at 00003008 in PSECT 0000
                                                      Branch Displacement at 00003048 in PSECT 0000
                                                      Branch Displacement at 00005674 in PSECT 0000
                                                      Branch Displacement at 00003A88 in PSECT 0000
call_pal__bugchk               = [00000000 00003040]  
call_pal__callsys              = [00000000 000030C0]  
call_pal__callsys_cont         = [00000000 000055C0]  Branch Displacement at 000030EC in PSECT 0000
call_pal__cflush               = [00000000 00002040]  
call_pal__clrfen               = [00000000 00003B80]  
call_pal__clrfen_cont          = [00000000 00005680]  Branch Displacement at 00003BBC in PSECT 0000
call_pal__cserve               = [00000000 00002240]  
call_pal__draina               = [00000000 00002080]  
call_pal__ecctest              = [00000000 000031C0]  
call_pal__ecctest_cont         = [00000000 00005600]  Branch Displacement at 000031F0 in PSECT 0000
call_pal__gentrap              = [00000000 00003A80]  
call_pal__halt                 = [00000000 00002000]  
call_pal__imb                  = [00000000 00003180]  
call_pal__perfmon_dis          = [00000000 000051C0]  Branch Displacement at 0000518C in PSECT 0000
call_pal__perfmon_en           = [00000000 00005240]  Branch Displacement at 00002E64 in PSECT 0000
call_pal__perfmon_en_wr        = [00000000 000053C0]  Branch Displacement at 00005184 in PSECT 0000
call_pal__perfmon_mux          = [00000000 00005280]  Branch Displacement at 00002E6C in PSECT 0000
call_pal__perfmon_opt          = [00000000 000052C0]  Branch Displacement at 00002E74 in PSECT 0000
call_pal__perfmon_rd           = [00000000 00005300]  Branch Displacement at 00002E44 in PSECT 0000
call_pal__perfmon_rd_istat     = [00000000 00005400]  Branch Displacement at 00002E54 in PSECT 0000
call_pal__perfmon_rd_pmpc      = [00000000 00005418]  Branch Displacement at 00002E5C in PSECT 0000
call_pal__perfmon_unknown      = [00000000 00005424]  Branch Displacement at 00005188 in PSECT 0000
call_pal__perfmon_wr           = [00000000 00005340]  Branch Displacement at 00002E4C in PSECT 0000
                                                      Branch Displacement at 000053D4 in PSECT 0000
call_pal__perfmon_wr_1         = [00000000 00005360]  Branch Displacement at 0000534C in PSECT 0000
call_pal__perfmon_wr_ipr       = [00000000 00005378]  Branch Displacement at 00005364 in PSECT 0000
call_pal__perfmon_zap          = [00000000 00005224]  Branch Displacement at 00005218 in PSECT 0000
call_pal__rdmces               = [00000000 00002400]  
call_pal__rdps                 = [00000000 00002D80]  
call_pal__rdunique             = [00000000 00003780]  
call_pal__rdusp                = [00000000 00002E80]  
call_pal__rdval                = [00000000 00002C80]  
call_pal__retsys               = [00000000 00002F40]  
call_pal__retsys_cont          = [00000000 00005440]  Branch Displacement at 00002F6C in PSECT 0000
call_pal__rti                  = [00000000 00002FC0]  
call_pal__rti_cont             = [00000000 00005480]  Branch Displacement at 00002FEC in PSECT 0000
call_pal__rti_to_kern          = [00000000 000054C8]  Branch Displacement at 00002FE8 in PSECT 0000
call_pal__start                = [00000000 00002000]  
call_pal__swpctx               = [00000000 00002C00]  
call_pal__swpctx_cont          = [00000000 00004F00]  Branch Displacement at 00002C38 in PSECT 0000
call_pal__swpipl               = [00000000 00002D40]  
call_pal__swppal               = [00000000 00002280]  
call_pal__swppal_addr          = [00000000 00004EA4]  Branch Displacement at 0000228C in PSECT 0000
call_pal__swppal_cont          = [00000000 00004E80]  Branch Displacement at 000022BC in PSECT 0000
                                                      Branch Displacement at 00004EB4 in PSECT 0000
call_pal__swppal_fail          = [00000000 00004EB8]  Branch Displacement at 00002294 in PSECT 0000
                                                      Branch Displacement at 000022B0 in PSECT 0000
                                                      Branch Displacement at 00004E84 in PSECT 0000
                                                      Branch Displacement at 00004EB0 in PSECT 0000
call_pal__swppal_osf           = [00000000 000022A8]  Branch Displacement at 0000229C in PSECT 0000
call_pal__tbi                  = [00000000 00002CC0]  
call_pal__tbi_addr             = [00000000 00002CC8]  Branch Displacement at 00002CC4 in PSECT 0000
call_pal__tbi_out              = [00000000 00002CE8]  Branch Displacement at 00002CD4 in PSECT 0000
call_pal__urti                 = [00000000 00003480]  
call_pal__urti_cont            = [00000000 00005640]  Branch Displacement at 000034AC in PSECT 0000
call_pal__urti_illop           = [00000000 00005664]  Branch Displacement at 00003498 in PSECT 0000
                                                      Branch Displacement at 000034A8 in PSECT 0000
call_pal__urti_ldq             = [00000000 0000349C]  
call_pal__whami                = [00000000 00002F00]  
call_pal__wrent                = [00000000 00002D00]  
call_pal__wrent_addr           = [00000000 00002D04]  Branch Displacement at 00002D00 in PSECT 0000
call_pal__wrent_out            = [00000000 00002D28]  Branch Displacement at 00002D10 in PSECT 0000
call_pal__wrfen                = [00000000 00002AC0]  
call_pal__wrfen_cont           = [00000000 00004EC0]  Branch Displacement at 00002AFC in PSECT 0000
call_pal__wripir               = [00000000 00002340]  
call_pal__wrkgp                = [00000000 00002DC0]  
call_pal__wrmces               = [00000000 00002440]  
call_pal__wrperfmon            = [00000000 00002E40]  
call_pal__wrperfmon_cont       = [00000000 00005180]  Branch Displacement at 00002E78 in PSECT 0000
call_pal__wrunique             = [00000000 000037C0]  
call_pal__wrusp                = [00000000 00002E00]  
call_pal__wrval                = [00000000 00002C40]  
call_pal__wrvptptr             = [00000000 00002B40]  
call_pal__wtint                = [00000000 00002F80]  
callsys_cm_offset              = [00000000 00000010]  
cfw__jtopal                    = [00000000 00006510]  Branch Displacement at 000064DC in PSECT 0000
cfw__rd_impure                 = [00000000 00006560]  Branch Displacement at 000064E4 in PSECT 0000
cfw__start                     = [00000000 0000650C]  Branch Displacement at 000064EC in PSECT 0000
chain__dc0__s                  = [00000000 0000002C]  
chain__dc0__v                  = [00000000 00000008]  
chain__dc1__s                  = [00000000 00000034]  
chain__dc1__v                  = [00000000 00000008]  
chain__stat__s                 = [00000000 00000027]  
chain__stat__v                 = [00000000 00000005]  
chain__sts__s                  = [00000000 00000023]  
chain__sts__v                  = [00000000 00000004]  
char_start                     = [00000000 00006C40]  Branch Displacement at 00006C54 in PSECT 0000
check_interrupt_pending        = [00000000 00000001]  
clrmap                         = [00000000 00000000]  
cns__cycle_cnt                 = [00000000 00000288]  
cns__dc_ctl                    = [00000000 00000398]  
cns__dc_stat                   = [00000000 000003A0]  
cns__dtb_alt_mode              = [00000000 00000380]  
cns__exc_addr                  = [00000000 00000330]  
cns__exc_sum                   = [00000000 00000350]  
cns__f0                        = [00000000 00000110]  
cns__f1                        = [00000000 00000118]  
cns__f10                       = [00000000 00000160]  
cns__f11                       = [00000000 00000168]  
cns__f12                       = [00000000 00000170]  
cns__f13                       = [00000000 00000178]  
cns__f14                       = [00000000 00000180]  
cns__f15                       = [00000000 00000188]  
cns__f16                       = [00000000 00000190]  
cns__f17                       = [00000000 00000198]  
cns__f18                       = [00000000 000001A0]  
cns__f19                       = [00000000 000001A8]  
cns__f2                        = [00000000 00000120]  
cns__f20                       = [00000000 000001B0]  
cns__f21                       = [00000000 000001B8]  
cns__f22                       = [00000000 000001C0]  
cns__f23                       = [00000000 000001C8]  
cns__f24                       = [00000000 000001D0]  
cns__f25                       = [00000000 000001D8]  
cns__f26                       = [00000000 000001E0]  
cns__f27                       = [00000000 000001E8]  
cns__f28                       = [00000000 000001F0]  
cns__f29                       = [00000000 000001F8]  
cns__f3                        = [00000000 00000128]  
cns__f30                       = [00000000 00000200]  
cns__f31                       = [00000000 00000208]  
cns__f4                        = [00000000 00000130]  
cns__f5                        = [00000000 00000138]  
cns__f6                        = [00000000 00000140]  
cns__f7                        = [00000000 00000148]  
cns__f8                        = [00000000 00000150]  
cns__f9                        = [00000000 00000158]  
cns__flag                      = [00000000 00000000]  
cns__fpcr                      = [00000000 00000318]  
cns__halt                      = [00000000 00000008]  
cns__halt_code                 = [00000000 00000248]  
cns__i_ctl                     = [00000000 00000360]  
cns__i_stat                    = [00000000 00000378]  
cns__ier_cm                    = [00000000 00000338]  
cns__impure                    = [00000000 00000218]  
cns__isum                      = [00000000 00000348]  
cns__ksp                       = [00000000 00000250]  
cns__m_ctl                     = [00000000 00000390]  
cns__mchkflag                  = [00000000 00000210]  
cns__mem_size                  = [00000000 00000280]  
cns__mm_stat                   = [00000000 00000388]  
cns__p20                       = [00000000 000002F8]  
cns__p23                       = [00000000 00000310]  
cns__p4                        = [00000000 000002D8]  
cns__p5                        = [00000000 000002E0]  
cns__p6                        = [00000000 000002E8]  
cns__p7                        = [00000000 000002F0]  
cns__p_misc                    = [00000000 00000308]  
cns__p_temp                    = [00000000 00000300]  
cns__pal_base                  = [00000000 00000358]  
cns__pcbb                      = [00000000 00000260]  
cns__pctr_ctl                  = [00000000 00000368]  
cns__place_holder18            = [00000000 000002A8]  
cns__place_holder19            = [00000000 000002B0]  
cns__place_holder20            = [00000000 000002B8]  
cns__place_holder21            = [00000000 000002C0]  
cns__place_holder22            = [00000000 000002C8]  
cns__place_holder23            = [00000000 000002D0]  
cns__prbr                      = [00000000 00000230]  
cns__proc_id                   = [00000000 00000278]  
cns__proc_mask                 = [00000000 00000298]  
cns__process_context           = [00000000 00000370]  
cns__ptbr                      = [00000000 00000238]  
cns__r0                        = [00000000 00000010]  
cns__r1                        = [00000000 00000018]  
cns__r10                       = [00000000 00000060]  
cns__r11                       = [00000000 00000068]  
cns__r12                       = [00000000 00000070]  
cns__r13                       = [00000000 00000078]  
cns__r14                       = [00000000 00000080]  
cns__r15                       = [00000000 00000088]  
cns__r16                       = [00000000 00000090]  
cns__r17                       = [00000000 00000098]  
cns__r18                       = [00000000 000000A0]  
cns__r19                       = [00000000 000000A8]  
cns__r2                        = [00000000 00000020]  
cns__r20                       = [00000000 000000B0]  
cns__r21                       = [00000000 000000B8]  
cns__r22                       = [00000000 000000C0]  
cns__r23                       = [00000000 000000C8]  
cns__r24                       = [00000000 000000D0]  
cns__r25                       = [00000000 000000D8]  
cns__r26                       = [00000000 000000E0]  
cns__r27                       = [00000000 000000E8]  
cns__r28                       = [00000000 000000F0]  
cns__r29                       = [00000000 000000F8]  
cns__r3                        = [00000000 00000028]  
cns__r30                       = [00000000 00000100]  
cns__r31                       = [00000000 00000108]  
cns__r4                        = [00000000 00000030]  
cns__r5                        = [00000000 00000038]  
cns__r6                        = [00000000 00000040]  
cns__r7                        = [00000000 00000048]  
cns__r8                        = [00000000 00000050]  
cns__r9                        = [00000000 00000058]  
cns__scbb                      = [00000000 00000258]  
cns__scc                       = [00000000 00000228]  
cns__signature                 = [00000000 00000290]  
cns__sirr                      = [00000000 00000340]  
cns__size                      = [00000000 000003B0]  
cns__srom_rev                  = [00000000 00000270]  
cns__sysctx                    = [00000000 000002A0]  
cns__trap                      = [00000000 00000240]  
cns__va                        = [00000000 00000320]  
cns__va_ctl                    = [00000000 00000328]  
cns__vptb                      = [00000000 00000268]  
cns__whami                     = [00000000 00000220]  
cns__write_many                = [00000000 000003A8]  
cserve__callback               = [00000000 00000002]  
cserve__jtopal                 = [00000000 00000009]  
cserve__rd_impure              = [00000000 0000000B]  
cserve__start                  = [00000000 00000001]  
cserve_k_srom_getc             = [00000000 00000020]  
cserve_k_srom_init             = [00000000 00000018]  
cserve_k_srom_putc             = [00000000 00000019]  
data_bit                       = [00000000 00006CC8]  Branch Displacement at 00006CF0 in PSECT 0000
dbm_serial_io                  = [00000000 00000001]  
dcache_set_en                  = [00000000 00000003]  
dfault_cm_offset               = [00000000 00000010]  
dpte_cm_offset                 = [00000000 00000010]  
dstream_dc_err                 = [00000000 00000005]  
end_sync                       = [00000000 00006D98]  Branch Displacement at 00006D84 in PSECT 0000
ev6__arith_entry               = [00000000 00000600]  
ev6__asn                       = [00000000 00004110]  
ev6__asn__asn__m               = [00000000 000000FF]  
ev6__asn__asn__s               = [00000000 00000027]  
ev6__asn__asn__v               = [00000000 00000008]  
ev6__asn__aster__m             = [00000000 0000000F]  
ev6__asn__aster__s             = [00000000 00000005]  
ev6__asn__aster__v             = [00000000 00000004]  
ev6__asn__astrr__m             = [00000000 0000000F]  
ev6__asn__astrr__s             = [00000000 00000009]  
ev6__asn__astrr__v             = [00000000 00000004]  
ev6__asn__fpe__m               = [00000000 00000001]  
ev6__asn__fpe__s               = [00000000 00000002]  
ev6__asn__fpe__v               = [00000000 00000001]  
ev6__asn__ppce__m              = [00000000 00000001]  
ev6__asn__ppce__s              = [00000000 00000001]  
ev6__asn__ppce__v              = [00000000 00000001]  
ev6__asn__rsv0__m              = [00000000 00000001]  
ev6__asn__rsv0__s              = [00000000 00000000]  
ev6__asn__rsv0__v              = [00000000 00000001]  
ev6__asn__rsv1__m              = [00000000 00000003]  
ev6__asn__rsv1__s              = [00000000 00000003]  
ev6__asn__rsv1__v              = [00000000 00000002]  
ev6__asn__rsv2__m              = [00000000 03FFFFFF]  
ev6__asn__rsv2__s              = [00000000 0000000D]  
ev6__asn__rsv2__v              = [00000000 0000001A]  
ev6__asn__rsv3__m              = [00000000 0001FFFF]  
ev6__asn__rsv3__s              = [00000000 0000002F]  
ev6__asn__rsv3__v              = [00000000 00000011]  
ev6__asn_aster                 = [00000000 00004310]  
ev6__asn_aster__asn__m         = [00000000 000000FF]  
ev6__asn_aster__asn__s         = [00000000 00000027]  
ev6__asn_aster__asn__v         = [00000000 00000008]  
ev6__asn_aster__aster__m       = [00000000 0000000F]  
ev6__asn_aster__aster__s       = [00000000 00000005]  
ev6__asn_aster__aster__v       = [00000000 00000004]  
ev6__asn_aster__astrr__m       = [00000000 0000000F]  
ev6__asn_aster__astrr__s       = [00000000 00000009]  
ev6__asn_aster__astrr__v       = [00000000 00000004]  
ev6__asn_aster__fpe__m         = [00000000 00000001]  
ev6__asn_aster__fpe__s         = [00000000 00000002]  
ev6__asn_aster__fpe__v         = [00000000 00000001]  
ev6__asn_aster__ppce__m        = [00000000 00000001]  
ev6__asn_aster__ppce__s        = [00000000 00000001]  
ev6__asn_aster__ppce__v        = [00000000 00000001]  
ev6__asn_aster__rsv0__m        = [00000000 00000001]  
ev6__asn_aster__rsv0__s        = [00000000 00000000]  
ev6__asn_aster__rsv0__v        = [00000000 00000001]  
ev6__asn_aster__rsv1__m        = [00000000 00000003]  
ev6__asn_aster__rsv1__s        = [00000000 00000003]  
ev6__asn_aster__rsv1__v        = [00000000 00000002]  
ev6__asn_aster__rsv2__m        = [00000000 03FFFFFF]  
ev6__asn_aster__rsv2__s        = [00000000 0000000D]  
ev6__asn_aster__rsv2__v        = [00000000 0000001A]  
ev6__asn_aster__rsv3__m        = [00000000 0001FFFF]  
ev6__asn_aster__rsv3__s        = [00000000 0000002F]  
ev6__asn_aster__rsv3__v        = [00000000 00000011]  
ev6__asn_aster_astrr           = [00000000 00004710]  
ev6__asn_aster_astrr__asn__m   = [00000000 000000FF]  
ev6__asn_aster_astrr__asn__s   = [00000000 00000027]  
ev6__asn_aster_astrr__asn__v   = [00000000 00000008]  
ev6__asn_aster_astrr__aster__m = [00000000 0000000F]  
ev6__asn_aster_astrr__aster__s = [00000000 00000005]  
ev6__asn_aster_astrr__aster__v = [00000000 00000004]  
ev6__asn_aster_astrr__astrr__m = [00000000 0000000F]  
ev6__asn_aster_astrr__astrr__s = [00000000 00000009]  
ev6__asn_aster_astrr__astrr__v = [00000000 00000004]  
ev6__asn_aster_astrr__fpe__m   = [00000000 00000001]  
ev6__asn_aster_astrr__fpe__s   = [00000000 00000002]  
ev6__asn_aster_astrr__fpe__v   = [00000000 00000001]  
ev6__asn_aster_astrr__ppce__m  = [00000000 00000001]  
ev6__asn_aster_astrr__ppce__s  = [00000000 00000001]  
ev6__asn_aster_astrr__ppce__v  = [00000000 00000001]  
ev6__asn_aster_astrr__rsv0__m  = [00000000 00000001]  
ev6__asn_aster_astrr__rsv0__s  = [00000000 00000000]  
ev6__asn_aster_astrr__rsv0__v  = [00000000 00000001]  
ev6__asn_aster_astrr__rsv1__m  = [00000000 00000003]  
ev6__asn_aster_astrr__rsv1__s  = [00000000 00000003]  
ev6__asn_aster_astrr__rsv1__v  = [00000000 00000002]  
ev6__asn_aster_astrr__rsv2__m  = [00000000 03FFFFFF]  
ev6__asn_aster_astrr__rsv2__s  = [00000000 0000000D]  
ev6__asn_aster_astrr__rsv2__v  = [00000000 0000001A]  
ev6__asn_aster_astrr__rsv3__m  = [00000000 0001FFFF]  
ev6__asn_aster_astrr__rsv3__s  = [00000000 0000002F]  
ev6__asn_aster_astrr__rsv3__v  = [00000000 00000011]  
ev6__asn_aster_astrr_fpe       = [00000000 00005710]  
ev6__asn_aster_astrr_fpe__asn__m = [00000000 000000FF]  
ev6__asn_aster_astrr_fpe__asn__s = [00000000 00000027]  
ev6__asn_aster_astrr_fpe__asn__v = [00000000 00000008]  
ev6__asn_aster_astrr_fpe__aster__m = [00000000 0000000F]  
ev6__asn_aster_astrr_fpe__aster__s = [00000000 00000005]  
ev6__asn_aster_astrr_fpe__aster__v = [00000000 00000004]  
ev6__asn_aster_astrr_fpe__astrr__m = [00000000 0000000F]  
ev6__asn_aster_astrr_fpe__astrr__s = [00000000 00000009]  
ev6__asn_aster_astrr_fpe__astrr__v = [00000000 00000004]  
ev6__asn_aster_astrr_fpe__fpe__m = [00000000 00000001]  
ev6__asn_aster_astrr_fpe__fpe__s = [00000000 00000002]  
ev6__asn_aster_astrr_fpe__fpe__v = [00000000 00000001]  
ev6__asn_aster_astrr_fpe__ppce__m = [00000000 00000001]  
ev6__asn_aster_astrr_fpe__ppce__s = [00000000 00000001]  
ev6__asn_aster_astrr_fpe__ppce__v = [00000000 00000001]  
ev6__asn_aster_astrr_fpe__rsv0__m = [00000000 00000001]  
ev6__asn_aster_astrr_fpe__rsv0__s = [00000000 00000000]  
ev6__asn_aster_astrr_fpe__rsv0__v = [00000000 00000001]  
ev6__asn_aster_astrr_fpe__rsv1__m = [00000000 00000003]  
ev6__asn_aster_astrr_fpe__rsv1__s = [00000000 00000003]  
ev6__asn_aster_astrr_fpe__rsv1__v = [00000000 00000002]  
ev6__asn_aster_astrr_fpe__rsv2__m = [00000000 03FFFFFF]  
ev6__asn_aster_astrr_fpe__rsv2__s = [00000000 0000000D]  
ev6__asn_aster_astrr_fpe__rsv2__v = [00000000 0000001A]  
ev6__asn_aster_astrr_fpe__rsv3__m = [00000000 0001FFFF]  
ev6__asn_aster_astrr_fpe__rsv3__s = [00000000 0000002F]  
ev6__asn_aster_astrr_fpe__rsv3__v = [00000000 00000011]  
ev6__asn_aster_astrr_ppce      = [00000000 00004F10]  
ev6__asn_aster_astrr_ppce__asn__m = [00000000 000000FF]  
ev6__asn_aster_astrr_ppce__asn__s = [00000000 00000027]  
ev6__asn_aster_astrr_ppce__asn__v = [00000000 00000008]  
ev6__asn_aster_astrr_ppce__aster__m = [00000000 0000000F]  
ev6__asn_aster_astrr_ppce__aster__s = [00000000 00000005]  
ev6__asn_aster_astrr_ppce__aster__v = [00000000 00000004]  
ev6__asn_aster_astrr_ppce__astrr__m = [00000000 0000000F]  
ev6__asn_aster_astrr_ppce__astrr__s = [00000000 00000009]  
ev6__asn_aster_astrr_ppce__astrr__v = [00000000 00000004]  
ev6__asn_aster_astrr_ppce__fpe__m = [00000000 00000001]  
ev6__asn_aster_astrr_ppce__fpe__s = [00000000 00000002]  
ev6__asn_aster_astrr_ppce__fpe__v = [00000000 00000001]  
ev6__asn_aster_astrr_ppce__ppce__m = [00000000 00000001]  
ev6__asn_aster_astrr_ppce__ppce__s = [00000000 00000001]  
ev6__asn_aster_astrr_ppce__ppce__v = [00000000 00000001]  
ev6__asn_aster_astrr_ppce__rsv0__m = [00000000 00000001]  
ev6__asn_aster_astrr_ppce__rsv0__s = [00000000 00000000]  
ev6__asn_aster_astrr_ppce__rsv0__v = [00000000 00000001]  
ev6__asn_aster_astrr_ppce__rsv1__m = [00000000 00000003]  
ev6__asn_aster_astrr_ppce__rsv1__s = [00000000 00000003]  
ev6__asn_aster_astrr_ppce__rsv1__v = [00000000 00000002]  
ev6__asn_aster_astrr_ppce__rsv2__m = [00000000 03FFFFFF]  
ev6__asn_aster_astrr_ppce__rsv2__s = [00000000 0000000D]  
ev6__asn_aster_astrr_ppce__rsv2__v = [00000000 0000001A]  
ev6__asn_aster_astrr_ppce__rsv3__m = [00000000 0001FFFF]  
ev6__asn_aster_astrr_ppce__rsv3__s = [00000000 0000002F]  
ev6__asn_aster_astrr_ppce__rsv3__v = [00000000 00000011]  
ev6__asn_aster_fpe             = [00000000 00005310]  
ev6__asn_aster_fpe__asn__m     = [00000000 000000FF]  
ev6__asn_aster_fpe__asn__s     = [00000000 00000027]  
ev6__asn_aster_fpe__asn__v     = [00000000 00000008]  
ev6__asn_aster_fpe__aster__m   = [00000000 0000000F]  
ev6__asn_aster_fpe__aster__s   = [00000000 00000005]  
ev6__asn_aster_fpe__aster__v   = [00000000 00000004]  
ev6__asn_aster_fpe__astrr__m   = [00000000 0000000F]  
ev6__asn_aster_fpe__astrr__s   = [00000000 00000009]  
ev6__asn_aster_fpe__astrr__v   = [00000000 00000004]  
ev6__asn_aster_fpe__fpe__m     = [00000000 00000001]  
ev6__asn_aster_fpe__fpe__s     = [00000000 00000002]  
ev6__asn_aster_fpe__fpe__v     = [00000000 00000001]  
ev6__asn_aster_fpe__ppce__m    = [00000000 00000001]  
ev6__asn_aster_fpe__ppce__s    = [00000000 00000001]  
ev6__asn_aster_fpe__ppce__v    = [00000000 00000001]  
ev6__asn_aster_fpe__rsv0__m    = [00000000 00000001]  
ev6__asn_aster_fpe__rsv0__s    = [00000000 00000000]  
ev6__asn_aster_fpe__rsv0__v    = [00000000 00000001]  
ev6__asn_aster_fpe__rsv1__m    = [00000000 00000003]  
ev6__asn_aster_fpe__rsv1__s    = [00000000 00000003]  
ev6__asn_aster_fpe__rsv1__v    = [00000000 00000002]  
ev6__asn_aster_fpe__rsv2__m    = [00000000 03FFFFFF]  
ev6__asn_aster_fpe__rsv2__s    = [00000000 0000000D]  
ev6__asn_aster_fpe__rsv2__v    = [00000000 0000001A]  
ev6__asn_aster_fpe__rsv3__m    = [00000000 0001FFFF]  
ev6__asn_aster_fpe__rsv3__s    = [00000000 0000002F]  
ev6__asn_aster_fpe__rsv3__v    = [00000000 00000011]  
ev6__asn_aster_ppce            = [00000000 00004B10]  
ev6__asn_aster_ppce__asn__m    = [00000000 000000FF]  
ev6__asn_aster_ppce__asn__s    = [00000000 00000027]  
ev6__asn_aster_ppce__asn__v    = [00000000 00000008]  
ev6__asn_aster_ppce__aster__m  = [00000000 0000000F]  
ev6__asn_aster_ppce__aster__s  = [00000000 00000005]  
ev6__asn_aster_ppce__aster__v  = [00000000 00000004]  
ev6__asn_aster_ppce__astrr__m  = [00000000 0000000F]  
ev6__asn_aster_ppce__astrr__s  = [00000000 00000009]  
ev6__asn_aster_ppce__astrr__v  = [00000000 00000004]  
ev6__asn_aster_ppce__fpe__m    = [00000000 00000001]  
ev6__asn_aster_ppce__fpe__s    = [00000000 00000002]  
ev6__asn_aster_ppce__fpe__v    = [00000000 00000001]  
ev6__asn_aster_ppce__ppce__m   = [00000000 00000001]  
ev6__asn_aster_ppce__ppce__s   = [00000000 00000001]  
ev6__asn_aster_ppce__ppce__v   = [00000000 00000001]  
ev6__asn_aster_ppce__rsv0__m   = [00000000 00000001]  
ev6__asn_aster_ppce__rsv0__s   = [00000000 00000000]  
ev6__asn_aster_ppce__rsv0__v   = [00000000 00000001]  
ev6__asn_aster_ppce__rsv1__m   = [00000000 00000003]  
ev6__asn_aster_ppce__rsv1__s   = [00000000 00000003]  
ev6__asn_aster_ppce__rsv1__v   = [00000000 00000002]  
ev6__asn_aster_ppce__rsv2__m   = [00000000 03FFFFFF]  
ev6__asn_aster_ppce__rsv2__s   = [00000000 0000000D]  
ev6__asn_aster_ppce__rsv2__v   = [00000000 0000001A]  
ev6__asn_aster_ppce__rsv3__m   = [00000000 0001FFFF]  
ev6__asn_aster_ppce__rsv3__s   = [00000000 0000002F]  
ev6__asn_aster_ppce__rsv3__v   = [00000000 00000011]  
ev6__asn_aster_ppce_fpe        = [00000000 00005B10]  
ev6__asn_aster_ppce_fpe__asn__m = [00000000 000000FF]  
ev6__asn_aster_ppce_fpe__asn__s = [00000000 00000027]  
ev6__asn_aster_ppce_fpe__asn__v = [00000000 00000008]  
ev6__asn_aster_ppce_fpe__aster__m = [00000000 0000000F]  
ev6__asn_aster_ppce_fpe__aster__s = [00000000 00000005]  
ev6__asn_aster_ppce_fpe__aster__v = [00000000 00000004]  
ev6__asn_aster_ppce_fpe__astrr__m = [00000000 0000000F]  
ev6__asn_aster_ppce_fpe__astrr__s = [00000000 00000009]  
ev6__asn_aster_ppce_fpe__astrr__v = [00000000 00000004]  
ev6__asn_aster_ppce_fpe__fpe__m = [00000000 00000001]  
ev6__asn_aster_ppce_fpe__fpe__s = [00000000 00000002]  
ev6__asn_aster_ppce_fpe__fpe__v = [00000000 00000001]  
ev6__asn_aster_ppce_fpe__ppce__m = [00000000 00000001]  
ev6__asn_aster_ppce_fpe__ppce__s = [00000000 00000001]  
ev6__asn_aster_ppce_fpe__ppce__v = [00000000 00000001]  
ev6__asn_aster_ppce_fpe__rsv0__m = [00000000 00000001]  
ev6__asn_aster_ppce_fpe__rsv0__s = [00000000 00000000]  
ev6__asn_aster_ppce_fpe__rsv0__v = [00000000 00000001]  
ev6__asn_aster_ppce_fpe__rsv1__m = [00000000 00000003]  
ev6__asn_aster_ppce_fpe__rsv1__s = [00000000 00000003]  
ev6__asn_aster_ppce_fpe__rsv1__v = [00000000 00000002]  
ev6__asn_aster_ppce_fpe__rsv2__m = [00000000 03FFFFFF]  
ev6__asn_aster_ppce_fpe__rsv2__s = [00000000 0000000D]  
ev6__asn_aster_ppce_fpe__rsv2__v = [00000000 0000001A]  
ev6__asn_aster_ppce_fpe__rsv3__m = [00000000 0001FFFF]  
ev6__asn_aster_ppce_fpe__rsv3__s = [00000000 0000002F]  
ev6__asn_aster_ppce_fpe__rsv3__v = [00000000 00000011]  
ev6__asn_astrr                 = [00000000 00004510]  
ev6__asn_astrr__asn__m         = [00000000 000000FF]  
ev6__asn_astrr__asn__s         = [00000000 00000027]  
ev6__asn_astrr__asn__v         = [00000000 00000008]  
ev6__asn_astrr__aster__m       = [00000000 0000000F]  
ev6__asn_astrr__aster__s       = [00000000 00000005]  
ev6__asn_astrr__aster__v       = [00000000 00000004]  
ev6__asn_astrr__astrr__m       = [00000000 0000000F]  
ev6__asn_astrr__astrr__s       = [00000000 00000009]  
ev6__asn_astrr__astrr__v       = [00000000 00000004]  
ev6__asn_astrr__fpe__m         = [00000000 00000001]  
ev6__asn_astrr__fpe__s         = [00000000 00000002]  
ev6__asn_astrr__fpe__v         = [00000000 00000001]  
ev6__asn_astrr__ppce__m        = [00000000 00000001]  
ev6__asn_astrr__ppce__s        = [00000000 00000001]  
ev6__asn_astrr__ppce__v        = [00000000 00000001]  
ev6__asn_astrr__rsv0__m        = [00000000 00000001]  
ev6__asn_astrr__rsv0__s        = [00000000 00000000]  
ev6__asn_astrr__rsv0__v        = [00000000 00000001]  
ev6__asn_astrr__rsv1__m        = [00000000 00000003]  
ev6__asn_astrr__rsv1__s        = [00000000 00000003]  
ev6__asn_astrr__rsv1__v        = [00000000 00000002]  
ev6__asn_astrr__rsv2__m        = [00000000 03FFFFFF]  
ev6__asn_astrr__rsv2__s        = [00000000 0000000D]  
ev6__asn_astrr__rsv2__v        = [00000000 0000001A]  
ev6__asn_astrr__rsv3__m        = [00000000 0001FFFF]  
ev6__asn_astrr__rsv3__s        = [00000000 0000002F]  
ev6__asn_astrr__rsv3__v        = [00000000 00000011]  
ev6__asn_astrr_fpe             = [00000000 00005510]  
ev6__asn_astrr_fpe__asn__m     = [00000000 000000FF]  
ev6__asn_astrr_fpe__asn__s     = [00000000 00000027]  
ev6__asn_astrr_fpe__asn__v     = [00000000 00000008]  
ev6__asn_astrr_fpe__aster__m   = [00000000 0000000F]  
ev6__asn_astrr_fpe__aster__s   = [00000000 00000005]  
ev6__asn_astrr_fpe__aster__v   = [00000000 00000004]  
ev6__asn_astrr_fpe__astrr__m   = [00000000 0000000F]  
ev6__asn_astrr_fpe__astrr__s   = [00000000 00000009]  
ev6__asn_astrr_fpe__astrr__v   = [00000000 00000004]  
ev6__asn_astrr_fpe__fpe__m     = [00000000 00000001]  
ev6__asn_astrr_fpe__fpe__s     = [00000000 00000002]  
ev6__asn_astrr_fpe__fpe__v     = [00000000 00000001]  
ev6__asn_astrr_fpe__ppce__m    = [00000000 00000001]  
ev6__asn_astrr_fpe__ppce__s    = [00000000 00000001]  
ev6__asn_astrr_fpe__ppce__v    = [00000000 00000001]  
ev6__asn_astrr_fpe__rsv0__m    = [00000000 00000001]  
ev6__asn_astrr_fpe__rsv0__s    = [00000000 00000000]  
ev6__asn_astrr_fpe__rsv0__v    = [00000000 00000001]  
ev6__asn_astrr_fpe__rsv1__m    = [00000000 00000003]  
ev6__asn_astrr_fpe__rsv1__s    = [00000000 00000003]  
ev6__asn_astrr_fpe__rsv1__v    = [00000000 00000002]  
ev6__asn_astrr_fpe__rsv2__m    = [00000000 03FFFFFF]  
ev6__asn_astrr_fpe__rsv2__s    = [00000000 0000000D]  
ev6__asn_astrr_fpe__rsv2__v    = [00000000 0000001A]  
ev6__asn_astrr_fpe__rsv3__m    = [00000000 0001FFFF]  
ev6__asn_astrr_fpe__rsv3__s    = [00000000 0000002F]  
ev6__asn_astrr_fpe__rsv3__v    = [00000000 00000011]  
ev6__asn_astrr_ppce            = [00000000 00004D10]  
ev6__asn_astrr_ppce__asn__m    = [00000000 000000FF]  
ev6__asn_astrr_ppce__asn__s    = [00000000 00000027]  
ev6__asn_astrr_ppce__asn__v    = [00000000 00000008]  
ev6__asn_astrr_ppce__aster__m  = [00000000 0000000F]  
ev6__asn_astrr_ppce__aster__s  = [00000000 00000005]  
ev6__asn_astrr_ppce__aster__v  = [00000000 00000004]  
ev6__asn_astrr_ppce__astrr__m  = [00000000 0000000F]  
ev6__asn_astrr_ppce__astrr__s  = [00000000 00000009]  
ev6__asn_astrr_ppce__astrr__v  = [00000000 00000004]  
ev6__asn_astrr_ppce__fpe__m    = [00000000 00000001]  
ev6__asn_astrr_ppce__fpe__s    = [00000000 00000002]  
ev6__asn_astrr_ppce__fpe__v    = [00000000 00000001]  
ev6__asn_astrr_ppce__ppce__m   = [00000000 00000001]  
ev6__asn_astrr_ppce__ppce__s   = [00000000 00000001]  
ev6__asn_astrr_ppce__ppce__v   = [00000000 00000001]  
ev6__asn_astrr_ppce__rsv0__m   = [00000000 00000001]  
ev6__asn_astrr_ppce__rsv0__s   = [00000000 00000000]  
ev6__asn_astrr_ppce__rsv0__v   = [00000000 00000001]  
ev6__asn_astrr_ppce__rsv1__m   = [00000000 00000003]  
ev6__asn_astrr_ppce__rsv1__s   = [00000000 00000003]  
ev6__asn_astrr_ppce__rsv1__v   = [00000000 00000002]  
ev6__asn_astrr_ppce__rsv2__m   = [00000000 03FFFFFF]  
ev6__asn_astrr_ppce__rsv2__s   = [00000000 0000000D]  
ev6__asn_astrr_ppce__rsv2__v   = [00000000 0000001A]  
ev6__asn_astrr_ppce__rsv3__m   = [00000000 0001FFFF]  
ev6__asn_astrr_ppce__rsv3__s   = [00000000 0000002F]  
ev6__asn_astrr_ppce__rsv3__v   = [00000000 00000011]  
ev6__asn_astrr_ppce_fpe        = [00000000 00005D10]  
ev6__asn_astrr_ppce_fpe__asn__m = [00000000 000000FF]  
ev6__asn_astrr_ppce_fpe__asn__s = [00000000 00000027]  
ev6__asn_astrr_ppce_fpe__asn__v = [00000000 00000008]  
ev6__asn_astrr_ppce_fpe__aster__m = [00000000 0000000F]  
ev6__asn_astrr_ppce_fpe__aster__s = [00000000 00000005]  
ev6__asn_astrr_ppce_fpe__aster__v = [00000000 00000004]  
ev6__asn_astrr_ppce_fpe__astrr__m = [00000000 0000000F]  
ev6__asn_astrr_ppce_fpe__astrr__s = [00000000 00000009]  
ev6__asn_astrr_ppce_fpe__astrr__v = [00000000 00000004]  
ev6__asn_astrr_ppce_fpe__fpe__m = [00000000 00000001]  
ev6__asn_astrr_ppce_fpe__fpe__s = [00000000 00000002]  
ev6__asn_astrr_ppce_fpe__fpe__v = [00000000 00000001]  
ev6__asn_astrr_ppce_fpe__ppce__m = [00000000 00000001]  
ev6__asn_astrr_ppce_fpe__ppce__s = [00000000 00000001]  
ev6__asn_astrr_ppce_fpe__ppce__v = [00000000 00000001]  
ev6__asn_astrr_ppce_fpe__rsv0__m = [00000000 00000001]  
ev6__asn_astrr_ppce_fpe__rsv0__s = [00000000 00000000]  
ev6__asn_astrr_ppce_fpe__rsv0__v = [00000000 00000001]  
ev6__asn_astrr_ppce_fpe__rsv1__m = [00000000 00000003]  
ev6__asn_astrr_ppce_fpe__rsv1__s = [00000000 00000003]  
ev6__asn_astrr_ppce_fpe__rsv1__v = [00000000 00000002]  
ev6__asn_astrr_ppce_fpe__rsv2__m = [00000000 03FFFFFF]  
ev6__asn_astrr_ppce_fpe__rsv2__s = [00000000 0000000D]  
ev6__asn_astrr_ppce_fpe__rsv2__v = [00000000 0000001A]  
ev6__asn_astrr_ppce_fpe__rsv3__m = [00000000 0001FFFF]  
ev6__asn_astrr_ppce_fpe__rsv3__s = [00000000 0000002F]  
ev6__asn_astrr_ppce_fpe__rsv3__v = [00000000 00000011]  
ev6__asn_fpe                   = [00000000 00005110]  
ev6__asn_fpe__asn__m           = [00000000 000000FF]  
ev6__asn_fpe__asn__s           = [00000000 00000027]  
ev6__asn_fpe__asn__v           = [00000000 00000008]  
ev6__asn_fpe__aster__m         = [00000000 0000000F]  
ev6__asn_fpe__aster__s         = [00000000 00000005]  
ev6__asn_fpe__aster__v         = [00000000 00000004]  
ev6__asn_fpe__astrr__m         = [00000000 0000000F]  
ev6__asn_fpe__astrr__s         = [00000000 00000009]  
ev6__asn_fpe__astrr__v         = [00000000 00000004]  
ev6__asn_fpe__fpe__m           = [00000000 00000001]  
ev6__asn_fpe__fpe__s           = [00000000 00000002]  
ev6__asn_fpe__fpe__v           = [00000000 00000001]  
ev6__asn_fpe__ppce__m          = [00000000 00000001]  
ev6__asn_fpe__ppce__s          = [00000000 00000001]  
ev6__asn_fpe__ppce__v          = [00000000 00000001]  
ev6__asn_fpe__rsv0__m          = [00000000 00000001]  
ev6__asn_fpe__rsv0__s          = [00000000 00000000]  
ev6__asn_fpe__rsv0__v          = [00000000 00000001]  
ev6__asn_fpe__rsv1__m          = [00000000 00000003]  
ev6__asn_fpe__rsv1__s          = [00000000 00000003]  
ev6__asn_fpe__rsv1__v          = [00000000 00000002]  
ev6__asn_fpe__rsv2__m          = [00000000 03FFFFFF]  
ev6__asn_fpe__rsv2__s          = [00000000 0000000D]  
ev6__asn_fpe__rsv2__v          = [00000000 0000001A]  
ev6__asn_fpe__rsv3__m          = [00000000 0001FFFF]  
ev6__asn_fpe__rsv3__s          = [00000000 0000002F]  
ev6__asn_fpe__rsv3__v          = [00000000 00000011]  
ev6__asn_ppce                  = [00000000 00004910]  
ev6__asn_ppce__asn__m          = [00000000 000000FF]  
ev6__asn_ppce__asn__s          = [00000000 00000027]  
ev6__asn_ppce__asn__v          = [00000000 00000008]  
ev6__asn_ppce__aster__m        = [00000000 0000000F]  
ev6__asn_ppce__aster__s        = [00000000 00000005]  
ev6__asn_ppce__aster__v        = [00000000 00000004]  
ev6__asn_ppce__astrr__m        = [00000000 0000000F]  
ev6__asn_ppce__astrr__s        = [00000000 00000009]  
ev6__asn_ppce__astrr__v        = [00000000 00000004]  
ev6__asn_ppce__fpe__m          = [00000000 00000001]  
ev6__asn_ppce__fpe__s          = [00000000 00000002]  
ev6__asn_ppce__fpe__v          = [00000000 00000001]  
ev6__asn_ppce__ppce__m         = [00000000 00000001]  
ev6__asn_ppce__ppce__s         = [00000000 00000001]  
ev6__asn_ppce__ppce__v         = [00000000 00000001]  
ev6__asn_ppce__rsv0__m         = [00000000 00000001]  
ev6__asn_ppce__rsv0__s         = [00000000 00000000]  
ev6__asn_ppce__rsv0__v         = [00000000 00000001]  
ev6__asn_ppce__rsv1__m         = [00000000 00000003]  
ev6__asn_ppce__rsv1__s         = [00000000 00000003]  
ev6__asn_ppce__rsv1__v         = [00000000 00000002]  
ev6__asn_ppce__rsv2__m         = [00000000 03FFFFFF]  
ev6__asn_ppce__rsv2__s         = [00000000 0000000D]  
ev6__asn_ppce__rsv2__v         = [00000000 0000001A]  
ev6__asn_ppce__rsv3__m         = [00000000 0001FFFF]  
ev6__asn_ppce__rsv3__s         = [00000000 0000002F]  
ev6__asn_ppce__rsv3__v         = [00000000 00000011]  
ev6__asn_ppce_fpe              = [00000000 00005910]  
ev6__asn_ppce_fpe__asn__m      = [00000000 000000FF]  
ev6__asn_ppce_fpe__asn__s      = [00000000 00000027]  
ev6__asn_ppce_fpe__asn__v      = [00000000 00000008]  
ev6__asn_ppce_fpe__aster__m    = [00000000 0000000F]  
ev6__asn_ppce_fpe__aster__s    = [00000000 00000005]  
ev6__asn_ppce_fpe__aster__v    = [00000000 00000004]  
ev6__asn_ppce_fpe__astrr__m    = [00000000 0000000F]  
ev6__asn_ppce_fpe__astrr__s    = [00000000 00000009]  
ev6__asn_ppce_fpe__astrr__v    = [00000000 00000004]  
ev6__asn_ppce_fpe__fpe__m      = [00000000 00000001]  
ev6__asn_ppce_fpe__fpe__s      = [00000000 00000002]  
ev6__asn_ppce_fpe__fpe__v      = [00000000 00000001]  
ev6__asn_ppce_fpe__ppce__m     = [00000000 00000001]  
ev6__asn_ppce_fpe__ppce__s     = [00000000 00000001]  
ev6__asn_ppce_fpe__ppce__v     = [00000000 00000001]  
ev6__asn_ppce_fpe__rsv0__m     = [00000000 00000001]  
ev6__asn_ppce_fpe__rsv0__s     = [00000000 00000000]  
ev6__asn_ppce_fpe__rsv0__v     = [00000000 00000001]  
ev6__asn_ppce_fpe__rsv1__m     = [00000000 00000003]  
ev6__asn_ppce_fpe__rsv1__s     = [00000000 00000003]  
ev6__asn_ppce_fpe__rsv1__v     = [00000000 00000002]  
ev6__asn_ppce_fpe__rsv2__m     = [00000000 03FFFFFF]  
ev6__asn_ppce_fpe__rsv2__s     = [00000000 0000000D]  
ev6__asn_ppce_fpe__rsv2__v     = [00000000 0000001A]  
ev6__asn_ppce_fpe__rsv3__m     = [00000000 0001FFFF]  
ev6__asn_ppce_fpe__rsv3__s     = [00000000 0000002F]  
ev6__asn_ppce_fpe__rsv3__v     = [00000000 00000011]  
ev6__aster                     = [00000000 00004210]  
ev6__aster__asn__m             = [00000000 000000FF]  
ev6__aster__asn__s             = [00000000 00000027]  
ev6__aster__asn__v             = [00000000 00000008]  
ev6__aster__aster__m           = [00000000 0000000F]  
ev6__aster__aster__s           = [00000000 00000005]  
ev6__aster__aster__v           = [00000000 00000004]  
ev6__aster__astrr__m           = [00000000 0000000F]  
ev6__aster__astrr__s           = [00000000 00000009]  
ev6__aster__astrr__v           = [00000000 00000004]  
ev6__aster__fpe__m             = [00000000 00000001]  
ev6__aster__fpe__s             = [00000000 00000002]  
ev6__aster__fpe__v             = [00000000 00000001]  
ev6__aster__ppce__m            = [00000000 00000001]  
ev6__aster__ppce__s            = [00000000 00000001]  
ev6__aster__ppce__v            = [00000000 00000001]  
ev6__aster__rsv0__m            = [00000000 00000001]  
ev6__aster__rsv0__s            = [00000000 00000000]  
ev6__aster__rsv0__v            = [00000000 00000001]  
ev6__aster__rsv1__m            = [00000000 00000003]  
ev6__aster__rsv1__s            = [00000000 00000003]  
ev6__aster__rsv1__v            = [00000000 00000002]  
ev6__aster__rsv2__m            = [00000000 03FFFFFF]  
ev6__aster__rsv2__s            = [00000000 0000000D]  
ev6__aster__rsv2__v            = [00000000 0000001A]  
ev6__aster__rsv3__m            = [00000000 0001FFFF]  
ev6__aster__rsv3__s            = [00000000 0000002F]  
ev6__aster__rsv3__v            = [00000000 00000011]  
ev6__aster_astrr               = [00000000 00004610]  
ev6__aster_astrr__asn__m       = [00000000 000000FF]  
ev6__aster_astrr__asn__s       = [00000000 00000027]  
ev6__aster_astrr__asn__v       = [00000000 00000008]  
ev6__aster_astrr__aster__m     = [00000000 0000000F]  
ev6__aster_astrr__aster__s     = [00000000 00000005]  
ev6__aster_astrr__aster__v     = [00000000 00000004]  
ev6__aster_astrr__astrr__m     = [00000000 0000000F]  
ev6__aster_astrr__astrr__s     = [00000000 00000009]  
ev6__aster_astrr__astrr__v     = [00000000 00000004]  
ev6__aster_astrr__fpe__m       = [00000000 00000001]  
ev6__aster_astrr__fpe__s       = [00000000 00000002]  
ev6__aster_astrr__fpe__v       = [00000000 00000001]  
ev6__aster_astrr__ppce__m      = [00000000 00000001]  
ev6__aster_astrr__ppce__s      = [00000000 00000001]  
ev6__aster_astrr__ppce__v      = [00000000 00000001]  
ev6__aster_astrr__rsv0__m      = [00000000 00000001]  
ev6__aster_astrr__rsv0__s      = [00000000 00000000]  
ev6__aster_astrr__rsv0__v      = [00000000 00000001]  
ev6__aster_astrr__rsv1__m      = [00000000 00000003]  
ev6__aster_astrr__rsv1__s      = [00000000 00000003]  
ev6__aster_astrr__rsv1__v      = [00000000 00000002]  
ev6__aster_astrr__rsv2__m      = [00000000 03FFFFFF]  
ev6__aster_astrr__rsv2__s      = [00000000 0000000D]  
ev6__aster_astrr__rsv2__v      = [00000000 0000001A]  
ev6__aster_astrr__rsv3__m      = [00000000 0001FFFF]  
ev6__aster_astrr__rsv3__s      = [00000000 0000002F]  
ev6__aster_astrr__rsv3__v      = [00000000 00000011]  
ev6__aster_astrr_fpe           = [00000000 00005610]  
ev6__aster_astrr_fpe__asn__m   = [00000000 000000FF]  
ev6__aster_astrr_fpe__asn__s   = [00000000 00000027]  
ev6__aster_astrr_fpe__asn__v   = [00000000 00000008]  
ev6__aster_astrr_fpe__aster__m = [00000000 0000000F]  
ev6__aster_astrr_fpe__aster__s = [00000000 00000005]  
ev6__aster_astrr_fpe__aster__v = [00000000 00000004]  
ev6__aster_astrr_fpe__astrr__m = [00000000 0000000F]  
ev6__aster_astrr_fpe__astrr__s = [00000000 00000009]  
ev6__aster_astrr_fpe__astrr__v = [00000000 00000004]  
ev6__aster_astrr_fpe__fpe__m   = [00000000 00000001]  
ev6__aster_astrr_fpe__fpe__s   = [00000000 00000002]  
ev6__aster_astrr_fpe__fpe__v   = [00000000 00000001]  
ev6__aster_astrr_fpe__ppce__m  = [00000000 00000001]  
ev6__aster_astrr_fpe__ppce__s  = [00000000 00000001]  
ev6__aster_astrr_fpe__ppce__v  = [00000000 00000001]  
ev6__aster_astrr_fpe__rsv0__m  = [00000000 00000001]  
ev6__aster_astrr_fpe__rsv0__s  = [00000000 00000000]  
ev6__aster_astrr_fpe__rsv0__v  = [00000000 00000001]  
ev6__aster_astrr_fpe__rsv1__m  = [00000000 00000003]  
ev6__aster_astrr_fpe__rsv1__s  = [00000000 00000003]  
ev6__aster_astrr_fpe__rsv1__v  = [00000000 00000002]  
ev6__aster_astrr_fpe__rsv2__m  = [00000000 03FFFFFF]  
ev6__aster_astrr_fpe__rsv2__s  = [00000000 0000000D]  
ev6__aster_astrr_fpe__rsv2__v  = [00000000 0000001A]  
ev6__aster_astrr_fpe__rsv3__m  = [00000000 0001FFFF]  
ev6__aster_astrr_fpe__rsv3__s  = [00000000 0000002F]  
ev6__aster_astrr_fpe__rsv3__v  = [00000000 00000011]  
ev6__aster_astrr_ppce          = [00000000 00004E10]  
ev6__aster_astrr_ppce__asn__m  = [00000000 000000FF]  
ev6__aster_astrr_ppce__asn__s  = [00000000 00000027]  
ev6__aster_astrr_ppce__asn__v  = [00000000 00000008]  
ev6__aster_astrr_ppce__aster__m = [00000000 0000000F]  
ev6__aster_astrr_ppce__aster__s = [00000000 00000005]  
ev6__aster_astrr_ppce__aster__v = [00000000 00000004]  
ev6__aster_astrr_ppce__astrr__m = [00000000 0000000F]  
ev6__aster_astrr_ppce__astrr__s = [00000000 00000009]  
ev6__aster_astrr_ppce__astrr__v = [00000000 00000004]  
ev6__aster_astrr_ppce__fpe__m  = [00000000 00000001]  
ev6__aster_astrr_ppce__fpe__s  = [00000000 00000002]  
ev6__aster_astrr_ppce__fpe__v  = [00000000 00000001]  
ev6__aster_astrr_ppce__ppce__m = [00000000 00000001]  
ev6__aster_astrr_ppce__ppce__s = [00000000 00000001]  
ev6__aster_astrr_ppce__ppce__v = [00000000 00000001]  
ev6__aster_astrr_ppce__rsv0__m = [00000000 00000001]  
ev6__aster_astrr_ppce__rsv0__s = [00000000 00000000]  
ev6__aster_astrr_ppce__rsv0__v = [00000000 00000001]  
ev6__aster_astrr_ppce__rsv1__m = [00000000 00000003]  
ev6__aster_astrr_ppce__rsv1__s = [00000000 00000003]  
ev6__aster_astrr_ppce__rsv1__v = [00000000 00000002]  
ev6__aster_astrr_ppce__rsv2__m = [00000000 03FFFFFF]  
ev6__aster_astrr_ppce__rsv2__s = [00000000 0000000D]  
ev6__aster_astrr_ppce__rsv2__v = [00000000 0000001A]  
ev6__aster_astrr_ppce__rsv3__m = [00000000 0001FFFF]  
ev6__aster_astrr_ppce__rsv3__s = [00000000 0000002F]  
ev6__aster_astrr_ppce__rsv3__v = [00000000 00000011]  
ev6__aster_astrr_ppce_fpe      = [00000000 00005E10]  
ev6__aster_astrr_ppce_fpe__asn__m = [00000000 000000FF]  
ev6__aster_astrr_ppce_fpe__asn__s = [00000000 00000027]  
ev6__aster_astrr_ppce_fpe__asn__v = [00000000 00000008]  
ev6__aster_astrr_ppce_fpe__aster__m = [00000000 0000000F]  
ev6__aster_astrr_ppce_fpe__aster__s = [00000000 00000005]  
ev6__aster_astrr_ppce_fpe__aster__v = [00000000 00000004]  
ev6__aster_astrr_ppce_fpe__astrr__m = [00000000 0000000F]  
ev6__aster_astrr_ppce_fpe__astrr__s = [00000000 00000009]  
ev6__aster_astrr_ppce_fpe__astrr__v = [00000000 00000004]  
ev6__aster_astrr_ppce_fpe__fpe__m = [00000000 00000001]  
ev6__aster_astrr_ppce_fpe__fpe__s = [00000000 00000002]  
ev6__aster_astrr_ppce_fpe__fpe__v = [00000000 00000001]  
ev6__aster_astrr_ppce_fpe__ppce__m = [00000000 00000001]  
ev6__aster_astrr_ppce_fpe__ppce__s = [00000000 00000001]  
ev6__aster_astrr_ppce_fpe__ppce__v = [00000000 00000001]  
ev6__aster_astrr_ppce_fpe__rsv0__m = [00000000 00000001]  
ev6__aster_astrr_ppce_fpe__rsv0__s = [00000000 00000000]  
ev6__aster_astrr_ppce_fpe__rsv0__v = [00000000 00000001]  
ev6__aster_astrr_ppce_fpe__rsv1__m = [00000000 00000003]  
ev6__aster_astrr_ppce_fpe__rsv1__s = [00000000 00000003]  
ev6__aster_astrr_ppce_fpe__rsv1__v = [00000000 00000002]  
ev6__aster_astrr_ppce_fpe__rsv2__m = [00000000 03FFFFFF]  
ev6__aster_astrr_ppce_fpe__rsv2__s = [00000000 0000000D]  
ev6__aster_astrr_ppce_fpe__rsv2__v = [00000000 0000001A]  
ev6__aster_astrr_ppce_fpe__rsv3__m = [00000000 0001FFFF]  
ev6__aster_astrr_ppce_fpe__rsv3__s = [00000000 0000002F]  
ev6__aster_astrr_ppce_fpe__rsv3__v = [00000000 00000011]  
ev6__aster_fpe                 = [00000000 00005210]  
ev6__aster_fpe__asn__m         = [00000000 000000FF]  
ev6__aster_fpe__asn__s         = [00000000 00000027]  
ev6__aster_fpe__asn__v         = [00000000 00000008]  
ev6__aster_fpe__aster__m       = [00000000 0000000F]  
ev6__aster_fpe__aster__s       = [00000000 00000005]  
ev6__aster_fpe__aster__v       = [00000000 00000004]  
ev6__aster_fpe__astrr__m       = [00000000 0000000F]  
ev6__aster_fpe__astrr__s       = [00000000 00000009]  
ev6__aster_fpe__astrr__v       = [00000000 00000004]  
ev6__aster_fpe__fpe__m         = [00000000 00000001]  
ev6__aster_fpe__fpe__s         = [00000000 00000002]  
ev6__aster_fpe__fpe__v         = [00000000 00000001]  
ev6__aster_fpe__ppce__m        = [00000000 00000001]  
ev6__aster_fpe__ppce__s        = [00000000 00000001]  
ev6__aster_fpe__ppce__v        = [00000000 00000001]  
ev6__aster_fpe__rsv0__m        = [00000000 00000001]  
ev6__aster_fpe__rsv0__s        = [00000000 00000000]  
ev6__aster_fpe__rsv0__v        = [00000000 00000001]  
ev6__aster_fpe__rsv1__m        = [00000000 00000003]  
ev6__aster_fpe__rsv1__s        = [00000000 00000003]  
ev6__aster_fpe__rsv1__v        = [00000000 00000002]  
ev6__aster_fpe__rsv2__m        = [00000000 03FFFFFF]  
ev6__aster_fpe__rsv2__s        = [00000000 0000000D]  
ev6__aster_fpe__rsv2__v        = [00000000 0000001A]  
ev6__aster_fpe__rsv3__m        = [00000000 0001FFFF]  
ev6__aster_fpe__rsv3__s        = [00000000 0000002F]  
ev6__aster_fpe__rsv3__v        = [00000000 00000011]  
ev6__aster_ppce                = [00000000 00004A10]  
ev6__aster_ppce__asn__m        = [00000000 000000FF]  
ev6__aster_ppce__asn__s        = [00000000 00000027]  
ev6__aster_ppce__asn__v        = [00000000 00000008]  
ev6__aster_ppce__aster__m      = [00000000 0000000F]  
ev6__aster_ppce__aster__s      = [00000000 00000005]  
ev6__aster_ppce__aster__v      = [00000000 00000004]  
ev6__aster_ppce__astrr__m      = [00000000 0000000F]  
ev6__aster_ppce__astrr__s      = [00000000 00000009]  
ev6__aster_ppce__astrr__v      = [00000000 00000004]  
ev6__aster_ppce__fpe__m        = [00000000 00000001]  
ev6__aster_ppce__fpe__s        = [00000000 00000002]  
ev6__aster_ppce__fpe__v        = [00000000 00000001]  
ev6__aster_ppce__ppce__m       = [00000000 00000001]  
ev6__aster_ppce__ppce__s       = [00000000 00000001]  
ev6__aster_ppce__ppce__v       = [00000000 00000001]  
ev6__aster_ppce__rsv0__m       = [00000000 00000001]  
ev6__aster_ppce__rsv0__s       = [00000000 00000000]  
ev6__aster_ppce__rsv0__v       = [00000000 00000001]  
ev6__aster_ppce__rsv1__m       = [00000000 00000003]  
ev6__aster_ppce__rsv1__s       = [00000000 00000003]  
ev6__aster_ppce__rsv1__v       = [00000000 00000002]  
ev6__aster_ppce__rsv2__m       = [00000000 03FFFFFF]  
ev6__aster_ppce__rsv2__s       = [00000000 0000000D]  
ev6__aster_ppce__rsv2__v       = [00000000 0000001A]  
ev6__aster_ppce__rsv3__m       = [00000000 0001FFFF]  
ev6__aster_ppce__rsv3__s       = [00000000 0000002F]  
ev6__aster_ppce__rsv3__v       = [00000000 00000011]  
ev6__aster_ppce_fpe            = [00000000 00005A10]  
ev6__aster_ppce_fpe__asn__m    = [00000000 000000FF]  
ev6__aster_ppce_fpe__asn__s    = [00000000 00000027]  
ev6__aster_ppce_fpe__asn__v    = [00000000 00000008]  
ev6__aster_ppce_fpe__aster__m  = [00000000 0000000F]  
ev6__aster_ppce_fpe__aster__s  = [00000000 00000005]  
ev6__aster_ppce_fpe__aster__v  = [00000000 00000004]  
ev6__aster_ppce_fpe__astrr__m  = [00000000 0000000F]  
ev6__aster_ppce_fpe__astrr__s  = [00000000 00000009]  
ev6__aster_ppce_fpe__astrr__v  = [00000000 00000004]  
ev6__aster_ppce_fpe__fpe__m    = [00000000 00000001]  
ev6__aster_ppce_fpe__fpe__s    = [00000000 00000002]  
ev6__aster_ppce_fpe__fpe__v    = [00000000 00000001]  
ev6__aster_ppce_fpe__ppce__m   = [00000000 00000001]  
ev6__aster_ppce_fpe__ppce__s   = [00000000 00000001]  
ev6__aster_ppce_fpe__ppce__v   = [00000000 00000001]  
ev6__aster_ppce_fpe__rsv0__m   = [00000000 00000001]  
ev6__aster_ppce_fpe__rsv0__s   = [00000000 00000000]  
ev6__aster_ppce_fpe__rsv0__v   = [00000000 00000001]  
ev6__aster_ppce_fpe__rsv1__m   = [00000000 00000003]  
ev6__aster_ppce_fpe__rsv1__s   = [00000000 00000003]  
ev6__aster_ppce_fpe__rsv1__v   = [00000000 00000002]  
ev6__aster_ppce_fpe__rsv2__m   = [00000000 03FFFFFF]  
ev6__aster_ppce_fpe__rsv2__s   = [00000000 0000000D]  
ev6__aster_ppce_fpe__rsv2__v   = [00000000 0000001A]  
ev6__aster_ppce_fpe__rsv3__m   = [00000000 0001FFFF]  
ev6__aster_ppce_fpe__rsv3__s   = [00000000 0000002F]  
ev6__aster_ppce_fpe__rsv3__v   = [00000000 00000011]  
ev6__astrr                     = [00000000 00004410]  
ev6__astrr__asn__m             = [00000000 000000FF]  
ev6__astrr__asn__s             = [00000000 00000027]  
ev6__astrr__asn__v             = [00000000 00000008]  
ev6__astrr__aster__m           = [00000000 0000000F]  
ev6__astrr__aster__s           = [00000000 00000005]  
ev6__astrr__aster__v           = [00000000 00000004]  
ev6__astrr__astrr__m           = [00000000 0000000F]  
ev6__astrr__astrr__s           = [00000000 00000009]  
ev6__astrr__astrr__v           = [00000000 00000004]  
ev6__astrr__fpe__m             = [00000000 00000001]  
ev6__astrr__fpe__s             = [00000000 00000002]  
ev6__astrr__fpe__v             = [00000000 00000001]  
ev6__astrr__ppce__m            = [00000000 00000001]  
ev6__astrr__ppce__s            = [00000000 00000001]  
ev6__astrr__ppce__v            = [00000000 00000001]  
ev6__astrr__rsv0__m            = [00000000 00000001]  
ev6__astrr__rsv0__s            = [00000000 00000000]  
ev6__astrr__rsv0__v            = [00000000 00000001]  
ev6__astrr__rsv1__m            = [00000000 00000003]  
ev6__astrr__rsv1__s            = [00000000 00000003]  
ev6__astrr__rsv1__v            = [00000000 00000002]  
ev6__astrr__rsv2__m            = [00000000 03FFFFFF]  
ev6__astrr__rsv2__s            = [00000000 0000000D]  
ev6__astrr__rsv2__v            = [00000000 0000001A]  
ev6__astrr__rsv3__m            = [00000000 0001FFFF]  
ev6__astrr__rsv3__s            = [00000000 0000002F]  
ev6__astrr__rsv3__v            = [00000000 00000011]  
ev6__astrr_fpe                 = [00000000 00005410]  
ev6__astrr_fpe__asn__m         = [00000000 000000FF]  
ev6__astrr_fpe__asn__s         = [00000000 00000027]  
ev6__astrr_fpe__asn__v         = [00000000 00000008]  
ev6__astrr_fpe__aster__m       = [00000000 0000000F]  
ev6__astrr_fpe__aster__s       = [00000000 00000005]  
ev6__astrr_fpe__aster__v       = [00000000 00000004]  
ev6__astrr_fpe__astrr__m       = [00000000 0000000F]  
ev6__astrr_fpe__astrr__s       = [00000000 00000009]  
ev6__astrr_fpe__astrr__v       = [00000000 00000004]  
ev6__astrr_fpe__fpe__m         = [00000000 00000001]  
ev6__astrr_fpe__fpe__s         = [00000000 00000002]  
ev6__astrr_fpe__fpe__v         = [00000000 00000001]  
ev6__astrr_fpe__ppce__m        = [00000000 00000001]  
ev6__astrr_fpe__ppce__s        = [00000000 00000001]  
ev6__astrr_fpe__ppce__v        = [00000000 00000001]  
ev6__astrr_fpe__rsv0__m        = [00000000 00000001]  
ev6__astrr_fpe__rsv0__s        = [00000000 00000000]  
ev6__astrr_fpe__rsv0__v        = [00000000 00000001]  
ev6__astrr_fpe__rsv1__m        = [00000000 00000003]  
ev6__astrr_fpe__rsv1__s        = [00000000 00000003]  
ev6__astrr_fpe__rsv1__v        = [00000000 00000002]  
ev6__astrr_fpe__rsv2__m        = [00000000 03FFFFFF]  
ev6__astrr_fpe__rsv2__s        = [00000000 0000000D]  
ev6__astrr_fpe__rsv2__v        = [00000000 0000001A]  
ev6__astrr_fpe__rsv3__m        = [00000000 0001FFFF]  
ev6__astrr_fpe__rsv3__s        = [00000000 0000002F]  
ev6__astrr_fpe__rsv3__v        = [00000000 00000011]  
ev6__astrr_ppce                = [00000000 00004C10]  
ev6__astrr_ppce__asn__m        = [00000000 000000FF]  
ev6__astrr_ppce__asn__s        = [00000000 00000027]  
ev6__astrr_ppce__asn__v        = [00000000 00000008]  
ev6__astrr_ppce__aster__m      = [00000000 0000000F]  
ev6__astrr_ppce__aster__s      = [00000000 00000005]  
ev6__astrr_ppce__aster__v      = [00000000 00000004]  
ev6__astrr_ppce__astrr__m      = [00000000 0000000F]  
ev6__astrr_ppce__astrr__s      = [00000000 00000009]  
ev6__astrr_ppce__astrr__v      = [00000000 00000004]  
ev6__astrr_ppce__fpe__m        = [00000000 00000001]  
ev6__astrr_ppce__fpe__s        = [00000000 00000002]  
ev6__astrr_ppce__fpe__v        = [00000000 00000001]  
ev6__astrr_ppce__ppce__m       = [00000000 00000001]  
ev6__astrr_ppce__ppce__s       = [00000000 00000001]  
ev6__astrr_ppce__ppce__v       = [00000000 00000001]  
ev6__astrr_ppce__rsv0__m       = [00000000 00000001]  
ev6__astrr_ppce__rsv0__s       = [00000000 00000000]  
ev6__astrr_ppce__rsv0__v       = [00000000 00000001]  
ev6__astrr_ppce__rsv1__m       = [00000000 00000003]  
ev6__astrr_ppce__rsv1__s       = [00000000 00000003]  
ev6__astrr_ppce__rsv1__v       = [00000000 00000002]  
ev6__astrr_ppce__rsv2__m       = [00000000 03FFFFFF]  
ev6__astrr_ppce__rsv2__s       = [00000000 0000000D]  
ev6__astrr_ppce__rsv2__v       = [00000000 0000001A]  
ev6__astrr_ppce__rsv3__m       = [00000000 0001FFFF]  
ev6__astrr_ppce__rsv3__s       = [00000000 0000002F]  
ev6__astrr_ppce__rsv3__v       = [00000000 00000011]  
ev6__astrr_ppce_fpe            = [00000000 00005C10]  
ev6__astrr_ppce_fpe__asn__m    = [00000000 000000FF]  
ev6__astrr_ppce_fpe__asn__s    = [00000000 00000027]  
ev6__astrr_ppce_fpe__asn__v    = [00000000 00000008]  
ev6__astrr_ppce_fpe__aster__m  = [00000000 0000000F]  
ev6__astrr_ppce_fpe__aster__s  = [00000000 00000005]  
ev6__astrr_ppce_fpe__aster__v  = [00000000 00000004]  
ev6__astrr_ppce_fpe__astrr__m  = [00000000 0000000F]  
ev6__astrr_ppce_fpe__astrr__s  = [00000000 00000009]  
ev6__astrr_ppce_fpe__astrr__v  = [00000000 00000004]  
ev6__astrr_ppce_fpe__fpe__m    = [00000000 00000001]  
ev6__astrr_ppce_fpe__fpe__s    = [00000000 00000002]  
ev6__astrr_ppce_fpe__fpe__v    = [00000000 00000001]  
ev6__astrr_ppce_fpe__ppce__m   = [00000000 00000001]  
ev6__astrr_ppce_fpe__ppce__s   = [00000000 00000001]  
ev6__astrr_ppce_fpe__ppce__v   = [00000000 00000001]  
ev6__astrr_ppce_fpe__rsv0__m   = [00000000 00000001]  
ev6__astrr_ppce_fpe__rsv0__s   = [00000000 00000000]  
ev6__astrr_ppce_fpe__rsv0__v   = [00000000 00000001]  
ev6__astrr_ppce_fpe__rsv1__m   = [00000000 00000003]  
ev6__astrr_ppce_fpe__rsv1__s   = [00000000 00000003]  
ev6__astrr_ppce_fpe__rsv1__v   = [00000000 00000002]  
ev6__astrr_ppce_fpe__rsv2__m   = [00000000 03FFFFFF]  
ev6__astrr_ppce_fpe__rsv2__s   = [00000000 0000000D]  
ev6__astrr_ppce_fpe__rsv2__v   = [00000000 0000001A]  
ev6__astrr_ppce_fpe__rsv3__m   = [00000000 0001FFFF]  
ev6__astrr_ppce_fpe__rsv3__s   = [00000000 0000002F]  
ev6__astrr_ppce_fpe__rsv3__v   = [00000000 00000011]  
ev6__c_stat__double__m         = [00000000 00000001]  
ev6__c_stat__double__s         = [00000000 00000004]  
ev6__c_stat__istream__m        = [00000000 00000001]  
ev6__c_stat__istream__s        = [00000000 00000003]  
ev6__c_stat__type__m           = [00000000 00000007]  
ev6__c_stat__type__s           = [00000000 00000000]  
ev6__call_pal_00_entry         = [00000000 00002000]  
ev6__call_pal_01_entry         = [00000000 00002040]  
ev6__call_pal_02_entry         = [00000000 00002080]  
ev6__call_pal_03_entry         = [00000000 000020C0]  
ev6__call_pal_04_entry         = [00000000 00002100]  
ev6__call_pal_05_entry         = [00000000 00002140]  
ev6__call_pal_06_entry         = [00000000 00002180]  
ev6__call_pal_07_entry         = [00000000 000021C0]  
ev6__call_pal_08_entry         = [00000000 00002200]  
ev6__call_pal_09_entry         = [00000000 00002240]  
ev6__call_pal_0a_entry         = [00000000 00002280]  
ev6__call_pal_0b_entry         = [00000000 000022C0]  
ev6__call_pal_0c_entry         = [00000000 00002300]  
ev6__call_pal_0d_entry         = [00000000 00002340]  
ev6__call_pal_0e_entry         = [00000000 00002380]  
ev6__call_pal_0f_entry         = [00000000 000023C0]  
ev6__call_pal_10_entry         = [00000000 00002400]  
ev6__call_pal_11_entry         = [00000000 00002440]  
ev6__call_pal_12_entry         = [00000000 00002480]  
ev6__call_pal_13_entry         = [00000000 000024C0]  
ev6__call_pal_14_entry         = [00000000 00002500]  
ev6__call_pal_15_entry         = [00000000 00002540]  
ev6__call_pal_16_entry         = [00000000 00002580]  
ev6__call_pal_17_entry         = [00000000 000025C0]  
ev6__call_pal_18_entry         = [00000000 00002600]  
ev6__call_pal_19_entry         = [00000000 00002640]  
ev6__call_pal_1a_entry         = [00000000 00002680]  
ev6__call_pal_1b_entry         = [00000000 000026C0]  
ev6__call_pal_1c_entry         = [00000000 00002700]  
ev6__call_pal_1d_entry         = [00000000 00002740]  
ev6__call_pal_1e_entry         = [00000000 00002780]  
ev6__call_pal_1f_entry         = [00000000 000027C0]  
ev6__call_pal_20_entry         = [00000000 00002800]  
ev6__call_pal_21_entry         = [00000000 00002840]  
ev6__call_pal_22_entry         = [00000000 00002880]  
ev6__call_pal_23_entry         = [00000000 000028C0]  
ev6__call_pal_24_entry         = [00000000 00002900]  
ev6__call_pal_25_entry         = [00000000 00002940]  
ev6__call_pal_26_entry         = [00000000 00002980]  
ev6__call_pal_27_entry         = [00000000 000029C0]  
ev6__call_pal_28_entry         = [00000000 00002A00]  
ev6__call_pal_29_entry         = [00000000 00002A40]  
ev6__call_pal_2a_entry         = [00000000 00002A80]  
ev6__call_pal_2b_entry         = [00000000 00002AC0]  
ev6__call_pal_2c_entry         = [00000000 00002B00]  
ev6__call_pal_2d_entry         = [00000000 00002B40]  
ev6__call_pal_2e_entry         = [00000000 00002B80]  
ev6__call_pal_2f_entry         = [00000000 00002BC0]  
ev6__call_pal_30_entry         = [00000000 00002C00]  
ev6__call_pal_31_entry         = [00000000 00002C40]  
ev6__call_pal_32_entry         = [00000000 00002C80]  
ev6__call_pal_33_entry         = [00000000 00002CC0]  
ev6__call_pal_34_entry         = [00000000 00002D00]  
ev6__call_pal_35_entry         = [00000000 00002D40]  
ev6__call_pal_36_entry         = [00000000 00002D80]  
ev6__call_pal_37_entry         = [00000000 00002DC0]  
ev6__call_pal_38_entry         = [00000000 00002E00]  
ev6__call_pal_39_entry         = [00000000 00002E40]  
ev6__call_pal_3a_entry         = [00000000 00002E80]  
ev6__call_pal_3b_entry         = [00000000 00002EC0]  
ev6__call_pal_3c_entry         = [00000000 00002F00]  
ev6__call_pal_3d_entry         = [00000000 00002F40]  
ev6__call_pal_3e_entry         = [00000000 00002F80]  
ev6__call_pal_3f_entry         = [00000000 00002FC0]  
ev6__call_pal_80_entry         = [00000000 00003000]  
ev6__call_pal_81_entry         = [00000000 00003040]  
ev6__call_pal_82_entry         = [00000000 00003080]  
ev6__call_pal_83_entry         = [00000000 000030C0]  
ev6__call_pal_84_entry         = [00000000 00003100]  
ev6__call_pal_85_entry         = [00000000 00003140]  
ev6__call_pal_86_entry         = [00000000 00003180]  
ev6__call_pal_87_entry         = [00000000 000031C0]  
ev6__call_pal_88_entry         = [00000000 00003200]  
ev6__call_pal_89_entry         = [00000000 00003240]  
ev6__call_pal_8a_entry         = [00000000 00003280]  
ev6__call_pal_8b_entry         = [00000000 000032C0]  
ev6__call_pal_8c_entry         = [00000000 00003300]  
ev6__call_pal_8d_entry         = [00000000 00003340]  
ev6__call_pal_8e_entry         = [00000000 00003380]  
ev6__call_pal_8f_entry         = [00000000 000033C0]  
ev6__call_pal_90_entry         = [00000000 00003400]  
ev6__call_pal_91_entry         = [00000000 00003440]  
ev6__call_pal_92_entry         = [00000000 00003480]  
ev6__call_pal_93_entry         = [00000000 000034C0]  
ev6__call_pal_94_entry         = [00000000 00003500]  
ev6__call_pal_95_entry         = [00000000 00003540]  
ev6__call_pal_96_entry         = [00000000 00003580]  
ev6__call_pal_97_entry         = [00000000 000035C0]  
ev6__call_pal_98_entry         = [00000000 00003600]  
ev6__call_pal_99_entry         = [00000000 00003640]  
ev6__call_pal_9a_entry         = [00000000 00003680]  
ev6__call_pal_9b_entry         = [00000000 000036C0]  
ev6__call_pal_9c_entry         = [00000000 00003700]  
ev6__call_pal_9d_entry         = [00000000 00003740]  
ev6__call_pal_9e_entry         = [00000000 00003780]  
ev6__call_pal_9f_entry         = [00000000 000037C0]  
ev6__call_pal_a0_entry         = [00000000 00003800]  
ev6__call_pal_a1_entry         = [00000000 00003840]  
ev6__call_pal_a2_entry         = [00000000 00003880]  
ev6__call_pal_a3_entry         = [00000000 000038C0]  
ev6__call_pal_a4_entry         = [00000000 00003900]  
ev6__call_pal_a5_entry         = [00000000 00003940]  
ev6__call_pal_a6_entry         = [00000000 00003980]  
ev6__call_pal_a7_entry         = [00000000 000039C0]  
ev6__call_pal_a8_entry         = [00000000 00003A00]  
ev6__call_pal_a9_entry         = [00000000 00003A40]  
ev6__call_pal_aa_entry         = [00000000 00003A80]  
ev6__call_pal_ab_entry         = [00000000 00003AC0]  
ev6__call_pal_ac_entry         = [00000000 00003B00]  
ev6__call_pal_ad_entry         = [00000000 00003B40]  
ev6__call_pal_ae_entry         = [00000000 00003B80]  
ev6__call_pal_af_entry         = [00000000 00003BC0]  
ev6__call_pal_b0_entry         = [00000000 00003C00]  
ev6__call_pal_b1_entry         = [00000000 00003C40]  
ev6__call_pal_b2_entry         = [00000000 00003C80]  
ev6__call_pal_b3_entry         = [00000000 00003CC0]  
ev6__call_pal_b4_entry         = [00000000 00003D00]  
ev6__call_pal_b5_entry         = [00000000 00003D40]  
ev6__call_pal_b6_entry         = [00000000 00003D80]  
ev6__call_pal_b7_entry         = [00000000 00003DC0]  
ev6__call_pal_b8_entry         = [00000000 00003E00]  
ev6__call_pal_b9_entry         = [00000000 00003E40]  
ev6__call_pal_ba_entry         = [00000000 00003E80]  
ev6__call_pal_bb_entry         = [00000000 00003EC0]  
ev6__call_pal_bc_entry         = [00000000 00003F00]  
ev6__call_pal_bd_entry         = [00000000 00003F40]  
ev6__call_pal_be_entry         = [00000000 00003F80]  
ev6__call_pal_bf_entry         = [00000000 00003FC0]  
ev6__cc                        = [00000000 0000C020]  
ev6__cc__counter__m            = [00000000 0FFFFFFF]  
ev6__cc__counter__s            = [00000000 00000004]  
ev6__cc__counter__v            = [00000000 0000001C]  
ev6__cc__counter_bot__m        = [00000000 0000000F]  
ev6__cc__counter_bot__s        = [00000000 00000000]  
ev6__cc__counter_bot__v        = [00000000 00000004]  
ev6__cc__offset__m             = [00000000 FFFFFFFF]  
ev6__cc__offset__s             = [00000000 00000020]  
ev6__cc__offset__v             = [00000000 00000020]  
ev6__cc_ctl                    = [00000000 0000C120]  
ev6__cc_ctl__cc_ena__m         = [00000000 00000001]  
ev6__cc_ctl__cc_ena__s         = [00000000 00000020]  
ev6__cc_ctl__cc_ena__v         = [00000000 00000001]  
ev6__cc_ctl__counter__m        = [00000000 0FFFFFFF]  
ev6__cc_ctl__counter__s        = [00000000 00000004]  
ev6__cc_ctl__counter__v        = [00000000 0000001C]  
ev6__cc_ctl__rsv1__m           = [00000000 0000000F]  
ev6__cc_ctl__rsv1__s           = [00000000 00000000]  
ev6__cc_ctl__rsv1__v           = [00000000 00000004]  
ev6__cc_ctl__rsv2__m           = [00000000 7FFFFFFF]  
ev6__cc_ctl__rsv2__s           = [00000000 00000021]  
ev6__cc_ctl__rsv2__v           = [00000000 0000001F]  
ev6__chip_id_ev67_pass1        = [00000000 00000008]  
ev6__chip_id_ev67_pass2_1      = [00000000 00000008]  
ev6__chip_id_ev67_pass2_1_1    = [00000000 0000000A]  
ev6__chip_id_ev67_pass2_2      = [00000000 00000009]  
ev6__chip_id_ev67_pass2_2_1    = [00000000 0000000B]  
ev6__chip_id_ev68_pass1        = [00000000 00000010]  
ev6__chip_id_ev6_pass1         = [00000000 00000000]  
ev6__chip_id_ev6_pass2         = [00000000 00000001]  
ev6__chip_id_ev6_pass2_2       = [00000000 00000002]  
ev6__chip_id_ev6_pass2_3       = [00000000 00000003]  
ev6__chip_id_ev6_pass3         = [00000000 00000004]  
ev6__chip_id_ev7_pass1         = [00000000 00000018]  
ev6__clr_map                   = [00000000 000015F0]  
ev6__clr_map__rsv__m           = [FFFFFFFF FFFFFFFF]  
ev6__clr_map__rsv__s           = [00000000 00000000]  
ev6__clr_map__rsv__v           = [00000000 00000040]  
ev6__data                      = [00000000 00002B40]  
ev6__data__c_data__m           = [00000000 0000003F]  
ev6__data__c_data__s           = [00000000 00000000]  
ev6__data__c_data__v           = [00000000 00000006]  
ev6__data__rsv1__m             = [03FFFFFF FFFFFFFF]  
ev6__data__rsv1__s             = [00000000 00000006]  
ev6__data__rsv1__v             = [00000000 0000003A]  
ev6__dc_ctl                    = [00000000 00002940]  
ev6__dc_ctl__dcdat_err_en__m   = [00000000 00000001]  
ev6__dc_ctl__dcdat_err_en__s   = [00000000 00000007]  
ev6__dc_ctl__dcdat_err_en__v   = [00000000 00000001]  
ev6__dc_ctl__dctag_par_en__m   = [00000000 00000001]  
ev6__dc_ctl__dctag_par_en__s   = [00000000 00000006]  
ev6__dc_ctl__dctag_par_en__v   = [00000000 00000001]  
ev6__dc_ctl__f_bad_decc__m     = [00000000 00000001]  
ev6__dc_ctl__f_bad_decc__s     = [00000000 00000005]  
ev6__dc_ctl__f_bad_decc__v     = [00000000 00000001]  
ev6__dc_ctl__f_bad_tpar__m     = [00000000 00000001]  
ev6__dc_ctl__f_bad_tpar__s     = [00000000 00000004]  
ev6__dc_ctl__f_bad_tpar__v     = [00000000 00000001]  
ev6__dc_ctl__f_hit__m          = [00000000 00000001]  
ev6__dc_ctl__f_hit__s          = [00000000 00000002]  
ev6__dc_ctl__f_hit__v          = [00000000 00000001]  
ev6__dc_ctl__flush__m          = [00000000 00000001]  
ev6__dc_ctl__flush__s          = [00000000 00000003]  
ev6__dc_ctl__flush__v          = [00000000 00000001]  
ev6__dc_ctl__rsv1__m           = [00FFFFFF FFFFFFFF]  
ev6__dc_ctl__rsv1__s           = [00000000 00000008]  
ev6__dc_ctl__rsv1__v           = [00000000 00000038]  
ev6__dc_ctl__set_en__m         = [00000000 00000003]  
ev6__dc_ctl__set_en__s         = [00000000 00000000]  
ev6__dc_ctl__set_en__v         = [00000000 00000002]  
ev6__dc_stat                   = [00000000 00002A40]  
ev6__dc_stat__ecc_err_ld__m    = [00000000 00000001]  
ev6__dc_stat__ecc_err_ld__s    = [00000000 00000003]  
ev6__dc_stat__ecc_err_ld__v    = [00000000 00000001]  
ev6__dc_stat__ecc_err_st__m    = [00000000 00000001]  
ev6__dc_stat__ecc_err_st__s    = [00000000 00000002]  
ev6__dc_stat__ecc_err_st__v    = [00000000 00000001]  
ev6__dc_stat__rsv1__m          = [07FFFFFF FFFFFFFF]  
ev6__dc_stat__rsv1__s          = [00000000 00000005]  
ev6__dc_stat__rsv1__v          = [00000000 0000003B]  
ev6__dc_stat__seo__m           = [00000000 00000001]  
ev6__dc_stat__seo__s           = [00000000 00000004]  
ev6__dc_stat__seo__v           = [00000000 00000001]  
ev6__dc_stat__tperr_p0__m      = [00000000 00000001]  
ev6__dc_stat__tperr_p0__s      = [00000000 00000000]  
ev6__dc_stat__tperr_p0__v      = [00000000 00000001]  
ev6__dc_stat__tperr_p1__m      = [00000000 00000001]  
ev6__dc_stat__tperr_p1__s      = [00000000 00000001]  
ev6__dc_stat__tperr_p1__v      = [00000000 00000001]  
ev6__dc_stat__w1c              = [00000000 0000001F]  
ev6__dc_stat__w1c_crd          = [00000000 0000000C]  
ev6__dfault_entry              = [00000000 00000380]  
ev6__dtb_alt_mode              = [00000000 00002640]  
ev6__dtb_alt_mode__mode__m     = [00000000 00000003]  
ev6__dtb_alt_mode__mode__s     = [00000000 00000000]  
ev6__dtb_alt_mode__mode__v     = [00000000 00000002]  
ev6__dtb_alt_mode__rsv1__m     = [3FFFFFFF FFFFFFFF]  
ev6__dtb_alt_mode__rsv1__s     = [00000000 00000002]  
ev6__dtb_alt_mode__rsv1__v     = [00000000 0000003E]  
ev6__dtb_asn0                  = [00000000 00002510]  
ev6__dtb_asn0__asn__m          = [00000000 000000FF]  
ev6__dtb_asn0__asn__s          = [00000000 00000038]  
ev6__dtb_asn0__asn__v          = [00000000 00000008]  
ev6__dtb_asn0__rsv__m          = [00FFFFFF FFFFFFFF]  
ev6__dtb_asn0__rsv__s          = [00000000 00000000]  
ev6__dtb_asn0__rsv__v          = [00000000 00000038]  
ev6__dtb_asn1                  = [00000000 0000A580]  
ev6__dtb_asn1__asn__m          = [00000000 000000FF]  
ev6__dtb_asn1__asn__s          = [00000000 00000038]  
ev6__dtb_asn1__asn__v          = [00000000 00000008]  
ev6__dtb_asn1__rsv__m          = [00FFFFFF FFFFFFFF]  
ev6__dtb_asn1__rsv__s          = [00000000 00000000]  
ev6__dtb_asn1__rsv__v          = [00000000 00000038]  
ev6__dtb_ia                    = [00000000 0000A380]  
ev6__dtb_ia__rsv__m            = [FFFFFFFF FFFFFFFF]  
ev6__dtb_ia__rsv__s            = [00000000 00000000]  
ev6__dtb_ia__rsv__v            = [00000000 00000040]  
ev6__dtb_iap                   = [00000000 0000A280]  
ev6__dtb_iap__rsv__m           = [FFFFFFFF FFFFFFFF]  
ev6__dtb_iap__rsv__s           = [00000000 00000000]  
ev6__dtb_iap__rsv__v           = [00000000 00000040]  
ev6__dtb_is0                   = [00000000 00002440]  
ev6__dtb_is0__rsv1__m          = [00000000 00001FFF]  
ev6__dtb_is0__rsv1__s          = [00000000 00000000]  
ev6__dtb_is0__rsv1__v          = [00000000 0000000D]  
ev6__dtb_is0__rsv2__m          = [00000000 0000FFFF]  
ev6__dtb_is0__rsv2__s          = [00000000 00000030]  
ev6__dtb_is0__rsv2__v          = [00000000 00000010]  
ev6__dtb_is0__va__m            = [00000007 FFFFFFFF]  
ev6__dtb_is0__va__s            = [00000000 0000000D]  
ev6__dtb_is0__va__v            = [00000000 00000023]  
ev6__dtb_is1                   = [00000000 0000A480]  
ev6__dtb_is1__rsv1__m          = [00000000 00001FFF]  
ev6__dtb_is1__rsv1__s          = [00000000 00000000]  
ev6__dtb_is1__rsv1__v          = [00000000 0000000D]  
ev6__dtb_is1__rsv2__m          = [00000000 0000FFFF]  
ev6__dtb_is1__rsv2__s          = [00000000 00000030]  
ev6__dtb_is1__rsv2__v          = [00000000 00000010]  
ev6__dtb_is1__va__m            = [00000007 FFFFFFFF]  
ev6__dtb_is1__va__s            = [00000000 0000000D]  
ev6__dtb_is1__va__v            = [00000000 00000023]  
ev6__dtb_pte0                  = [00000000 00002111]  
ev6__dtb_pte0__asm__m          = [00000000 00000001]  
ev6__dtb_pte0__asm__s          = [00000000 00000004]  
ev6__dtb_pte0__asm__v          = [00000000 00000001]  
ev6__dtb_pte0__ere__m          = [00000000 00000001]  
ev6__dtb_pte0__ere__s          = [00000000 00000009]  
ev6__dtb_pte0__ere__v          = [00000000 00000001]  
ev6__dtb_pte0__ewe__m          = [00000000 00000001]  
ev6__dtb_pte0__ewe__s          = [00000000 0000000D]  
ev6__dtb_pte0__ewe__v          = [00000000 00000001]  
ev6__dtb_pte0__for__m          = [00000000 00000001]  
ev6__dtb_pte0__for__s          = [00000000 00000001]  
ev6__dtb_pte0__for__v          = [00000000 00000001]  
ev6__dtb_pte0__fow__m          = [00000000 00000001]  
ev6__dtb_pte0__fow__s          = [00000000 00000002]  
ev6__dtb_pte0__fow__v          = [00000000 00000001]  
ev6__dtb_pte0__gh__m           = [00000000 00000003]  
ev6__dtb_pte0__gh__s           = [00000000 00000005]  
ev6__dtb_pte0__gh__v           = [00000000 00000002]  
ev6__dtb_pte0__kre__m          = [00000000 00000001]  
ev6__dtb_pte0__kre__s          = [00000000 00000008]  
ev6__dtb_pte0__kre__v          = [00000000 00000001]  
ev6__dtb_pte0__kwe__m          = [00000000 00000001]  
ev6__dtb_pte0__kwe__s          = [00000000 0000000C]  
ev6__dtb_pte0__kwe__v          = [00000000 00000001]  
ev6__dtb_pte0__pfn__m          = [00000000 7FFFFFFF]  
ev6__dtb_pte0__pfn__s          = [00000000 00000020]  
ev6__dtb_pte0__pfn__v          = [00000000 0000001F]  
ev6__dtb_pte0__rsv1__m         = [00000000 00000001]  
ev6__dtb_pte0__rsv1__s         = [00000000 00000000]  
ev6__dtb_pte0__rsv1__v         = [00000000 00000001]  
ev6__dtb_pte0__rsv2__m         = [00000000 00000001]  
ev6__dtb_pte0__rsv2__s         = [00000000 00000003]  
ev6__dtb_pte0__rsv2__v         = [00000000 00000001]  
ev6__dtb_pte0__rsv3__m         = [00000000 00000001]  
ev6__dtb_pte0__rsv3__s         = [00000000 00000007]  
ev6__dtb_pte0__rsv3__v         = [00000000 00000001]  
ev6__dtb_pte0__rsv4__m         = [00000000 0000FFFF]  
ev6__dtb_pte0__rsv4__s         = [00000000 00000010]  
ev6__dtb_pte0__rsv4__v         = [00000000 00000010]  
ev6__dtb_pte0__rsv5__m         = [00000000 00000001]  
ev6__dtb_pte0__rsv5__s         = [00000000 0000003F]  
ev6__dtb_pte0__rsv5__v         = [00000000 00000001]  
ev6__dtb_pte0__sre__m          = [00000000 00000001]  
ev6__dtb_pte0__sre__s          = [00000000 0000000A]  
ev6__dtb_pte0__sre__v          = [00000000 00000001]  
ev6__dtb_pte0__swe__m          = [00000000 00000001]  
ev6__dtb_pte0__swe__s          = [00000000 0000000E]  
ev6__dtb_pte0__swe__v          = [00000000 00000001]  
ev6__dtb_pte0__ure__m          = [00000000 00000001]  
ev6__dtb_pte0__ure__s          = [00000000 0000000B]  
ev6__dtb_pte0__ure__v          = [00000000 00000001]  
ev6__dtb_pte0__uwe__m          = [00000000 00000001]  
ev6__dtb_pte0__uwe__s          = [00000000 0000000F]  
ev6__dtb_pte0__uwe__v          = [00000000 00000001]  
ev6__dtb_pte1                  = [00000000 0000A188]  
ev6__dtb_pte1__asm__m          = [00000000 00000001]  
ev6__dtb_pte1__asm__s          = [00000000 00000004]  
ev6__dtb_pte1__asm__v          = [00000000 00000001]  
ev6__dtb_pte1__ere__m          = [00000000 00000001]  
ev6__dtb_pte1__ere__s          = [00000000 00000009]  
ev6__dtb_pte1__ere__v          = [00000000 00000001]  
ev6__dtb_pte1__ewe__m          = [00000000 00000001]  
ev6__dtb_pte1__ewe__s          = [00000000 0000000D]  
ev6__dtb_pte1__ewe__v          = [00000000 00000001]  
ev6__dtb_pte1__for__m          = [00000000 00000001]  
ev6__dtb_pte1__for__s          = [00000000 00000001]  
ev6__dtb_pte1__for__v          = [00000000 00000001]  
ev6__dtb_pte1__fow__m          = [00000000 00000001]  
ev6__dtb_pte1__fow__s          = [00000000 00000002]  
ev6__dtb_pte1__fow__v          = [00000000 00000001]  
ev6__dtb_pte1__gh__m           = [00000000 00000003]  
ev6__dtb_pte1__gh__s           = [00000000 00000005]  
ev6__dtb_pte1__gh__v           = [00000000 00000002]  
ev6__dtb_pte1__kre__m          = [00000000 00000001]  
ev6__dtb_pte1__kre__s          = [00000000 00000008]  
ev6__dtb_pte1__kre__v          = [00000000 00000001]  
ev6__dtb_pte1__kwe__m          = [00000000 00000001]  
ev6__dtb_pte1__kwe__s          = [00000000 0000000C]  
ev6__dtb_pte1__kwe__v          = [00000000 00000001]  
ev6__dtb_pte1__pfn__m          = [00000000 7FFFFFFF]  
ev6__dtb_pte1__pfn__s          = [00000000 00000020]  
ev6__dtb_pte1__pfn__v          = [00000000 0000001F]  
ev6__dtb_pte1__rsv1__m         = [00000000 00000001]  
ev6__dtb_pte1__rsv1__s         = [00000000 00000000]  
ev6__dtb_pte1__rsv1__v         = [00000000 00000001]  
ev6__dtb_pte1__rsv2__m         = [00000000 00000001]  
ev6__dtb_pte1__rsv2__s         = [00000000 00000003]  
ev6__dtb_pte1__rsv2__v         = [00000000 00000001]  
ev6__dtb_pte1__rsv3__m         = [00000000 00000001]  
ev6__dtb_pte1__rsv3__s         = [00000000 00000007]  
ev6__dtb_pte1__rsv3__v         = [00000000 00000001]  
ev6__dtb_pte1__rsv4__m         = [00000000 0000FFFF]  
ev6__dtb_pte1__rsv4__s         = [00000000 00000010]  
ev6__dtb_pte1__rsv4__v         = [00000000 00000010]  
ev6__dtb_pte1__rsv5__m         = [00000000 00000001]  
ev6__dtb_pte1__rsv5__s         = [00000000 0000003F]  
ev6__dtb_pte1__rsv5__v         = [00000000 00000001]  
ev6__dtb_pte1__sre__m          = [00000000 00000001]  
ev6__dtb_pte1__sre__s          = [00000000 0000000A]  
ev6__dtb_pte1__sre__v          = [00000000 00000001]  
ev6__dtb_pte1__swe__m          = [00000000 00000001]  
ev6__dtb_pte1__swe__s          = [00000000 0000000E]  
ev6__dtb_pte1__swe__v          = [00000000 00000001]  
ev6__dtb_pte1__ure__m          = [00000000 00000001]  
ev6__dtb_pte1__ure__s          = [00000000 0000000B]  
ev6__dtb_pte1__ure__v          = [00000000 00000001]  
ev6__dtb_pte1__uwe__m          = [00000000 00000001]  
ev6__dtb_pte1__uwe__s          = [00000000 0000000F]  
ev6__dtb_pte1__uwe__v          = [00000000 00000001]  
ev6__dtb_tag0                  = [00000000 00002044]  
ev6__dtb_tag0__rsv1__m         = [00000000 00001FFF]  
ev6__dtb_tag0__rsv1__s         = [00000000 00000000]  
ev6__dtb_tag0__rsv1__v         = [00000000 0000000D]  
ev6__dtb_tag0__rsv2__m         = [00000000 0000FFFF]  
ev6__dtb_tag0__rsv2__s         = [00000000 00000030]  
ev6__dtb_tag0__rsv2__v         = [00000000 00000010]  
ev6__dtb_tag0__va__m           = [00000007 FFFFFFFF]  
ev6__dtb_tag0__va__s           = [00000000 0000000D]  
ev6__dtb_tag0__va__v           = [00000000 00000023]  
ev6__dtb_tag1                  = [00000000 0000A022]  
ev6__dtb_tag1__rsv1__m         = [00000000 00001FFF]  
ev6__dtb_tag1__rsv1__s         = [00000000 00000000]  
ev6__dtb_tag1__rsv1__v         = [00000000 0000000D]  
ev6__dtb_tag1__rsv2__m         = [00000000 0000FFFF]  
ev6__dtb_tag1__rsv2__s         = [00000000 00000030]  
ev6__dtb_tag1__rsv2__v         = [00000000 00000010]  
ev6__dtb_tag1__va__m           = [00000007 FFFFFFFF]  
ev6__dtb_tag1__va__s           = [00000000 0000000D]  
ev6__dtb_tag1__va__v           = [00000000 00000023]  
ev6__dtbm_double_3_entry       = [00000000 00000100]  
ev6__dtbm_double_4_entry       = [00000000 00000180]  
ev6__dtbm_single_entry         = [00000000 00000300]  
ev6__exc_addr                  = [00000000 00000600]  
ev6__exc_addr__pal__m          = [00000000 00000001]  
ev6__exc_addr__pal__s          = [00000000 00000000]  
ev6__exc_addr__pal__v          = [00000000 00000001]  
ev6__exc_addr__pc__m           = [00003FFF FFFFFFFF]  
ev6__exc_addr__pc__s           = [00000000 00000002]  
ev6__exc_addr__pc__v           = [00000000 0000002E]  
ev6__exc_addr__pc_sext0__m     = [00000000 00000001]  
ev6__exc_addr__pc_sext0__s     = [00000000 00000030]  
ev6__exc_addr__pc_sext0__v     = [00000000 00000001]  
ev6__exc_addr__pc_sext10__m    = [00000000 00000001]  
ev6__exc_addr__pc_sext10__s    = [00000000 0000003A]  
ev6__exc_addr__pc_sext10__v    = [00000000 00000001]  
ev6__exc_addr__pc_sext11__m    = [00000000 00000001]  
ev6__exc_addr__pc_sext11__s    = [00000000 0000003B]  
ev6__exc_addr__pc_sext11__v    = [00000000 00000001]  
ev6__exc_addr__pc_sext12__m    = [00000000 00000001]  
ev6__exc_addr__pc_sext12__s    = [00000000 0000003C]  
ev6__exc_addr__pc_sext12__v    = [00000000 00000001]  
ev6__exc_addr__pc_sext13__m    = [00000000 00000001]  
ev6__exc_addr__pc_sext13__s    = [00000000 0000003D]  
ev6__exc_addr__pc_sext13__v    = [00000000 00000001]  
ev6__exc_addr__pc_sext14__m    = [00000000 00000001]  
ev6__exc_addr__pc_sext14__s    = [00000000 0000003E]  
ev6__exc_addr__pc_sext14__v    = [00000000 00000001]  
ev6__exc_addr__pc_sext15__m    = [00000000 00000001]  
ev6__exc_addr__pc_sext15__s    = [00000000 0000003F]  
ev6__exc_addr__pc_sext15__v    = [00000000 00000001]  
ev6__exc_addr__pc_sext1__m     = [00000000 00000001]  
ev6__exc_addr__pc_sext1__s     = [00000000 00000031]  
ev6__exc_addr__pc_sext1__v     = [00000000 00000001]  
ev6__exc_addr__pc_sext2__m     = [00000000 00000001]  
ev6__exc_addr__pc_sext2__s     = [00000000 00000032]  
ev6__exc_addr__pc_sext2__v     = [00000000 00000001]  
ev6__exc_addr__pc_sext3__m     = [00000000 00000001]  
ev6__exc_addr__pc_sext3__s     = [00000000 00000033]  
ev6__exc_addr__pc_sext3__v     = [00000000 00000001]  
ev6__exc_addr__pc_sext4__m     = [00000000 00000001]  
ev6__exc_addr__pc_sext4__s     = [00000000 00000034]  
ev6__exc_addr__pc_sext4__v     = [00000000 00000001]  
ev6__exc_addr__pc_sext5__m     = [00000000 00000001]  
ev6__exc_addr__pc_sext5__s     = [00000000 00000035]  
ev6__exc_addr__pc_sext5__v     = [00000000 00000001]  
ev6__exc_addr__pc_sext6__m     = [00000000 00000001]  
ev6__exc_addr__pc_sext6__s     = [00000000 00000036]  
ev6__exc_addr__pc_sext6__v     = [00000000 00000001]  
ev6__exc_addr__pc_sext7__m     = [00000000 00000001]  
ev6__exc_addr__pc_sext7__s     = [00000000 00000037]  
ev6__exc_addr__pc_sext7__v     = [00000000 00000001]  
ev6__exc_addr__pc_sext8__m     = [00000000 00000001]  
ev6__exc_addr__pc_sext8__s     = [00000000 00000038]  
ev6__exc_addr__pc_sext8__v     = [00000000 00000001]  
ev6__exc_addr__pc_sext9__m     = [00000000 00000001]  
ev6__exc_addr__pc_sext9__s     = [00000000 00000039]  
ev6__exc_addr__pc_sext9__v     = [00000000 00000001]  
ev6__exc_addr__rsv__m          = [00000000 00000001]  
ev6__exc_addr__rsv__s          = [00000000 00000001]  
ev6__exc_addr__rsv__v          = [00000000 00000001]  
ev6__exc_sum                   = [00000000 00000F00]  
ev6__exc_sum__bad_iva__m       = [00000000 00000001]  
ev6__exc_sum__bad_iva__s       = [00000000 0000000D]  
ev6__exc_sum__bad_iva__v       = [00000000 00000001]  
ev6__exc_sum__dze__m           = [00000000 00000001]  
ev6__exc_sum__dze__s           = [00000000 00000002]  
ev6__exc_sum__dze__v           = [00000000 00000001]  
ev6__exc_sum__fov__m           = [00000000 00000001]  
ev6__exc_sum__fov__s           = [00000000 00000003]  
ev6__exc_sum__fov__v           = [00000000 00000001]  
ev6__exc_sum__ine__m           = [00000000 00000001]  
ev6__exc_sum__ine__s           = [00000000 00000005]  
ev6__exc_sum__ine__v           = [00000000 00000001]  
ev6__exc_sum__int__m           = [00000000 00000001]  
ev6__exc_sum__int__s           = [00000000 00000007]  
ev6__exc_sum__int__v           = [00000000 00000001]  
ev6__exc_sum__inv__m           = [00000000 00000001]  
ev6__exc_sum__inv__s           = [00000000 00000001]  
ev6__exc_sum__inv__v           = [00000000 00000001]  
ev6__exc_sum__iov__m           = [00000000 00000001]  
ev6__exc_sum__iov__s           = [00000000 00000006]  
ev6__exc_sum__iov__v           = [00000000 00000001]  
ev6__exc_sum__pc_ovfl__m       = [00000000 00000001]  
ev6__exc_sum__pc_ovfl__s       = [00000000 00000029]  
ev6__exc_sum__pc_ovfl__v       = [00000000 00000001]  
ev6__exc_sum__reg__m           = [00000000 0000001F]  
ev6__exc_sum__reg__s           = [00000000 00000008]  
ev6__exc_sum__reg__v           = [00000000 00000005]  
ev6__exc_sum__rsv1__m          = [00000000 07FFFFFF]  
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ev6__exc_sum__set_dze__m       = [00000000 00000001]  
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ev6__exc_sum__set_fov__m       = [00000000 00000001]  
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ev6__exc_sum__set_inv__s       = [00000000 0000002A]  
ev6__exc_sum__set_inv__v       = [00000000 00000001]  
ev6__exc_sum__set_iov__m       = [00000000 00000001]  
ev6__exc_sum__set_iov__s       = [00000000 0000002F]  
ev6__exc_sum__set_iov__v       = [00000000 00000001]  
ev6__exc_sum__set_unf__m       = [00000000 00000001]  
ev6__exc_sum__set_unf__s       = [00000000 0000002D]  
ev6__exc_sum__set_unf__v       = [00000000 00000001]  
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ev6__exc_sum__swc__m           = [00000000 00000001]  
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ev6__exc_sum__unf__m           = [00000000 00000001]  
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ev6__fen                       = [00000000 00010000]  
ev6__fen__fen__m               = [00000000 00000001]  
ev6__fen__fen__s               = [00000000 00000000]  
ev6__fen__fen__v               = [00000000 00000001]  
ev6__fen__rsv2__m              = [7FFFFFFF FFFFFFFF]  
ev6__fen__rsv2__s              = [00000000 00000001]  
ev6__fen__rsv2__v              = [00000000 0000003F]  
ev6__fen_entry                 = [00000000 00000200]  
ev6__fpcr                      = [00000000 00010001]  
ev6__fpcr__dnz__m              = [00000000 00000001]  
ev6__fpcr__dnz__s              = [00000000 00000030]  
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ev6__fpcr__dyn__m              = [00000000 00000003]  
ev6__fpcr__dyn__s              = [00000000 0000003A]  
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ev6__fpcr__dze__m              = [00000000 00000001]  
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ev6__fpcr__dzed__m             = [00000000 00000001]  
ev6__fpcr__dzed__s             = [00000000 00000032]  
ev6__fpcr__dzed__v             = [00000000 00000001]  
ev6__fpcr__ine__m              = [00000000 00000001]  
ev6__fpcr__ine__s              = [00000000 00000038]  
ev6__fpcr__ine__v              = [00000000 00000001]  
ev6__fpcr__ined__m             = [00000000 00000001]  
ev6__fpcr__ined__s             = [00000000 0000003E]  
ev6__fpcr__ined__v             = [00000000 00000001]  
ev6__fpcr__inv__m              = [00000000 00000001]  
ev6__fpcr__inv__s              = [00000000 00000034]  
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ev6__fpcr__invd__m             = [00000000 00000001]  
ev6__fpcr__invd__s             = [00000000 00000031]  
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ev6__fpcr__iov__m              = [00000000 00000001]  
ev6__fpcr__iov__s              = [00000000 00000039]  
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ev6__fpcr__ovf__m              = [00000000 00000001]  
ev6__fpcr__ovf__s              = [00000000 00000036]  
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ev6__fpcr__ovfd__m             = [00000000 00000001]  
ev6__fpcr__ovfd__s             = [00000000 00000033]  
ev6__fpcr__ovfd__v             = [00000000 00000001]  
ev6__fpcr__rsv1__m             = [0000FFFF FFFFFFFF]  
ev6__fpcr__rsv1__s             = [00000000 00000000]  
ev6__fpcr__rsv1__v             = [00000000 00000030]  
ev6__fpcr__sum__m              = [00000000 00000001]  
ev6__fpcr__sum__s              = [00000000 0000003F]  
ev6__fpcr__sum__v              = [00000000 00000001]  
ev6__fpcr__undz__m             = [00000000 00000001]  
ev6__fpcr__undz__s             = [00000000 0000003C]  
ev6__fpcr__undz__v             = [00000000 00000001]  
ev6__fpcr__unf__m              = [00000000 00000001]  
ev6__fpcr__unf__s              = [00000000 00000037]  
ev6__fpcr__unf__v              = [00000000 00000001]  
ev6__fpcr__unfd__m             = [00000000 00000001]  
ev6__fpcr__unfd__s             = [00000000 0000003D]  
ev6__fpcr__unfd__v             = [00000000 00000001]  
ev6__fpe                       = [00000000 00005010]  
ev6__fpe__asn__m               = [00000000 000000FF]  
ev6__fpe__asn__s               = [00000000 00000027]  
ev6__fpe__asn__v               = [00000000 00000008]  
ev6__fpe__aster__m             = [00000000 0000000F]  
ev6__fpe__aster__s             = [00000000 00000005]  
ev6__fpe__aster__v             = [00000000 00000004]  
ev6__fpe__astrr__m             = [00000000 0000000F]  
ev6__fpe__astrr__s             = [00000000 00000009]  
ev6__fpe__astrr__v             = [00000000 00000004]  
ev6__fpe__fpe__m               = [00000000 00000001]  
ev6__fpe__fpe__s               = [00000000 00000002]  
ev6__fpe__fpe__v               = [00000000 00000001]  
ev6__fpe__ppce__m              = [00000000 00000001]  
ev6__fpe__ppce__s              = [00000000 00000001]  
ev6__fpe__ppce__v              = [00000000 00000001]  
ev6__fpe__rsv0__m              = [00000000 00000001]  
ev6__fpe__rsv0__s              = [00000000 00000000]  
ev6__fpe__rsv0__v              = [00000000 00000001]  
ev6__fpe__rsv1__m              = [00000000 00000003]  
ev6__fpe__rsv1__s              = [00000000 00000003]  
ev6__fpe__rsv1__v              = [00000000 00000002]  
ev6__fpe__rsv2__m              = [00000000 03FFFFFF]  
ev6__fpe__rsv2__s              = [00000000 0000000D]  
ev6__fpe__rsv2__v              = [00000000 0000001A]  
ev6__fpe__rsv3__m              = [00000000 0001FFFF]  
ev6__fpe__rsv3__s              = [00000000 0000002F]  
ev6__fpe__rsv3__v              = [00000000 00000011]  
ev6__halt_entry                = [00000000 00002000]  
ev6__hw_int_clr                = [00000000 00000E10]  
ev6__hw_int_clr__cr__m         = [00000000 00000001]  
ev6__hw_int_clr__cr__s         = [00000000 0000001F]  
ev6__hw_int_clr__cr__v         = [00000000 00000001]  
ev6__hw_int_clr__fbdp__m       = [00000000 00000001]  
ev6__hw_int_clr__fbdp__s       = [00000000 0000001B]  
ev6__hw_int_clr__fbdp__v       = [00000000 00000001]  
ev6__hw_int_clr__fbtp__m       = [00000000 00000001]  
ev6__hw_int_clr__fbtp__s       = [00000000 0000001A]  
ev6__hw_int_clr__fbtp__v       = [00000000 00000001]  
ev6__hw_int_clr__init          = [00000000 0000001F]  
ev6__hw_int_clr__mchk_d__m     = [00000000 00000001]  
ev6__hw_int_clr__mchk_d__s     = [00000000 0000001C]  
ev6__hw_int_clr__mchk_d__v     = [00000000 00000001]  
ev6__hw_int_clr__pc__m         = [00000000 00000003]  
ev6__hw_int_clr__pc__s         = [00000000 0000001D]  
ev6__hw_int_clr__pc__v         = [00000000 00000002]  
ev6__hw_int_clr__rsv1__m       = [00000000 03FFFFFF]  
ev6__hw_int_clr__rsv1__s       = [00000000 00000000]  
ev6__hw_int_clr__rsv1__v       = [00000000 0000001A]  
ev6__hw_int_clr__rsv2__m       = [00000000 7FFFFFFF]  
ev6__hw_int_clr__rsv2__s       = [00000000 00000021]  
ev6__hw_int_clr__rsv2__v       = [00000000 0000001F]  
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ev6__hw_int_clr__sl__s         = [00000000 00000020]  
ev6__hw_int_clr__sl__v         = [00000000 00000001]  
ev6__hw_int_reg                = [00000000 0001000E]  
ev6__hw_int_reg__cr__m         = [00000000 00000001]  
ev6__hw_int_reg__cr__s         = [00000000 0000001F]  
ev6__hw_int_reg__cr__v         = [00000000 00000001]  
ev6__hw_int_reg__fbdp__m       = [00000000 00000001]  
ev6__hw_int_reg__fbdp__s       = [00000000 0000001B]  
ev6__hw_int_reg__fbdp__v       = [00000000 00000001]  
ev6__hw_int_reg__fbtp__m       = [00000000 00000001]  
ev6__hw_int_reg__fbtp__s       = [00000000 0000001A]  
ev6__hw_int_reg__fbtp__v       = [00000000 00000001]  
ev6__hw_int_reg__mchk_d__m     = [00000000 00000001]  
ev6__hw_int_reg__mchk_d__s     = [00000000 0000001C]  
ev6__hw_int_reg__mchk_d__v     = [00000000 00000001]  
ev6__hw_int_reg__pc__m         = [00000000 00000003]  
ev6__hw_int_reg__pc__s         = [00000000 0000001D]  
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ev6__hw_int_reg__rsv1__m       = [00000000 03FFFFFF]  
ev6__hw_int_reg__rsv1__s       = [00000000 00000000]  
ev6__hw_int_reg__rsv1__v       = [00000000 0000001A]  
ev6__hw_int_reg__rsv2__m       = [00000000 7FFFFFFF]  
ev6__hw_int_reg__rsv2__s       = [00000000 00000021]  
ev6__hw_int_reg__rsv2__v       = [00000000 0000001F]  
ev6__hw_int_reg__sl__m         = [00000000 00000001]  
ev6__hw_int_reg__sl__s         = [00000000 00000020]  
ev6__hw_int_reg__sl__v         = [00000000 00000001]  
ev6__i_ctl                     = [00000000 00001110]  
ev6__i_ctl__bist_fail__m       = [00000000 00000001]  
ev6__i_ctl__bist_fail__s       = [00000000 00000017]  
ev6__i_ctl__bist_fail__v       = [00000000 00000001]  
ev6__i_ctl__bp_mode__m         = [00000000 00000003]  
ev6__i_ctl__bp_mode__s         = [00000000 0000000A]  
ev6__i_ctl__bp_mode__v         = [00000000 00000002]  
ev6__i_ctl__call_pal_r23__m    = [00000000 00000001]  
ev6__i_ctl__call_pal_r23__s    = [00000000 00000014]  
ev6__i_ctl__call_pal_r23__v    = [00000000 00000001]  
ev6__i_ctl__chip_id__m         = [00000000 0000003F]  
ev6__i_ctl__chip_id__s         = [00000000 00000018]  
ev6__i_ctl__chip_id__v         = [00000000 00000006]  
ev6__i_ctl__hwe__m             = [00000000 00000001]  
ev6__i_ctl__hwe__s             = [00000000 0000000C]  
ev6__i_ctl__hwe__v             = [00000000 00000001]  
ev6__i_ctl__ic_en__m           = [00000000 00000003]  
ev6__i_ctl__ic_en__s           = [00000000 00000001]  
ev6__i_ctl__ic_en__v           = [00000000 00000002]  
ev6__i_ctl__init               = [00000000 001083A6]  
ev6__i_ctl__mchk_en__m         = [00000000 00000001]  
ev6__i_ctl__mchk_en__s         = [00000000 00000015]  
ev6__i_ctl__mchk_en__v         = [00000000 00000001]  
ev6__i_ctl__pct0_en__m         = [00000000 00000001]  
ev6__i_ctl__pct0_en__s         = [00000000 00000012]  
ev6__i_ctl__pct0_en__v         = [00000000 00000001]  
ev6__i_ctl__pct1_en__m         = [00000000 00000001]  
ev6__i_ctl__pct1_en__s         = [00000000 00000013]  
ev6__i_ctl__pct1_en__v         = [00000000 00000001]  
ev6__i_ctl__sbe__m             = [00000000 00000003]  
ev6__i_ctl__sbe__s             = [00000000 00000008]  
ev6__i_ctl__sbe__v             = [00000000 00000002]  
ev6__i_ctl__sde7__s            = [00000000 00000007]  
ev6__i_ctl__sde__m             = [00000000 00000003]  
ev6__i_ctl__sde__s             = [00000000 00000006]  
ev6__i_ctl__sde__v             = [00000000 00000002]  
ev6__i_ctl__shadow_init        = [00000000 00100086]  
ev6__i_ctl__single_issue__m    = [00000000 00000001]  
ev6__i_ctl__single_issue__s    = [00000000 00000011]  
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ev6__i_ctl__sl_xmit__m         = [00000000 00000001]  
ev6__i_ctl__sl_xmit__s         = [00000000 0000000D]  
ev6__i_ctl__sl_xmit__v         = [00000000 00000001]  
ev6__i_ctl__spce__m            = [00000000 00000001]  
ev6__i_ctl__spce__s            = [00000000 00000000]  
ev6__i_ctl__spce__v            = [00000000 00000001]  
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ev6__i_ctl__spe__s             = [00000000 00000003]  
ev6__i_ctl__spe__v             = [00000000 00000003]  
ev6__i_ctl__tb_mb_en__m        = [00000000 00000001]  
ev6__i_ctl__tb_mb_en__s        = [00000000 00000016]  
ev6__i_ctl__tb_mb_en__v        = [00000000 00000001]  
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ev6__i_ctl__vptb__v            = [00000000 00000012]  
ev6__i_ctl__vptb_sext0__m      = [00000000 00000001]  
ev6__i_ctl__vptb_sext0__s      = [00000000 00000030]  
ev6__i_ctl__vptb_sext0__v      = [00000000 00000001]  
ev6__i_ctl__vptb_sext10__m     = [00000000 00000001]  
ev6__i_ctl__vptb_sext10__s     = [00000000 0000003A]  
ev6__i_ctl__vptb_sext10__v     = [00000000 00000001]  
ev6__i_ctl__vptb_sext11__m     = [00000000 00000001]  
ev6__i_ctl__vptb_sext11__s     = [00000000 0000003B]  
ev6__i_ctl__vptb_sext11__v     = [00000000 00000001]  
ev6__i_ctl__vptb_sext12__m     = [00000000 00000001]  
ev6__i_ctl__vptb_sext12__s     = [00000000 0000003C]  
ev6__i_ctl__vptb_sext12__v     = [00000000 00000001]  
ev6__i_ctl__vptb_sext13__m     = [00000000 00000001]  
ev6__i_ctl__vptb_sext13__s     = [00000000 0000003D]  
ev6__i_ctl__vptb_sext13__v     = [00000000 00000001]  
ev6__i_ctl__vptb_sext14__m     = [00000000 00000001]  
ev6__i_ctl__vptb_sext14__s     = [00000000 0000003E]  
ev6__i_ctl__vptb_sext14__v     = [00000000 00000001]  
ev6__i_ctl__vptb_sext15__m     = [00000000 00000001]  
ev6__i_ctl__vptb_sext15__s     = [00000000 0000003F]  
ev6__i_ctl__vptb_sext15__v     = [00000000 00000001]  
ev6__i_ctl__vptb_sext1__m      = [00000000 00000001]  
ev6__i_ctl__vptb_sext1__s      = [00000000 00000031]  
ev6__i_ctl__vptb_sext1__v      = [00000000 00000001]  
ev6__i_ctl__vptb_sext2__m      = [00000000 00000001]  
ev6__i_ctl__vptb_sext2__s      = [00000000 00000032]  
ev6__i_ctl__vptb_sext2__v      = [00000000 00000001]  
ev6__i_ctl__vptb_sext3__m      = [00000000 00000001]  
ev6__i_ctl__vptb_sext3__s      = [00000000 00000033]  
ev6__i_ctl__vptb_sext3__v      = [00000000 00000001]  
ev6__i_ctl__vptb_sext4__m      = [00000000 00000001]  
ev6__i_ctl__vptb_sext4__s      = [00000000 00000034]  
ev6__i_ctl__vptb_sext4__v      = [00000000 00000001]  
ev6__i_ctl__vptb_sext5__m      = [00000000 00000001]  
ev6__i_ctl__vptb_sext5__s      = [00000000 00000035]  
ev6__i_ctl__vptb_sext5__v      = [00000000 00000001]  
ev6__i_ctl__vptb_sext6__m      = [00000000 00000001]  
ev6__i_ctl__vptb_sext6__s      = [00000000 00000036]  
ev6__i_ctl__vptb_sext6__v      = [00000000 00000001]  
ev6__i_ctl__vptb_sext7__m      = [00000000 00000001]  
ev6__i_ctl__vptb_sext7__s      = [00000000 00000037]  
ev6__i_ctl__vptb_sext7__v      = [00000000 00000001]  
ev6__i_ctl__vptb_sext8__m      = [00000000 00000001]  
ev6__i_ctl__vptb_sext8__s      = [00000000 00000038]  
ev6__i_ctl__vptb_sext8__v      = [00000000 00000001]  
ev6__i_ctl__vptb_sext9__m      = [00000000 00000001]  
ev6__i_ctl__vptb_sext9__s      = [00000000 00000039]  
ev6__i_ctl__vptb_sext9__v      = [00000000 00000001]  
ev6__i_stat                    = [00000000 00001610]  
ev6__i_stat__dpe__s            = [00000000 0000001E]  
ev6__i_stat__icm__m            = [00000000 00000001]  
ev6__i_stat__icm__s            = [00000000 00000021]  
ev6__i_stat__icm__v            = [00000000 00000001]  
ev6__i_stat__ls0__m            = [00000000 00000001]  
ev6__i_stat__ls0__s            = [00000000 00000026]  
ev6__i_stat__ls0__v            = [00000000 00000001]  
ev6__i_stat__mis__m            = [00000000 00000001]  
ev6__i_stat__mis__s            = [00000000 00000028]  
ev6__i_stat__mis__v            = [00000000 00000001]  
ev6__i_stat__ovr__m            = [00000000 00000007]  
ev6__i_stat__ovr__s            = [00000000 0000001E]  
ev6__i_stat__ovr__v            = [00000000 00000003]  
ev6__i_stat__par__m            = [00000000 00000001]  
ev6__i_stat__par__s            = [00000000 0000001D]  
ev6__i_stat__par__v            = [00000000 00000001]  
ev6__i_stat__prfme__m          = [00000000 000007FF]  
ev6__i_stat__prfme__s          = [00000000 0000001E]  
ev6__i_stat__prfme__v          = [00000000 0000000B]  
ev6__i_stat__rsv1__m           = [00000000 1FFFFFFF]  
ev6__i_stat__rsv1__s           = [00000000 00000000]  
ev6__i_stat__rsv1__v           = [00000000 0000001D]  
ev6__i_stat__rsv2__m           = [00000000 007FFFFF]  
ev6__i_stat__rsv2__s           = [00000000 00000029]  
ev6__i_stat__rsv2__v           = [00000000 00000017]  
ev6__i_stat__tpe__s            = [00000000 0000001D]  
ev6__i_stat__trap_type__m      = [00000000 0000000F]  
ev6__i_stat__trap_type__s      = [00000000 00000022]  
ev6__i_stat__trap_type__v      = [00000000 00000004]  
ev6__i_stat__trp__m            = [00000000 00000001]  
ev6__i_stat__trp__s            = [00000000 00000027]  
ev6__i_stat__trp__v            = [00000000 00000001]  
ev6__i_stat__w1c               = [00000000 60000000]  
ev6__iacv_entry                = [00000000 00000480]  
ev6__ic_flush                  = [00000000 00001310]  
ev6__ic_flush__rsv__m          = [FFFFFFFF FFFFFFFF]  
ev6__ic_flush__rsv__s          = [00000000 00000000]  
ev6__ic_flush__rsv__v          = [00000000 00000040]  
ev6__ic_flush_asm              = [00000000 00001210]  
ev6__ic_flush_asm__rsv__m      = [FFFFFFFF FFFFFFFF]  
ev6__ic_flush_asm__rsv__s      = [00000000 00000000]  
ev6__ic_flush_asm__rsv__v      = [00000000 00000040]  
ev6__ier                       = [00000000 00000A10]  
ev6__ier__asten__m             = [00000000 00000001]  
ev6__ier__asten__s             = [00000000 0000000D]  
ev6__ier__asten__v             = [00000000 00000001]  
ev6__ier__cm__m                = [00000000 00000003]  
ev6__ier__cm__s                = [00000000 00000003]  
ev6__ier__cm__v                = [00000000 00000002]  
ev6__ier__cren__m              = [00000000 00000001]  
ev6__ier__cren__s              = [00000000 0000001F]  
ev6__ier__cren__v              = [00000000 00000001]  
ev6__ier__eien__m              = [00000000 0000003F]  
ev6__ier__eien__s              = [00000000 00000021]  
ev6__ier__eien__v              = [00000000 00000006]  
ev6__ier__init                 = [00000000 00000000]  
ev6__ier__pcen__m              = [00000000 00000003]  
ev6__ier__pcen__s              = [00000000 0000001D]  
ev6__ier__pcen__v              = [00000000 00000002]  
ev6__ier__rsv0__m              = [00000000 00000007]  
ev6__ier__rsv0__s              = [00000000 00000000]  
ev6__ier__rsv0__v              = [00000000 00000003]  
ev6__ier__rsv1__m              = [00000000 000000FF]  
ev6__ier__rsv1__s              = [00000000 00000005]  
ev6__ier__rsv1__v              = [00000000 00000008]  
ev6__ier__rsv2__m              = [00000000 01FFFFFF]  
ev6__ier__rsv2__s              = [00000000 00000027]  
ev6__ier__rsv2__v              = [00000000 00000019]  
ev6__ier__sien__m              = [00000000 00007FFF]  
ev6__ier__sien__s              = [00000000 0000000E]  
ev6__ier__sien__v              = [00000000 0000000F]  
ev6__ier__slen__m              = [00000000 00000001]  
ev6__ier__slen__s              = [00000000 00000020]  
ev6__ier__slen__v              = [00000000 00000001]  
ev6__ier_cm                    = [00000000 00000B10]  
ev6__ier_cm__asten__m          = [00000000 00000001]  
ev6__ier_cm__asten__s          = [00000000 0000000D]  
ev6__ier_cm__asten__v          = [00000000 00000001]  
ev6__ier_cm__cm__m             = [00000000 00000003]  
ev6__ier_cm__cm__s             = [00000000 00000003]  
ev6__ier_cm__cm__v             = [00000000 00000002]  
ev6__ier_cm__cren__m           = [00000000 00000001]  
ev6__ier_cm__cren__s           = [00000000 0000001F]  
ev6__ier_cm__cren__v           = [00000000 00000001]  
ev6__ier_cm__eien__m           = [00000000 0000003F]  
ev6__ier_cm__eien__s           = [00000000 00000021]  
ev6__ier_cm__eien__v           = [00000000 00000006]  
ev6__ier_cm__pcen__m           = [00000000 00000003]  
ev6__ier_cm__pcen__s           = [00000000 0000001D]  
ev6__ier_cm__pcen__v           = [00000000 00000002]  
ev6__ier_cm__rsv0__m           = [00000000 00000007]  
ev6__ier_cm__rsv0__s           = [00000000 00000000]  
ev6__ier_cm__rsv0__v           = [00000000 00000003]  
ev6__ier_cm__rsv1__m           = [00000000 000000FF]  
ev6__ier_cm__rsv1__s           = [00000000 00000005]  
ev6__ier_cm__rsv1__v           = [00000000 00000008]  
ev6__ier_cm__rsv2__m           = [00000000 01FFFFFF]  
ev6__ier_cm__rsv2__s           = [00000000 00000027]  
ev6__ier_cm__rsv2__v           = [00000000 00000019]  
ev6__ier_cm__sien__m           = [00000000 00007FFF]  
ev6__ier_cm__sien__s           = [00000000 0000000E]  
ev6__ier_cm__sien__v           = [00000000 0000000F]  
ev6__ier_cm__slen__m           = [00000000 00000001]  
ev6__ier_cm__slen__s           = [00000000 00000020]  
ev6__ier_cm__slen__v           = [00000000 00000001]  
ev6__interrupt_entry           = [00000000 00000680]  
ev6__isum                      = [00000000 00000D00]  
ev6__isum__aste__m             = [00000000 00000001]  
ev6__isum__aste__s             = [00000000 00000004]  
ev6__isum__aste__v             = [00000000 00000001]  
ev6__isum__astk__m             = [00000000 00000001]  
ev6__isum__astk__s             = [00000000 00000003]  
ev6__isum__astk__v             = [00000000 00000001]  
ev6__isum__asts__m             = [00000000 00000001]  
ev6__isum__asts__s             = [00000000 00000009]  
ev6__isum__asts__v             = [00000000 00000001]  
ev6__isum__astu__m             = [00000000 00000001]  
ev6__isum__astu__s             = [00000000 0000000A]  
ev6__isum__astu__v             = [00000000 00000001]  
ev6__isum__cr__m               = [00000000 00000001]  
ev6__isum__cr__s               = [00000000 0000001F]  
ev6__isum__cr__v               = [00000000 00000001]  
ev6__isum__ei__m               = [00000000 0000003F]  
ev6__isum__ei__s               = [00000000 00000021]  
ev6__isum__ei__v               = [00000000 00000006]  
ev6__isum__pc__m               = [00000000 00000003]  
ev6__isum__pc__s               = [00000000 0000001D]  
ev6__isum__pc__v               = [00000000 00000002]  
ev6__isum__rsv0__m             = [00000000 00000007]  
ev6__isum__rsv0__s             = [00000000 00000000]  
ev6__isum__rsv0__v             = [00000000 00000003]  
ev6__isum__rsv1__m             = [00000000 0000000F]  
ev6__isum__rsv1__s             = [00000000 00000005]  
ev6__isum__rsv1__v             = [00000000 00000004]  
ev6__isum__rsv2__m             = [00000000 00000007]  
ev6__isum__rsv2__s             = [00000000 0000000B]  
ev6__isum__rsv2__v             = [00000000 00000003]  
ev6__isum__rsv3__m             = [00000000 01FFFFFF]  
ev6__isum__rsv3__s             = [00000000 00000027]  
ev6__isum__rsv3__v             = [00000000 00000019]  
ev6__isum__si__m               = [00000000 00007FFF]  
ev6__isum__si__s               = [00000000 0000000E]  
ev6__isum__si__v               = [00000000 0000000F]  
ev6__isum__sl__m               = [00000000 00000001]  
ev6__isum__sl__s               = [00000000 00000020]  
ev6__isum__sl__v               = [00000000 00000001]  
ev6__itb_ia                    = [00000000 00000310]  
ev6__itb_ia__rsv__m            = [FFFFFFFF FFFFFFFF]  
ev6__itb_ia__rsv__s            = [00000000 00000000]  
ev6__itb_ia__rsv__v            = [00000000 00000040]  
ev6__itb_iap                   = [00000000 00000210]  
ev6__itb_iap__rsv__m           = [FFFFFFFF FFFFFFFF]  
ev6__itb_iap__rsv__s           = [00000000 00000000]  
ev6__itb_iap__rsv__v           = [00000000 00000040]  
ev6__itb_is                    = [00000000 00000450]  
ev6__itb_is__rsv1__m           = [00000000 00001FFF]  
ev6__itb_is__rsv1__s           = [00000000 00000000]  
ev6__itb_is__rsv1__v           = [00000000 0000000D]  
ev6__itb_is__rsv2__m           = [00000000 0000FFFF]  
ev6__itb_is__rsv2__s           = [00000000 00000030]  
ev6__itb_is__rsv2__v           = [00000000 00000010]  
ev6__itb_is__va__m             = [00000007 FFFFFFFF]  
ev6__itb_is__va__s             = [00000000 0000000D]  
ev6__itb_is__va__v             = [00000000 00000023]  
ev6__itb_miss_entry            = [00000000 00000580]  
ev6__itb_pte                   = [00000000 00000111]  
ev6__itb_pte__asm__m           = [00000000 00000001]  
ev6__itb_pte__asm__s           = [00000000 00000004]  
ev6__itb_pte__asm__v           = [00000000 00000001]  
ev6__itb_pte__ere__m           = [00000000 00000001]  
ev6__itb_pte__ere__s           = [00000000 00000009]  
ev6__itb_pte__ere__v           = [00000000 00000001]  
ev6__itb_pte__gh__m            = [00000000 00000003]  
ev6__itb_pte__gh__s            = [00000000 00000005]  
ev6__itb_pte__gh__v            = [00000000 00000002]  
ev6__itb_pte__kre__m           = [00000000 00000001]  
ev6__itb_pte__kre__s           = [00000000 00000008]  
ev6__itb_pte__kre__v           = [00000000 00000001]  
ev6__itb_pte__pfn__m           = [00000000 7FFFFFFF]  
ev6__itb_pte__pfn__s           = [00000000 0000000D]  
ev6__itb_pte__pfn__v           = [00000000 0000001F]  
ev6__itb_pte__rsv1__m          = [00000000 0000000F]  
ev6__itb_pte__rsv1__s          = [00000000 00000000]  
ev6__itb_pte__rsv1__v          = [00000000 00000004]  
ev6__itb_pte__rsv2__m          = [00000000 00000001]  
ev6__itb_pte__rsv2__s          = [00000000 00000007]  
ev6__itb_pte__rsv2__v          = [00000000 00000001]  
ev6__itb_pte__rsv3__m          = [00000000 00000001]  
ev6__itb_pte__rsv3__s          = [00000000 0000000C]  
ev6__itb_pte__rsv3__v          = [00000000 00000001]  
ev6__itb_pte__rsv4__m          = [00000000 000FFFFF]  
ev6__itb_pte__rsv4__s          = [00000000 0000002C]  
ev6__itb_pte__rsv4__v          = [00000000 00000014]  
ev6__itb_pte__sre__m           = [00000000 00000001]  
ev6__itb_pte__sre__s           = [00000000 0000000A]  
ev6__itb_pte__sre__v           = [00000000 00000001]  
ev6__itb_pte__ure__m           = [00000000 00000001]  
ev6__itb_pte__ure__s           = [00000000 0000000B]  
ev6__itb_pte__ure__v           = [00000000 00000001]  
ev6__itb_tag                   = [00000000 00000040]  
ev6__itb_tag__rsv1__m          = [00000000 00001FFF]  
ev6__itb_tag__rsv1__s          = [00000000 00000000]  
ev6__itb_tag__rsv1__v          = [00000000 0000000D]  
ev6__itb_tag__rsv2__m          = [00000000 0000FFFF]  
ev6__itb_tag__rsv2__s          = [00000000 00000030]  
ev6__itb_tag__rsv2__v          = [00000000 00000010]  
ev6__itb_tag__va__m            = [00000007 FFFFFFFF]  
ev6__itb_tag__va__s            = [00000000 0000000D]  
ev6__itb_tag__va__v            = [00000000 00000023]  
ev6__iva_form                  = [00000000 00000710]  
ev6__iva_form_32               = [00000000 00071010]  
ev6__iva_form_32__rsv1__m      = [00000000 00000007]  
ev6__iva_form_32__rsv1__s      = [00000000 00000000]  
ev6__iva_form_32__rsv1__v      = [00000000 00000003]  
ev6__iva_form_32__rsv2__m      = [00000000 000000FF]  
ev6__iva_form_32__rsv2__s      = [00000000 00000016]  
ev6__iva_form_32__rsv2__v      = [00000000 00000008]  
ev6__iva_form_32__va__m        = [00000000 0007FFFF]  
ev6__iva_form_32__va__s        = [00000000 00000003]  
ev6__iva_form_32__va__v        = [00000000 00000013]  
ev6__iva_form_32__vptb__m      = [00000003 FFFFFFFF]  
ev6__iva_form_32__vptb__s      = [00000000 0000001E]  
ev6__iva_form_32__vptb__v      = [00000000 00000022]  
ev6__iva_form_48               = [00000000 00071010]  
ev6__iva_form_48__rsv1__m      = [00000000 00000007]  
ev6__iva_form_48__rsv1__s      = [00000000 00000000]  
ev6__iva_form_48__rsv1__v      = [00000000 00000003]  
ev6__iva_form_48__va__m        = [00000007 FFFFFFFF]  
ev6__iva_form_48__va__s        = [00000000 00000003]  
ev6__iva_form_48__va__v        = [00000000 00000023]  
ev6__iva_form_48__va_sext0__m  = [00000000 00000001]  
ev6__iva_form_48__va_sext0__s  = [00000000 00000026]  
ev6__iva_form_48__va_sext0__v  = [00000000 00000001]  
ev6__iva_form_48__va_sext1__m  = [00000000 00000001]  
ev6__iva_form_48__va_sext1__s  = [00000000 00000027]  
ev6__iva_form_48__va_sext1__v  = [00000000 00000001]  
ev6__iva_form_48__va_sext2__m  = [00000000 00000001]  
ev6__iva_form_48__va_sext2__s  = [00000000 00000028]  
ev6__iva_form_48__va_sext2__v  = [00000000 00000001]  
ev6__iva_form_48__va_sext3__m  = [00000000 00000001]  
ev6__iva_form_48__va_sext3__s  = [00000000 00000029]  
ev6__iva_form_48__va_sext3__v  = [00000000 00000001]  
ev6__iva_form_48__va_sext4__m  = [00000000 00000001]  
ev6__iva_form_48__va_sext4__s  = [00000000 0000002A]  
ev6__iva_form_48__va_sext4__v  = [00000000 00000001]  
ev6__iva_form_48__vptb__m      = [00000000 001FFFFF]  
ev6__iva_form_48__vptb__s      = [00000000 0000002B]  
ev6__iva_form_48__vptb__v      = [00000000 00000015]  
ev6__iva_form_64               = [00000000 00000007]  
ev6__iva_form_64__rsv1__m      = [00000000 00000007]  
ev6__iva_form_64__rsv1__s      = [00000000 00000000]  
ev6__iva_form_64__rsv1__v      = [00000000 00000003]  
ev6__iva_form_64__va__m        = [00000000 FFFFFFFF]  
ev6__iva_form_64__va__s        = [00000000 00000003]  
ev6__iva_form_64__va__v        = [00000000 00000020]  
ev6__iva_form_64__va_sext0__m  = [00000000 00000001]  
ev6__iva_form_64__va_sext0__s  = [00000000 00000023]  
ev6__iva_form_64__va_sext0__v  = [00000000 00000001]  
ev6__iva_form_64__va_sext1__m  = [00000000 00000001]  
ev6__iva_form_64__va_sext1__s  = [00000000 00000024]  
ev6__iva_form_64__va_sext1__v  = [00000000 00000001]  
ev6__iva_form_64__va_sext2__m  = [00000000 00000001]  
ev6__iva_form_64__va_sext2__s  = [00000000 00000025]  
ev6__iva_form_64__va_sext2__v  = [00000000 00000001]  
ev6__iva_form_64__va_sext3__m  = [00000000 00000001]  
ev6__iva_form_64__va_sext3__s  = [00000000 00000026]  
ev6__iva_form_64__va_sext3__v  = [00000000 00000001]  
ev6__iva_form_64__va_sext4__m  = [00000000 00000001]  
ev6__iva_form_64__va_sext4__s  = [00000000 00000027]  
ev6__iva_form_64__va_sext4__v  = [00000000 00000001]  
ev6__iva_form_64__va_sext5__m  = [00000000 00000001]  
ev6__iva_form_64__va_sext5__s  = [00000000 00000028]  
ev6__iva_form_64__va_sext5__v  = [00000000 00000001]  
ev6__iva_form_64__va_sext6__m  = [00000000 00000001]  
ev6__iva_form_64__va_sext6__s  = [00000000 00000029]  
ev6__iva_form_64__va_sext6__v  = [00000000 00000001]  
ev6__iva_form_64__va_sext7__m  = [00000000 00000001]  
ev6__iva_form_64__va_sext7__s  = [00000000 0000002A]  
ev6__iva_form_64__va_sext7__v  = [00000000 00000001]  
ev6__iva_form_64__vptb__m      = [00000000 001FFFFF]  
ev6__iva_form_64__vptb__s      = [00000000 0000002B]  
ev6__iva_form_64__vptb__v      = [00000000 00000015]  
ev6__iva_form__rsv1__m         = [00000000 00000007]  
ev6__iva_form__rsv1__s         = [00000000 00000000]  
ev6__iva_form__rsv1__v         = [00000000 00000003]  
ev6__iva_form__va__m           = [00000000 3FFFFFFF]  
ev6__iva_form__va__s           = [00000000 00000003]  
ev6__iva_form__va__v           = [00000000 0000001E]  
ev6__iva_form__vptb__m         = [00000000 7FFFFFFF]  
ev6__iva_form__vptb__s         = [00000000 00000021]  
ev6__iva_form__vptb__v         = [00000000 0000001F]  
ev6__m_ctl                     = [00000000 00002840]  
ev6__m_ctl__init               = [00000000 00000008]  
ev6__m_ctl__rsv1__m            = [00000000 00000001]  
ev6__m_ctl__rsv1__s            = [00000000 00000000]  
ev6__m_ctl__rsv1__v            = [00000000 00000001]  
ev6__m_ctl__rsv2__m            = [03FFFFFF FFFFFFFF]  
ev6__m_ctl__rsv2__s            = [00000000 00000006]  
ev6__m_ctl__rsv2__v            = [00000000 0000003A]  
ev6__m_ctl__spe2__s            = [00000000 00000003]  
ev6__m_ctl__spe__m             = [00000000 00000007]  
ev6__m_ctl__spe__s             = [00000000 00000001]  
ev6__m_ctl__spe__v             = [00000000 00000003]  
ev6__m_ctl__spec_st_cons__m    = [00000000 00000003]  
ev6__m_ctl__spec_st_cons__s    = [00000000 00000004]  
ev6__m_ctl__spec_st_cons__v    = [00000000 00000002]  
ev6__mchk_entry                = [00000000 00000500]  
ev6__mm_stat                   = [00000000 00002700]  
ev6__mm_stat__acv__m           = [00000000 00000001]  
ev6__mm_stat__acv__s           = [00000000 00000001]  
ev6__mm_stat__acv__v           = [00000000 00000001]  
ev6__mm_stat__dc_tag_perr__m   = [00000000 00000001]  
ev6__mm_stat__dc_tag_perr__s   = [00000000 0000000A]  
ev6__mm_stat__dc_tag_perr__v   = [00000000 00000001]  
ev6__mm_stat__for__m           = [00000000 00000001]  
ev6__mm_stat__for__s           = [00000000 00000002]  
ev6__mm_stat__for__v           = [00000000 00000001]  
ev6__mm_stat__fow__m           = [00000000 00000001]  
ev6__mm_stat__fow__s           = [00000000 00000003]  
ev6__mm_stat__fow__v           = [00000000 00000001]  
ev6__mm_stat__opcode__m        = [00000000 0000003F]  
ev6__mm_stat__opcode__s        = [00000000 00000004]  
ev6__mm_stat__opcode__v        = [00000000 00000006]  
ev6__mm_stat__rsv1__m          = [001FFFFF FFFFFFFF]  
ev6__mm_stat__rsv1__s          = [00000000 0000000B]  
ev6__mm_stat__rsv1__v          = [00000000 00000035]  
ev6__mm_stat__wr__m            = [00000000 00000001]  
ev6__mm_stat__wr__s            = [00000000 00000000]  
ev6__mm_stat__wr__v            = [00000000 00000001]  
ev6__mt_fpcr_entry             = [00000000 00000700]  
ev6__opcdec_entry              = [00000000 00000400]  
ev6__pal_base                  = [00000000 00001010]  
ev6__pal_base__pal_base__m     = [00000000 1FFFFFFF]  
ev6__pal_base__pal_base__s     = [00000000 0000000F]  
ev6__pal_base__pal_base__v     = [00000000 0000001D]  
ev6__pal_base__rsv1__m         = [00000000 00007FFF]  
ev6__pal_base__rsv1__s         = [00000000 00000000]  
ev6__pal_base__rsv1__v         = [00000000 0000000F]  
ev6__pal_base__rsv2__m         = [00000000 000FFFFF]  
ev6__pal_base__rsv2__s         = [00000000 0000002C]  
ev6__pal_base__rsv2__v         = [00000000 00000014]  
ev6__pctr_ctl                  = [00000000 00001410]  
ev6__pctr_ctl__pctr0__m        = [00000000 000FFFFF]  
ev6__pctr_ctl__pctr0__s        = [00000000 0000001C]  
ev6__pctr_ctl__pctr0__v        = [00000000 00000014]  
ev6__pctr_ctl__pctr1__m        = [00000000 000FFFFF]  
ev6__pctr_ctl__pctr1__s        = [00000000 00000006]  
ev6__pctr_ctl__pctr1__v        = [00000000 00000014]  
ev6__pctr_ctl__pm_kill__m      = [00000000 00000001]  
ev6__pctr_ctl__pm_kill__s      = [00000000 0000001A]  
ev6__pctr_ctl__pm_kill__v      = [00000000 00000001]  
ev6__pctr_ctl__pm_stall__m     = [00000000 00000001]  
ev6__pctr_ctl__pm_stall__s     = [00000000 0000001B]  
ev6__pctr_ctl__pm_stall__v     = [00000000 00000001]  
ev6__pctr_ctl__rsv1__m         = [00000000 00000001]  
ev6__pctr_ctl__rsv1__s         = [00000000 00000005]  
ev6__pctr_ctl__rsv1__v         = [00000000 00000001]  
ev6__pctr_ctl__rsv2__m         = [00000000 0000FFFF]  
ev6__pctr_ctl__rsv2__s         = [00000000 00000030]  
ev6__pctr_ctl__rsv2__v         = [00000000 00000010]  
ev6__pctr_ctl__sl0__m          = [00000000 00000001]  
ev6__pctr_ctl__sl0__s          = [00000000 00000004]  
ev6__pctr_ctl__sl0__v          = [00000000 00000001]  
ev6__pctr_ctl__sl1__m          = [00000000 00000003]  
ev6__pctr_ctl__sl1__s          = [00000000 00000002]  
ev6__pctr_ctl__sl1__v          = [00000000 00000002]  
ev6__pctr_ctl__tak__m          = [00000000 00000001]  
ev6__pctr_ctl__tak__s          = [00000000 00000000]  
ev6__pctr_ctl__tak__v          = [00000000 00000001]  
ev6__pctr_ctl__val__m          = [00000000 00000001]  
ev6__pctr_ctl__val__s          = [00000000 00000001]  
ev6__pctr_ctl__val__v          = [00000000 00000001]  
ev6__pctx__init                = [00000000 00000004]  
ev6__pmpc                      = [00000000 00000510]  
ev6__pmpc__pal__m              = [00000000 00000001]  
ev6__pmpc__pal__s              = [00000000 00000000]  
ev6__pmpc__pal__v              = [00000000 00000001]  
ev6__pmpc__pc__m               = [3FFFFFFF FFFFFFFF]  
ev6__pmpc__pc__s               = [00000000 00000002]  
ev6__pmpc__pc__v               = [00000000 0000003E]  
ev6__pmpc__rsv__m              = [00000000 00000001]  
ev6__pmpc__rsv__s              = [00000000 00000001]  
ev6__pmpc__rsv__v              = [00000000 00000001]  
ev6__powerup_entry             = [00000000 00000000]  
ev6__ppce                      = [00000000 00004810]  
ev6__ppce__asn__m              = [00000000 000000FF]  
ev6__ppce__asn__s              = [00000000 00000027]  
ev6__ppce__asn__v              = [00000000 00000008]  
ev6__ppce__aster__m            = [00000000 0000000F]  
ev6__ppce__aster__s            = [00000000 00000005]  
ev6__ppce__aster__v            = [00000000 00000004]  
ev6__ppce__astrr__m            = [00000000 0000000F]  
ev6__ppce__astrr__s            = [00000000 00000009]  
ev6__ppce__astrr__v            = [00000000 00000004]  
ev6__ppce__fpe__m              = [00000000 00000001]  
ev6__ppce__fpe__s              = [00000000 00000002]  
ev6__ppce__fpe__v              = [00000000 00000001]  
ev6__ppce__ppce__m             = [00000000 00000001]  
ev6__ppce__ppce__s             = [00000000 00000001]  
ev6__ppce__ppce__v             = [00000000 00000001]  
ev6__ppce__rsv0__m             = [00000000 00000001]  
ev6__ppce__rsv0__s             = [00000000 00000000]  
ev6__ppce__rsv0__v             = [00000000 00000001]  
ev6__ppce__rsv1__m             = [00000000 00000003]  
ev6__ppce__rsv1__s             = [00000000 00000003]  
ev6__ppce__rsv1__v             = [00000000 00000002]  
ev6__ppce__rsv2__m             = [00000000 03FFFFFF]  
ev6__ppce__rsv2__s             = [00000000 0000000D]  
ev6__ppce__rsv2__v             = [00000000 0000001A]  
ev6__ppce__rsv3__m             = [00000000 0001FFFF]  
ev6__ppce__rsv3__s             = [00000000 0000002F]  
ev6__ppce__rsv3__v             = [00000000 00000011]  
ev6__ppce_fpe                  = [00000000 00005810]  
ev6__ppce_fpe__asn__m          = [00000000 000000FF]  
ev6__ppce_fpe__asn__s          = [00000000 00000027]  
ev6__ppce_fpe__asn__v          = [00000000 00000008]  
ev6__ppce_fpe__aster__m        = [00000000 0000000F]  
ev6__ppce_fpe__aster__s        = [00000000 00000005]  
ev6__ppce_fpe__aster__v        = [00000000 00000004]  
ev6__ppce_fpe__astrr__m        = [00000000 0000000F]  
ev6__ppce_fpe__astrr__s        = [00000000 00000009]  
ev6__ppce_fpe__astrr__v        = [00000000 00000004]  
ev6__ppce_fpe__fpe__m          = [00000000 00000001]  
ev6__ppce_fpe__fpe__s          = [00000000 00000002]  
ev6__ppce_fpe__fpe__v          = [00000000 00000001]  
ev6__ppce_fpe__ppce__m         = [00000000 00000001]  
ev6__ppce_fpe__ppce__s         = [00000000 00000001]  
ev6__ppce_fpe__ppce__v         = [00000000 00000001]  
ev6__ppce_fpe__rsv0__m         = [00000000 00000001]  
ev6__ppce_fpe__rsv0__s         = [00000000 00000000]  
ev6__ppce_fpe__rsv0__v         = [00000000 00000001]  
ev6__ppce_fpe__rsv1__m         = [00000000 00000003]  
ev6__ppce_fpe__rsv1__s         = [00000000 00000003]  
ev6__ppce_fpe__rsv1__v         = [00000000 00000002]  
ev6__ppce_fpe__rsv2__m         = [00000000 03FFFFFF]  
ev6__ppce_fpe__rsv2__s         = [00000000 0000000D]  
ev6__ppce_fpe__rsv2__v         = [00000000 0000001A]  
ev6__ppce_fpe__rsv3__m         = [00000000 0001FFFF]  
ev6__ppce_fpe__rsv3__s         = [00000000 0000002F]  
ev6__ppce_fpe__rsv3__v         = [00000000 00000011]  
ev6__process_context           = [00000000 00005F10]  
ev6__process_context__asn__m   = [00000000 000000FF]  
ev6__process_context__asn__s   = [00000000 00000027]  
ev6__process_context__asn__v   = [00000000 00000008]  
ev6__process_context__aster__m = [00000000 0000000F]  
ev6__process_context__aster__s = [00000000 00000005]  
ev6__process_context__aster__v = [00000000 00000004]  
ev6__process_context__astrr__m = [00000000 0000000F]  
ev6__process_context__astrr__s = [00000000 00000009]  
ev6__process_context__astrr__v = [00000000 00000004]  
ev6__process_context__fpe__m   = [00000000 00000001]  
ev6__process_context__fpe__s   = [00000000 00000002]  
ev6__process_context__fpe__v   = [00000000 00000001]  
ev6__process_context__ppce__m  = [00000000 00000001]  
ev6__process_context__ppce__s  = [00000000 00000001]  
ev6__process_context__ppce__v  = [00000000 00000001]  
ev6__process_context__rsv0__m  = [00000000 00000001]  
ev6__process_context__rsv0__s  = [00000000 00000000]  
ev6__process_context__rsv0__v  = [00000000 00000001]  
ev6__process_context__rsv1__m  = [00000000 00000003]  
ev6__process_context__rsv1__s  = [00000000 00000003]  
ev6__process_context__rsv1__v  = [00000000 00000002]  
ev6__process_context__rsv2__m  = [00000000 03FFFFFF]  
ev6__process_context__rsv2__s  = [00000000 0000000D]  
ev6__process_context__rsv2__v  = [00000000 0000001A]  
ev6__process_context__rsv3__m  = [00000000 0001FFFF]  
ev6__process_context__rsv3__s  = [00000000 0000002F]  
ev6__process_context__rsv3__v  = [00000000 00000011]  
ev6__ps                        = [00000000 00000910]  
ev6__ps__asten__m              = [00000000 00000001]  
ev6__ps__asten__s              = [00000000 0000000D]  
ev6__ps__asten__v              = [00000000 00000001]  
ev6__ps__cm__m                 = [00000000 00000003]  
ev6__ps__cm__s                 = [00000000 00000003]  
ev6__ps__cm__v                 = [00000000 00000002]  
ev6__ps__cren__m               = [00000000 00000001]  
ev6__ps__cren__s               = [00000000 0000001F]  
ev6__ps__cren__v               = [00000000 00000001]  
ev6__ps__eien__m               = [00000000 0000003F]  
ev6__ps__eien__s               = [00000000 00000021]  
ev6__ps__eien__v               = [00000000 00000006]  
ev6__ps__pcen__m               = [00000000 00000003]  
ev6__ps__pcen__s               = [00000000 0000001D]  
ev6__ps__pcen__v               = [00000000 00000002]  
ev6__ps__rsv0__m               = [00000000 00000007]  
ev6__ps__rsv0__s               = [00000000 00000000]  
ev6__ps__rsv0__v               = [00000000 00000003]  
ev6__ps__rsv1__m               = [00000000 000000FF]  
ev6__ps__rsv1__s               = [00000000 00000005]  
ev6__ps__rsv1__v               = [00000000 00000008]  
ev6__ps__rsv2__m               = [00000000 01FFFFFF]  
ev6__ps__rsv2__s               = [00000000 00000027]  
ev6__ps__rsv2__v               = [00000000 00000019]  
ev6__ps__sien__m               = [00000000 00007FFF]  
ev6__ps__sien__s               = [00000000 0000000E]  
ev6__ps__sien__v               = [00000000 0000000F]  
ev6__ps__slen__m               = [00000000 00000001]  
ev6__ps__slen__s               = [00000000 00000020]  
ev6__ps__slen__v               = [00000000 00000001]  
ev6__reset_entry               = [00000000 00000780]  
ev6__shift_control             = [00000000 00002C40]  
ev6__shift_control__c_shift__m = [00000000 00000001]  
ev6__shift_control__c_shift__s = [00000000 00000000]  
ev6__shift_control__c_shift__v = [00000000 00000001]  
ev6__shift_control__rsv1__m    = [7FFFFFFF FFFFFFFF]  
ev6__shift_control__rsv1__s    = [00000000 00000001]  
ev6__shift_control__rsv1__v    = [00000000 0000003F]  
ev6__sirr                      = [00000000 00000C10]  
ev6__sirr__rsv1__m             = [00000000 00003FFF]  
ev6__sirr__rsv1__s             = [00000000 00000000]  
ev6__sirr__rsv1__v             = [00000000 0000000E]  
ev6__sirr__rsv2__m             = [00000007 FFFFFFFF]  
ev6__sirr__rsv2__s             = [00000000 0000001D]  
ev6__sirr__rsv2__v             = [00000000 00000023]  
ev6__sirr__sir__m              = [00000000 00007FFF]  
ev6__sirr__sir__s              = [00000000 0000000E]  
ev6__sirr__sir__v              = [00000000 0000000F]  
ev6__sleep                     = [00000000 000017F0]  
ev6__sleep__rsv__m             = [FFFFFFFF FFFFFFFF]  
ev6__sleep__rsv__s             = [00000000 00000000]  
ev6__sleep__rsv__v             = [00000000 00000040]  
ev6__unalign_entry             = [00000000 00000280]  
ev6__va                        = [00000000 0000C2F0]  
ev6__va__addr__m               = [FFFFFFFF FFFFFFFF]  
ev6__va__addr__s               = [00000000 00000000]  
ev6__va__addr__v               = [00000000 00000040]  
ev6__va_ctl                    = [00000000 0000C420]  
ev6__va_ctl__b_endian__m       = [00000000 00000001]  
ev6__va_ctl__b_endian__s       = [00000000 00000000]  
ev6__va_ctl__b_endian__v       = [00000000 00000001]  
ev6__va_ctl__init              = [00000000 00000002]  
ev6__va_ctl__rsv1__m           = [00000000 07FFFFFF]  
ev6__va_ctl__rsv1__s           = [00000000 00000003]  
ev6__va_ctl__rsv1__v           = [00000000 0000001B]  
ev6__va_ctl__va_48__m          = [00000000 00000001]  
ev6__va_ctl__va_48__s          = [00000000 00000001]  
ev6__va_ctl__va_48__v          = [00000000 00000001]  
ev6__va_ctl__va_form_32__m     = [00000000 00000001]  
ev6__va_ctl__va_form_32__s     = [00000000 00000002]  
ev6__va_ctl__va_form_32__v     = [00000000 00000001]  
ev6__va_ctl__vptb__m           = [00000003 FFFFFFFF]  
ev6__va_ctl__vptb__s           = [00000000 0000001E]  
ev6__va_ctl__vptb__v           = [00000000 00000022]  
ev6__va_form                   = [00000000 0000C3F0]  
ev6__va_form_32                = [00000000 00C3F0F0]  
ev6__va_form_32__rsv1__m       = [00000000 00000007]  
ev6__va_form_32__rsv1__s       = [00000000 00000000]  
ev6__va_form_32__rsv1__v       = [00000000 00000003]  
ev6__va_form_32__rsv2__m       = [00000000 000000FF]  
ev6__va_form_32__rsv2__s       = [00000000 00000016]  
ev6__va_form_32__rsv2__v       = [00000000 00000008]  
ev6__va_form_32__va__m         = [00000000 0007FFFF]  
ev6__va_form_32__va__s         = [00000000 00000003]  
ev6__va_form_32__va__v         = [00000000 00000013]  
ev6__va_form_32__vptb__m       = [00000003 FFFFFFFF]  
ev6__va_form_32__vptb__s       = [00000000 0000001E]  
ev6__va_form_32__vptb__v       = [00000000 00000022]  
ev6__va_form_48                = [00000000 00C3F0F0]  
ev6__va_form_48__rsv1__m       = [00000000 00000007]  
ev6__va_form_48__rsv1__s       = [00000000 00000000]  
ev6__va_form_48__rsv1__v       = [00000000 00000003]  
ev6__va_form_48__va__m         = [00000007 FFFFFFFF]  
ev6__va_form_48__va__s         = [00000000 00000003]  
ev6__va_form_48__va__v         = [00000000 00000023]  
ev6__va_form_48__va_sext0__m   = [00000000 00000001]  
ev6__va_form_48__va_sext0__s   = [00000000 00000026]  
ev6__va_form_48__va_sext0__v   = [00000000 00000001]  
ev6__va_form_48__va_sext1__m   = [00000000 00000001]  
ev6__va_form_48__va_sext1__s   = [00000000 00000027]  
ev6__va_form_48__va_sext1__v   = [00000000 00000001]  
ev6__va_form_48__va_sext2__m   = [00000000 00000001]  
ev6__va_form_48__va_sext2__s   = [00000000 00000028]  
ev6__va_form_48__va_sext2__v   = [00000000 00000001]  
ev6__va_form_48__va_sext3__m   = [00000000 00000001]  
ev6__va_form_48__va_sext3__s   = [00000000 00000029]  
ev6__va_form_48__va_sext3__v   = [00000000 00000001]  
ev6__va_form_48__va_sext4__m   = [00000000 00000001]  
ev6__va_form_48__va_sext4__s   = [00000000 0000002A]  
ev6__va_form_48__va_sext4__v   = [00000000 00000001]  
ev6__va_form_48__vptb__m       = [00000000 001FFFFF]  
ev6__va_form_48__vptb__s       = [00000000 0000002B]  
ev6__va_form_48__vptb__v       = [00000000 00000015]  
ev6__va_form_64                = [00000000 000000C3]  
ev6__va_form_64__rsv1__m       = [00000000 00000007]  
ev6__va_form_64__rsv1__s       = [00000000 00000000]  
ev6__va_form_64__rsv1__v       = [00000000 00000003]  
ev6__va_form_64__va__m         = [00000000 FFFFFFFF]  
ev6__va_form_64__va__s         = [00000000 00000003]  
ev6__va_form_64__va__v         = [00000000 00000020]  
ev6__va_form_64__va_sext0__m   = [00000000 00000001]  
ev6__va_form_64__va_sext0__s   = [00000000 00000023]  
ev6__va_form_64__va_sext0__v   = [00000000 00000001]  
ev6__va_form_64__va_sext1__m   = [00000000 00000001]  
ev6__va_form_64__va_sext1__s   = [00000000 00000024]  
ev6__va_form_64__va_sext1__v   = [00000000 00000001]  
ev6__va_form_64__va_sext2__m   = [00000000 00000001]  
ev6__va_form_64__va_sext2__s   = [00000000 00000025]  
ev6__va_form_64__va_sext2__v   = [00000000 00000001]  
ev6__va_form_64__va_sext3__m   = [00000000 00000001]  
ev6__va_form_64__va_sext3__s   = [00000000 00000026]  
ev6__va_form_64__va_sext3__v   = [00000000 00000001]  
ev6__va_form_64__va_sext4__m   = [00000000 00000001]  
ev6__va_form_64__va_sext4__s   = [00000000 00000027]  
ev6__va_form_64__va_sext4__v   = [00000000 00000001]  
ev6__va_form_64__va_sext5__m   = [00000000 00000001]  
ev6__va_form_64__va_sext5__s   = [00000000 00000028]  
ev6__va_form_64__va_sext5__v   = [00000000 00000001]  
ev6__va_form_64__va_sext6__m   = [00000000 00000001]  
ev6__va_form_64__va_sext6__s   = [00000000 00000029]  
ev6__va_form_64__va_sext6__v   = [00000000 00000001]  
ev6__va_form_64__va_sext7__m   = [00000000 00000001]  
ev6__va_form_64__va_sext7__s   = [00000000 0000002A]  
ev6__va_form_64__va_sext7__v   = [00000000 00000001]  
ev6__va_form_64__vptb__m       = [00000000 001FFFFF]  
ev6__va_form_64__vptb__s       = [00000000 0000002B]  
ev6__va_form_64__vptb__v       = [00000000 00000015]  
ev6__va_form__rsv1__m          = [00000000 00000007]  
ev6__va_form__rsv1__s          = [00000000 00000000]  
ev6__va_form__rsv1__v          = [00000000 00000003]  
ev6__va_form__va__m            = [00000000 3FFFFFFF]  
ev6__va_form__va__s            = [00000000 00000003]  
ev6__va_form__va__v            = [00000000 0000001E]  
ev6__va_form__vptb__m          = [00000000 7FFFFFFF]  
ev6__va_form__vptb__s          = [00000000 00000021]  
ev6__va_form__vptb__v          = [00000000 0000001F]  
ev6__wakeup_entry              = [00000000 00000780]  
ev6_p1                         = [00000000 00000000]  
ev6_p2                         = [00000000 00000001]  
ev6_p3                         = [00000000 00000000]  
ev6_scb__asn                   = [00000000 00000010]  
ev6_scb__aster                 = [00000000 00000010]  
ev6_scb__astrr                 = [00000000 00000010]  
ev6_scb__cc                    = [00000000 00000020]  
ev6_scb__cc_ctl                = [00000000 00000020]  
ev6_scb__clr_map               = [00000000 000000F0]  
ev6_scb__data                  = [00000000 00000040]  
ev6_scb__dc_ctl                = [00000000 00000040]  
ev6_scb__dc_stat               = [00000000 00000040]  
ev6_scb__dtb_alt_mode          = [00000000 00000040]  
ev6_scb__dtb_asn0              = [00000000 00000010]  
ev6_scb__dtb_asn1              = [00000000 00000080]  
ev6_scb__dtb_ia                = [00000000 00000080]  
ev6_scb__dtb_iap               = [00000000 00000080]  
ev6_scb__dtb_is0               = [00000000 00000040]  
ev6_scb__dtb_is1               = [00000000 00000080]  
ev6_scb__dtb_pte0              = [00000000 00000011]  
ev6_scb__dtb_pte1              = [00000000 00000088]  
ev6_scb__dtb_tag0              = [00000000 00000044]  
ev6_scb__dtb_tag1              = [00000000 00000022]  
ev6_scb__exc_addr              = [00000000 00000000]  
ev6_scb__exc_sum               = [00000000 00000000]  
ev6_scb__fpe                   = [00000000 00000010]  
ev6_scb__hw_int_clr            = [00000000 00000010]  
ev6_scb__i_ctl                 = [00000000 00000010]  
ev6_scb__i_stat                = [00000000 00000010]  
ev6_scb__ic_flush              = [00000000 00000010]  
ev6_scb__ic_flush_asm          = [00000000 00000010]  
ev6_scb__ier                   = [00000000 00000010]  
ev6_scb__ier_cm                = [00000000 00000010]  
ev6_scb__isum                  = [00000000 00000000]  
ev6_scb__itb_ia                = [00000000 00000010]  
ev6_scb__itb_iap               = [00000000 00000010]  
ev6_scb__itb_is                = [00000000 00000050]  
ev6_scb__itb_pte               = [00000000 00000011]  
ev6_scb__itb_tag               = [00000000 00000040]  
ev6_scb__iva_form              = [00000000 00000010]  
ev6_scb__m_ctl                 = [00000000 00000040]  
ev6_scb__mm_stat               = [00000000 00000000]  
ev6_scb__pal_base              = [00000000 00000010]  
ev6_scb__pctr_ctl              = [00000000 00000010]  
ev6_scb__pmpc                  = [00000000 00000010]  
ev6_scb__ppce                  = [00000000 00000010]  
ev6_scb__process_context       = [00000000 00000010]  
ev6_scb__ps                    = [00000000 00000010]  
ev6_scb__shift_control         = [00000000 00000040]  
ev6_scb__sirr                  = [00000000 00000010]  
ev6_scb__sleep                 = [00000000 000000F0]  
ev6_scb__va                    = [00000000 000000F0]  
ev6_scb__va_ctl                = [00000000 00000020]  
ev6_scb__va_form               = [00000000 000000F0]  
exit_getchar                   = [00000000 00006CB0]  Branch Displacement at 00006C9C in PSECT 0000
                                                      Branch Displacement at 00006CA4 in PSECT 0000
exit_putchar                   = [00000000 00006CF4]  Branch Displacement at 00006CB8 in PSECT 0000
fen_cm_offset                  = [00000000 00000010]  
focus                          = [00000000 00000000]  
force_ecc                      = [00000000 00000001]  
force_multi_issue              = [00000000 00000000]  
force_path                     = [00000000 00000000]  
force_path2                    = [00000000 00000000]  
fp_cmov_cmp                    = [00000000 5C000500]  
fp_cmov_mask                   = [00000000 FC00FF00]  
fp_count                       = [00000000 00000000]  
fpe_shift                      = [00000000 00000002]  
get_bits                       = [00000000 00006C64]  Branch Displacement at 00006C88 in PSECT 0000
getchar                        = [00000000 00006C38]  Branch Displacement at 00006C14 in PSECT 0000
halt__callback                 = [00000000 00000021]  
halt__dbl_mchk                 = [00000000 00000006]  
halt__dc_tag_perr_from_pal     = [00000000 00000008]  
halt__hw_halt                  = [00000000 00000001]  
halt__jump0                    = [00000000 00000040]  
halt__ksp_inval                = [00000000 00000002]  
halt__lfu_start                = [00000000 00000023]  
halt__mchk_from_pal            = [00000000 00000007]  
halt__mpstart                  = [00000000 00000022]  
halt__ptbr_inval               = [00000000 00000004]  
halt__reset                    = [00000000 00000000]  
halt__scbb_inval               = [00000000 00000003]  
halt__start                    = [00000000 00000020]  
halt__sw_halt                  = [00000000 00000005]  
i                              = [00000000 0000001E]  
iacv_cm_offset                 = [00000000 00000010]  
initial_pcbb                   = [00000000 00000C00]  
int_cmov_cmp                   = [00000000 44000080]  
int_cmov_mask                  = [00000000 FC0001A0]  
ipl3                           = [00000000 0000000F]  
ipl4                           = [00000000 0000000D]  
ipl5                           = [00000000 00000001]  
ipl6                           = [00000000 00000001]  
ipl7                           = [00000000 00000000]  
ipl_offset                     = [00000000 00000D00]  
ipl_table                      = [00000000 00000D00]  
ipte_cm_offset                 = [00000000 00000010]  
irq_clk                        = [00000000 00000004]  
irq_dev                        = [00000000 00000002]  
irq_dev__m                     = [00000000 00000002]  
irq_err                        = [00000000 00000001]  
irq_ip                         = [00000000 00000008]  
irq_mask                       = [00000000 0000000F]  
irq_noclk                      = [00000000 0000000B]  
is_hal                         = [00000000 00000001]  
keypressed                     = [00000000 00006C1C]  Branch Displacement at 00006C90 in PSECT 0000
                                                      Branch Displacement at 00006D4C in PSECT 0000
kseg_hack                      = [00000000 00000000]  
level_bits                     = [00000000 0000000A]  
max_cpuid                      = [00000000 00000002]  
mc_m_base                      = [00000000 00000020]  
mc_m_block                     = [00000000 00000800]  
mc_m_cmp                       = [00000000 00001000]  
mc_m_cp                        = [00000000 00002000]  
mc_m_display                   = [00000000 00000002]  
mc_m_echo                      = [00000000 00000100]  
mc_m_follow_w_rd               = [00000000 00000040]  
mc_m_follow_w_wr               = [00000000 00000080]  
mc_m_loop                      = [00000000 00000004]  
mc_m_mt                        = [00000000 00004000]  
mc_m_notdata                   = [00000000 00000010]  
mc_m_qw                        = [00000000 00000001]  
mc_m_write                     = [00000000 00000200]  
mc_m_writeaddr                 = [00000000 00000008]  
mc_m_xm                        = [00000000 00000400]  
mc_v_base                      = [00000000 00000005]  
mc_v_block                     = [00000000 0000000B]  
mc_v_cmp                       = [00000000 0000000C]  
mc_v_cp                        = [00000000 0000000D]  
mc_v_display                   = [00000000 00000001]  
mc_v_echo                      = [00000000 00000008]  
mc_v_follow_w_rd               = [00000000 00000006]  
mc_v_follow_w_wr               = [00000000 00000007]  
mc_v_loop                      = [00000000 00000002]  
mc_v_mt                        = [00000000 0000000E]  
mc_v_notdata                   = [00000000 00000004]  
mc_v_qw                        = [00000000 00000000]  
mc_v_write                     = [00000000 00000009]  
mc_v_writeaddr                 = [00000000 00000003]  
mc_v_xm                        = [00000000 0000000A]  
mces__dpc__s                   = [00000000 00000003]  
mces__dsc__s                   = [00000000 00000004]  
mces__mchk__s                  = [00000000 00000000]  
mces__pce__s                   = [00000000 00000002]  
mces__sce__s                   = [00000000 00000001]  
mces_clear                     = [00000000 00000007]  
mces_dis                       = [00000000 00000018]  
mchk__base                     = [00000000 00000100]  
mchk__bugcheck                 = [00000000 0000008E]  
mchk__c_addr                   = [00000000 00000028]  
mchk__c_stat                   = [00000000 00000040]  
mchk__c_sts                    = [00000000 00000048]  
mchk__corr_ecc                 = [00000000 00000086]  
mchk__cpu_base                 = [00000000 00000018]  
mchk__dc0_syndrome             = [00000000 00000038]  
mchk__dc1_syndrome             = [00000000 00000030]  
mchk__dc_stat                  = [00000000 00000020]  
mchk__dc_tag_perr              = [00000000 0000009E]  
mchk__exc_addr                 = [00000000 00000058]  
mchk__flag_frame               = [00000000 00000000]  
mchk__i_ctl                    = [00000000 00000080]  
mchk__i_stat                   = [00000000 00000018]  
mchk__ier_cm                   = [00000000 00000060]  
mchk__istream_cmov             = [00000000 000000A0]  
mchk__istream_cmov_fault       = [00000000 000000A2]  
mchk__isum                     = [00000000 00000068]  
mchk__mchk_code                = [00000000 00000010]  
mchk__mm_stat                  = [00000000 00000050]  
mchk__offsets                  = [00000000 00000008]  
mchk__os_bugcheck              = [00000000 00000090]  
mchk__pal_base                 = [00000000 00000078]  
mchk__proc_hrd_err             = [00000000 00000098]  
mchk__process_context          = [00000000 00000088]  
mchk__reserved_0               = [00000000 00000070]  
mchk__reserved_1               = [00000000 00000090]  
mchk__reserved_2               = [00000000 00000098]  
mchk__rev                      = [00000000 00000001]  
mchk__size                     = [00000000 000000A0]  
mchk__sys_corr_ecc             = [00000000 00000204]  
mchk__sys_event                = [00000000 00000206]  
mchk__sys_hrd_err              = [00000000 00000202]  
mchk__system_base              = [00000000 000000A0]  
mchk__unknown                  = [00000000 0000008A]  
mchk_crd__base                 = [00000000 00000000]  
mchk_crd__c_addr               = [00000000 00000028]  
mchk_crd__c_stat               = [00000000 00000040]  
mchk_crd__c_sts                = [00000000 00000048]  
mchk_crd__cpu_base             = [00000000 00000018]  
mchk_crd__dc0_syndrome         = [00000000 00000038]  
mchk_crd__dc1_syndrome         = [00000000 00000030]  
mchk_crd__dc_stat              = [00000000 00000020]  
mchk_crd__flag_frame           = [00000000 00000000]  
mchk_crd__i_stat               = [00000000 00000018]  
mchk_crd__mchk_code            = [00000000 00000010]  
mchk_crd__mm_stat              = [00000000 00000050]  
mchk_crd__offsets              = [00000000 00000008]  
mchk_crd__rev                  = [00000000 00000001]  
mchk_crd__size                 = [00000000 00000058]  
mchk_crd__system_base          = [00000000 00000058]  
mchk_en                        = [00000000 00000000]  
new_func_code                  = [00000000 0000006E]  
no_dctag_par_en                = [00000000 00000003]  
opcdec_cm_offset               = [00000000 00000010]  
opcdec_offset                  = [00000000 00000418]  
opcode__hw_ld                  = [00000000 00000003]  
opcode__hw_st                  = [00000000 00000007]  
osf_a0__bpt                    = [00000000 00000000]  
osf_a0__bugchk                 = [00000000 00000001]  
osf_a0__fen                    = [00000000 00000003]  
osf_a0__gentrap                = [00000000 00000002]  
osf_a0__illop                  = [00000000 00000005]  
osf_a0__opdec                  = [00000000 00000004]  
osf_a0_int__clk                = [00000000 00000001]  
osf_a0_int__crd                = [00000000 00000002]  
osf_a0_int__dev                = [00000000 00000003]  
osf_a0_int__ip                 = [00000000 00000000]  
osf_a0_int__mchk               = [00000000 00000002]  
osf_a0_int__perfmon            = [00000000 00000004]  
osf_frm__a0                    = [00000000 00000018]  
osf_frm__a1                    = [00000000 00000020]  
osf_frm__a2                    = [00000000 00000028]  
osf_frm__gp                    = [00000000 00000010]  
osf_frm__pc                    = [00000000 00000008]  
osf_frm__ps                    = [00000000 00000000]  
osf_frm__r16                   = [00000000 00000018]  
osf_frm__r17                   = [00000000 00000020]  
osf_frm__r18                   = [00000000 00000028]  
osf_frm__size                  = [00000000 00000030]  
osf_ipl__clk                   = [00000000 00000005]  
osf_ipl__dev3                  = [00000000 00000003]  
osf_ipl__dev4                  = [00000000 00000004]  
osf_ipl__dev5                  = [00000000 00000005]  
osf_ipl__dev6                  = [00000000 00000006]  
osf_ipl__ip                    = [00000000 00000005]  
osf_ipl__mchk                  = [00000000 00000007]  
osf_ipl__mchk_crd              = [00000000 00000007]  
osf_ipl__perfmon               = [00000000 00000006]  
osf_mmcsr__acv                 = [00000000 00000001]  
osf_mmcsr__foe                 = [00000000 00000003]  
osf_mmcsr__for                 = [00000000 00000002]  
osf_mmcsr__fow                 = [00000000 00000004]  
osf_mmcsr__tnv                 = [00000000 00000000]  
osf_p_misc__cm__m              = [00000000 00000001]  
osf_p_misc__cm__s              = [00000000 00000003]  
osf_p_misc__ipl__m             = [00000000 00000007]  
osf_p_misc__ipl__s             = [00000000 00000000]  
osf_p_misc__mces__dpc__s       = [00000000 00000013]  
osf_p_misc__mces__dsc__s       = [00000000 00000014]  
osf_p_misc__mces__mchk__s      = [00000000 00000010]  
osf_p_misc__mces__pce__s       = [00000000 00000012]  
osf_p_misc__mces__rsv__m       = [00000000 00000007]  
osf_p_misc__mces__rsv__s       = [00000000 00000015]  
osf_p_misc__mces__sce__s       = [00000000 00000011]  
osf_p_misc__mchk_code__m       = [00000000 0000FFFF]  
osf_p_misc__mchk_code__s       = [00000000 00000028]  
osf_p_misc__phys__s            = [00000000 0000003F]  
osf_p_misc__ps__m              = [00000000 0000000F]  
osf_p_misc__ps__s              = [00000000 00000000]  
osf_p_misc__rsv__m             = [00000000 00000FFF]  
osf_p_misc__rsv__s             = [00000000 00000004]  
osf_p_misc__scbv__m            = [00000000 0000FFFF]  
osf_p_misc__scbv__s            = [00000000 00000018]  
osf_p_misc__switch__s          = [00000000 0000003E]  
osf_pal                        = [00000000 00000002]  
osf_pcb__asn                   = [00000000 0000001C]  
osf_pcb__asn__m                = [00000000 000000FF]  
osf_pcb__asn__s                = [00000000 00000020]  
osf_pcb__cpc                   = [00000000 00000018]  
osf_pcb__fen                   = [00000000 00000028]  
osf_pcb__fen__m                = [00000000 00000001]  
osf_pcb__fen__s                = [00000000 00000000]  
osf_pcb__ksp                   = [00000000 00000000]  
osf_pcb__pme__m                = [00000000 00000001]  
osf_pcb__pme__s                = [00000000 0000003E]  
osf_pcb__ptbr                  = [00000000 00000010]  
osf_pcb__rsv                   = [00000000 00000030]  
osf_pcb__stacks                = [00000000 00000000]  
osf_pcb__unq                   = [00000000 00000020]  
osf_pcb__usp                   = [00000000 00000008]  
osf_ps__cm__m                  = [00000000 00000001]  
osf_ps__cm__s                  = [00000000 00000003]  
osf_ps__ipl__m                 = [00000000 00000007]  
osf_ps__ipl__s                 = [00000000 00000000]  
osf_pte__asm__m                = [00000000 00000001]  
osf_pte__asm__s                = [00000000 00000004]  
osf_pte__foe__m                = [00000000 00000001]  
osf_pte__foe__s                = [00000000 00000003]  
osf_pte__for__m                = [00000000 00000001]  
osf_pte__for__s                = [00000000 00000001]  
osf_pte__fow__m                = [00000000 00000001]  
osf_pte__fow__s                = [00000000 00000002]  
osf_pte__gh__m                 = [00000000 00000003]  
osf_pte__gh__s                 = [00000000 00000005]  
osf_pte__kre__m                = [00000000 00000001]  
osf_pte__kre__s                = [00000000 00000008]  
osf_pte__kwe__m                = [00000000 00000001]  
osf_pte__kwe__s                = [00000000 0000000C]  
osf_pte__pfn__m                = [00000000 FFFFFFFF]  
osf_pte__pfn__s                = [00000000 00000020]  
osf_pte__prot__m               = [00000000 00003300]  
osf_pte__soft__m               = [00000000 0000FFFF]  
osf_pte__soft__s               = [00000000 00000010]  
osf_pte__ure__m                = [00000000 00000001]  
osf_pte__ure__s                = [00000000 00000009]  
osf_pte__uwe__m                = [00000000 00000001]  
osf_pte__uwe__s                = [00000000 0000000D]  
osf_pte__v__m                  = [00000000 00000001]  
osf_pte__v__s                  = [00000000 00000000]  
osf_svmin                      = [00000000 00000000]  
osfpal                         = [00000000 00000001]  
osfpal_func__bpt               = [00000000 00000080]  
osfpal_func__bugchk            = [00000000 00000081]  
osfpal_func__callsys           = [00000000 00000083]  
osfpal_func__cflush            = [00000000 00000001]  
osfpal_func__clrfen            = [00000000 000000AE]  
osfpal_func__cserve            = [00000000 00000009]  
osfpal_func__draina            = [00000000 00000002]  
osfpal_func__ecctest           = [00000000 00000087]  
osfpal_func__gentrap           = [00000000 000000AA]  
osfpal_func__halt              = [00000000 00000000]  
osfpal_func__imb               = [00000000 00000086]  
osfpal_func__rdmces            = [00000000 00000010]  
osfpal_func__rdps              = [00000000 00000036]  
osfpal_func__rdunique          = [00000000 0000009E]  
osfpal_func__rdusp             = [00000000 0000003A]  
osfpal_func__rdval             = [00000000 00000032]  
osfpal_func__retsys            = [00000000 0000003D]  
osfpal_func__rti               = [00000000 0000003F]  
osfpal_func__swpctx            = [00000000 00000030]  
osfpal_func__swpipl            = [00000000 00000035]  
osfpal_func__swppal            = [00000000 0000000A]  
osfpal_func__tbi               = [00000000 00000033]  
osfpal_func__urti              = [00000000 00000092]  
osfpal_func__whami             = [00000000 0000003C]  
osfpal_func__wrent             = [00000000 00000034]  
osfpal_func__wrfen             = [00000000 0000002B]  
osfpal_func__wripir            = [00000000 0000000D]  
osfpal_func__wrkgp             = [00000000 00000037]  
osfpal_func__wrmces            = [00000000 00000011]  
osfpal_func__wrperfmon         = [00000000 00000039]  
osfpal_func__wrunique          = [00000000 0000009F]  
osfpal_func__wrusp             = [00000000 00000038]  
osfpal_func__wrval             = [00000000 00000031]  
osfpal_func__wrvptptr          = [00000000 0000002D]  
osfpal_func__wtint             = [00000000 0000003E]  
osfpal_version_h               = [00000000 00020000]  
osfpal_version_l               = [00000000 00020132]  
outled                         = [00000000 00000001]  
p20                            = [00000000 00000014]  
p21                            = [00000000 00000015]  
p22                            = [00000000 00000016]  
p23                            = [00000000 00000017]  
p4                             = [00000000 00000004]  
p5                             = [00000000 00000005]  
p6                             = [00000000 00000006]  
p7                             = [00000000 00000007]  
p_misc                         = [00000000 00000016]  
p_temp                         = [00000000 00000015]  
pa_bits                        = [00000000 0000002C]  
page_offset_size_bits          = [00000000 0000000D]  
page_size_bytes                = [00000000 00002000]  
pal__console_base              = [00000000 00010000]  
pal__emul_base                 = [00000000 FFFFFFFF]  
pal__enter_osf                 = [00000000 0000C100]  
pal__impure_base               = [00000000 00004000]  
pal__impure_common_size        = [00000000 00000200]  
pal__impure_specific_size      = [00000000 00000600]  
pal__logout_base               = [00000000 00006000]  
pal__logout_specific_size      = [00000000 00000400]  
pal__osfpal_base               = [00000000 00008000]  
pal__pal_base                  = [00000000 00008000]  
pal__restore_fpcr              = [00000000 00004B8C]  Branch Displacement at 00004B88 in PSECT 0000
pal__restore_fpcr_done         = [00000000 00004B9C]  
pal__restore_state             = [00000000 00004B2C]  Branch Displacement at 000059C0 in PSECT 0000
                                                      Branch Displacement at 00006680 in PSECT 0000
                                                      Branch Displacement at 00006BC0 in PSECT 0000
pal__save_shadow               = [00000000 000048A0]  
pal__save_state                = [00000000 000047B0]  Branch Displacement at 00005798 in PSECT 0000
                                                      Branch Displacement at 00006580 in PSECT 0000
pal__temps_base                = [00000000 00007000]  
pal__temps_specific_size       = [00000000 00000200]  
pal_type                       = [00000000 00000002]  
pcv_index                      = [00000000 000000FB]  
pcv_jsr_arith_cm0              = [00000000 00000C2C]  
pcv_jsr_arith_cm0_inst         = [00000000 00000002]  
pcv_jsr_arith_fpcr0            = [00000000 00000C2A]  
pcv_jsr_arith_fpcr0_inst       = [00000000 00000002]  
pcv_jsr_auto0                  = [00000000 00001426]  
pcv_jsr_auto0_inst             = [00000000 00000002]  
pcv_jsr_bpt_cm0                = [00000000 00000C40]  
pcv_jsr_bpt_cm0_inst           = [00000000 00000002]  
pcv_jsr_callsys_cm0            = [00000000 00000C42]  
pcv_jsr_callsys_cm0_inst       = [00000000 00000002]  
pcv_jsr_cbox0                  = [00000000 00001418]  
pcv_jsr_cbox0_inst             = [00000000 00000002]  
pcv_jsr_dfault_cm0             = [00000000 00000C22]  
pcv_jsr_dfault_cm0_inst        = [00000000 00000002]  
pcv_jsr_dpte_cm0               = [00000000 00000C20]  
pcv_jsr_dpte_cm0_inst          = [00000000 00000002]  
pcv_jsr_fen_cm0                = [00000000 00000C1C]  
pcv_jsr_fen_cm0_inst           = [00000000 00000002]  
pcv_jsr_getchar0               = [00000000 00001428]  
pcv_jsr_getchar0_inst          = [00000000 00000003]  
pcv_jsr_iacv_cm0               = [00000000 00000C26]  
pcv_jsr_iacv_cm0_inst          = [00000000 00000002]  
pcv_jsr_index                  = [00000000 00000C66]  
pcv_jsr_ipte_cm0               = [00000000 00000C28]  
pcv_jsr_ipte_cm0_inst          = [00000000 00000002]  
pcv_jsr_key0                   = [00000000 00001429]  
pcv_jsr_key0_inst              = [00000000 00000002]  
pcv_jsr_opcdec_cm0             = [00000000 00000C24]  
pcv_jsr_opcdec_cm0_inst        = [00000000 00000002]  
pcv_jsr_post_cm0               = [00000000 00000C46]  
pcv_jsr_post_cm0_inst          = [00000000 00000002]  
pcv_jsr_putchar0               = [00000000 00001427]  
pcv_jsr_putchar0_inst          = [00000000 00000002]  
pcv_jsr_restore_fpcr0          = [00000000 00000C2F]  
pcv_jsr_restore_fpcr0_inst     = [00000000 00000002]  
pcv_jsr_restore_state0         = [00000000 00001401]  
pcv_jsr_restore_state0_inst    = [00000000 00000002]  
pcv_jsr_save_state0            = [00000000 000013FE]  
pcv_jsr_save_state0_inst       = [00000000 00000002]  
pcv_jsr_sbe_off0               = [00000000 00000C4F]  
pcv_jsr_sbe_off0_inst          = [00000000 00000002]  
pcv_jsr_scrub0                 = [00000000 00001419]  
pcv_jsr_scrub0_inst            = [00000000 00000002]  
pcv_jsr_tbi0                   = [00000000 00000C32]  
pcv_jsr_tbi0_inst              = [00000000 00000007]  
pcv_jsr_unalign_cm0            = [00000000 00000C1E]  
pcv_jsr_unalign_cm0_inst       = [00000000 00000002]  
pcv_jsr_wait0                  = [00000000 0000142A]  
pcv_jsr_wait0_inst             = [00000000 00000002]  
pcv_jsr_wrent0                 = [00000000 00000C39]  
pcv_jsr_wrent0_inst            = [00000000 00000007]  
pcv_rule                       = [00000000 0000001D]  
poll_h                         = [00000000 00006D60]  Branch Displacement at 00006D68 in PSECT 0000
                                                      Branch Displacement at 00006D94 in PSECT 0000
poll_l                         = [00000000 00006D74]  Branch Displacement at 00006D90 in PSECT 0000
poll_start                     = [00000000 00006D50]  Branch Displacement at 00006D58 in PSECT 0000
post_cm_offset                 = [00000000 00000010]  
ppce_shift                     = [00000000 0000003D]  
pt__call_pal_pc                = [00000000 00000140]  
pt__ch_mode                    = [00000000 00000130]  
pt__ch_sp                      = [00000000 00000138]  
pt__dtb_alt_mode               = [00000000 00000148]  
pt__ent_arith                  = [00000000 00000030]  
pt__ent_if                     = [00000000 00000038]  
pt__ent_int                    = [00000000 00000040]  
pt__ent_mm                     = [00000000 00000048]  
pt__ent_sys                    = [00000000 00000050]  
pt__ent_una                    = [00000000 00000058]  
pt__fault_pc                   = [00000000 00000150]  
pt__fault_r4                   = [00000000 00000160]  
pt__fault_r5                   = [00000000 00000168]  
pt__fault_scb                  = [00000000 00000158]  
pt__halt_code                  = [00000000 000000C8]  
pt__impure                     = [00000000 00000088]  
pt__kgp                        = [00000000 00000028]  
pt__ksp                        = [00000000 00000018]  
pt__m_ctl                      = [00000000 000000C0]  
pt__new_a0                     = [00000000 00000068]  
pt__new_a1                     = [00000000 00000070]  
pt__new_a2                     = [00000000 00000078]  
pt__new_ps                     = [00000000 00000128]  
pt__opcode                     = [00000000 000000E0]  
pt__p_misc                     = [00000000 00000090]  
pt__pcbb                       = [00000000 00000010]  
pt__pctr_flag                  = [00000000 00000190]  
pt__pctr_pend                  = [00000000 000001A0]  
pt__pctr_r4                    = [00000000 00000198]  
pt__pctr_save                  = [00000000 00000188]  
pt__pctr_vms                   = [00000000 000001A8]  
pt__prbr                       = [00000000 000000A8]  
pt__ptbr                       = [00000000 00000008]  
pt__r0                         = [00000000 000000E8]  
pt__r1                         = [00000000 000000F0]  
pt__r2                         = [00000000 000000F8]  
pt__r25                        = [00000000 00000118]  
pt__r26                        = [00000000 00000120]  
pt__r3                         = [00000000 00000100]  
pt__r8                         = [00000000 00000108]  
pt__r9                         = [00000000 00000110]  
pt__reg                        = [00000000 000000D8]  
pt__rsv_for_pal                = [00000000 00000178]  
pt__scbb                       = [00000000 00000170]  
pt__scc                        = [00000000 000000A0]  
pt__stack_pc                   = [00000000 00000060]  
pt__sys_event                  = [00000000 00000180]  
pt__sysval                     = [00000000 00000080]  
pt__trap                       = [00000000 000000B0]  
pt__usp                        = [00000000 00000020]  
pt__va_ctl                     = [00000000 000000B8]  
pt__vptb                       = [00000000 00000000]  
pt__vpte_pc                    = [00000000 000000D0]  
pt__whami                      = [00000000 00000098]  
pte_eco                        = [00000000 00000001]  
putchar                        = [00000000 00006CB4]  Branch Displacement at 00006C04 in PSECT 0000
pvc$osf0$2                     = [00000000 00000160]  
pvc$osf1$2                     = [00000000 00004080]  
pvc$osf10$3106                 = [00000000 00004318]  
pvc$osf100$1007                = [00000000 00003214]  
pvc$osf101$1007                = [00000000 00003254]  
pvc$osf102$1007                = [00000000 00003294]  
pvc$osf103$1007                = [00000000 000032D4]  
pvc$osf104$1007                = [00000000 00003314]  
pvc$osf105$1007                = [00000000 00003354]  
pvc$osf106$1007                = [00000000 00003394]  
pvc$osf107$1007                = [00000000 000033D4]  
pvc$osf108$1007                = [00000000 00003414]  
pvc$osf109$1007                = [00000000 00003454]  
pvc$osf11$3106.1               = [00000000 0000431C]  
pvc$osf110$1007                = [00000000 00003494]  
pvc$osf111$1007                = [00000000 000034D4]  
pvc$osf112$1007                = [00000000 00003514]  
pvc$osf113$1007                = [00000000 00003554]  
pvc$osf114$1007                = [00000000 00003594]  
pvc$osf115$1007                = [00000000 000035D4]  
pvc$osf116$1007                = [00000000 00003614]  
pvc$osf117$1007                = [00000000 00003654]  
pvc$osf118$1007                = [00000000 00003694]  
pvc$osf119$1007                = [00000000 000036D4]  
pvc$osf12$3108                 = [00000000 00000440]  
pvc$osf120$1007                = [00000000 00003714]  
pvc$osf121$1007                = [00000000 00003754]  
pvc$osf122$1007                = [00000000 00003794]  
pvc$osf123$1007                = [00000000 000037D4]  
pvc$osf124$1007                = [00000000 00003814]  
pvc$osf125$1007                = [00000000 00003854]  
pvc$osf126$1007                = [00000000 00003894]  
pvc$osf127$1007                = [00000000 000038D4]  
pvc$osf128$1007                = [00000000 00003914]  
pvc$osf129$1007                = [00000000 00003954]  
pvc$osf13$3108.1               = [00000000 00000444]  
pvc$osf130$1007                = [00000000 00003994]  
pvc$osf131$1007                = [00000000 000039D4]  
pvc$osf132$1007                = [00000000 00003A14]  
pvc$osf133$1007                = [00000000 00003A54]  
pvc$osf134$1007                = [00000000 00003A94]  
pvc$osf135$1007                = [00000000 00003AD4]  
pvc$osf136$1007                = [00000000 00003B14]  
pvc$osf137$1007                = [00000000 00003B54]  
pvc$osf138$1007                = [00000000 00003B94]  
pvc$osf139$1007                = [00000000 00003BD4]  
pvc$osf14$3110                 = [00000000 000044A8]  
pvc$osf140$1007                = [00000000 00003C14]  
pvc$osf141$1007                = [00000000 00003C54]  
pvc$osf142$1007                = [00000000 00003C94]  
pvc$osf143$1007                = [00000000 00003CD4]  
pvc$osf144$1007                = [00000000 00003D14]  
pvc$osf145$1007                = [00000000 00003D54]  
pvc$osf146$1007                = [00000000 00003D94]  
pvc$osf147$1007                = [00000000 00003DD4]  
pvc$osf148$1007                = [00000000 00003E14]  
pvc$osf149$1007                = [00000000 00003E54]  
pvc$osf15$3110.1               = [00000000 000044AC]  
pvc$osf150$1007                = [00000000 00003E94]  
pvc$osf151$1007                = [00000000 00003ED4]  
pvc$osf152$1007                = [00000000 00003F14]  
pvc$osf153$1007                = [00000000 00003F54]  
pvc$osf154$1007                = [00000000 00003F94]  
pvc$osf155$1007                = [00000000 00003FD4]  
pvc$osf156$1007                = [00000000 00004EA0]  
pvc$osf157$3122                = [00000000 00002CE4]  
pvc$osf158$3122.1              = [00000000 00004FC0]  
pvc$osf159$3122.2              = [00000000 00005000]  
pvc$osf16$2                    = [00000000 000005C0]  
pvc$osf160$3122.3              = [00000000 00005040]  
pvc$osf161$3122.4              = [00000000 00005080]  
pvc$osf162$3122.5              = [00000000 000050C0]  
pvc$osf163$3122.6              = [00000000 00005100]  
pvc$osf164$3129                = [00000000 00002D24]  
pvc$osf165$3129.1              = [00000000 00005140]  
pvc$osf166$3129.2              = [00000000 00005148]  
pvc$osf167$3129.3              = [00000000 00005150]  
pvc$osf168$3129.4              = [00000000 00005158]  
pvc$osf169$3129.5              = [00000000 00005160]  
pvc$osf17$2                    = [00000000 000045D0]  
pvc$osf170$3129.6              = [00000000 00005168]  
pvc$osf171$3136                = [00000000 00005568]  
pvc$osf172$3136.1              = [00000000 0000556C]  
pvc$osf173$3138                = [00000000 000030E8]  
pvc$osf174$3138.1              = [00000000 000030EC]  
pvc$osf175$5118                = [00000000 00005798]  
pvc$osf176$1007                = [00000000 0000585C]  
pvc$osf177$30                  = [00000000 000058D8]  
pvc$osf178$1006                = [00000000 000058F8]  
pvc$osf179$1006                = [00000000 000059B4]  
pvc$osf18$3112                 = [00000000 00004614]  
pvc$osf180$5121                = [00000000 000059C0]  
pvc$osf181$35                  = [00000000 00005B68]  
pvc$osf182$3142                = [00000000 00005B98]  
pvc$osf183$3142.1              = [00000000 00005B9C]  
pvc$osf184$5144                = [00000000 00005C00]  
pvc$osf185$2                   = [00000000 00005D40]  
pvc$osf186$5145                = [00000000 00005D58]  
pvc$osf187$1006                = [00000000 00005DB4]  
pvc$osf188$5144                = [00000000 00005DC0]  
pvc$osf189$5145.1              = [00000000 00005DD0]  
pvc$osf19$3112.1               = [00000000 00004618]  
pvc$osf190$35                  = [00000000 00005DDC]  
pvc$osf191$2                   = [00000000 00005ED0]  
pvc$osf192$5145                = [00000000 00005EE8]  
pvc$osf193$5144                = [00000000 00006000]  
pvc$osf194$35                  = [00000000 00006114]  
pvc$osf195$2                   = [00000000 00006280]  
pvc$osf196$1006                = [00000000 000062F4]  
pvc$osf197$5144                = [00000000 00006310]  
pvc$osf198$35                  = [00000000 00006320]  
pvc$osf199$3151                = [00000000 00006418]  
pvc$osf2$3100                  = [00000000 0000023C]  
pvc$osf20$3114                 = [00000000 000046A8]  
pvc$osf200$3151.1              = [00000000 0000641C]  
pvc$osf201$1006                = [00000000 000064B4]  
pvc$osf202$5144.1              = [00000000 000064D4]  
pvc$osf203$1007                = [00000000 00006554]  
pvc$osf204$5118                = [00000000 00006580]  
pvc$osf205$1007                = [00000000 00006648]  
pvc$osf206$5121                = [00000000 00006680]  
pvc$osf207$2                   = [00000000 000066B0]  
pvc$osf208$1007                = [00000000 000066E0]  
pvc$osf209$35                  = [00000000 000067A8]  
pvc$osf21$3114.1               = [00000000 000046AC]  
pvc$osf210$21                  = [00000000 000067C0]  
pvc$osf211$35                  = [00000000 000067F8]  
pvc$osf212$2                   = [00000000 000068D0]  
pvc$osf213$5144                = [00000000 0000690C]  
pvc$osf214$35                  = [00000000 000069B8]  
pvc$osf215$2                   = [00000000 00006A90]  
pvc$osf216$30                  = [00000000 00006B58]  
pvc$osf217$1006                = [00000000 00006B78]  
pvc$osf218$5121                = [00000000 00006BC0]  
pvc$osf219$5158                = [00000000 00006BE0]  
pvc$osf22$3116                 = [00000000 000046EC]  
pvc$osf220$5159                = [00000000 00006C04]  
pvc$osf221$5160                = [00000000 00006C14]  
pvc$osf222$11                  = [00000000 00006C2C]  
pvc$osf223$35                  = [00000000 00006C2C]  
pvc$osf224$29                  = [00000000 00006C34]  
pvc$osf225$5161.1              = [00000000 00006C34]  
pvc$osf226$5162                = [00000000 00006C4C]  
pvc$osf227$1008                = [00000000 00006C54]  
pvc$osf228$29                  = [00000000 00006C5C]  
pvc$osf229$5160.1              = [00000000 00006C5C]  
pvc$osf23$3116.1               = [00000000 000046F0]  
pvc$osf230$5162                = [00000000 00006C60]  
pvc$osf231$5162                = [00000000 00006C64]  
pvc$osf232$1008                = [00000000 00006C88]  
pvc$osf233$5162                = [00000000 00006C8C]  
pvc$osf234$5161                = [00000000 00006C90]  
pvc$osf235$29                  = [00000000 00006CB0]  
pvc$osf236$5160.2              = [00000000 00006CB0]  
pvc$osf237$5162                = [00000000 00006CEC]  
pvc$osf238$1008                = [00000000 00006CF0]  
pvc$osf239$5159.1              = [00000000 00006CF4]  
pvc$osf24$5118.1               = [00000000 00004B28]  
pvc$osf240$29                  = [00000000 00006CF4]  
pvc$osf241$1008                = [00000000 00006D3C]  
pvc$osf242$29                  = [00000000 00006D40]  
pvc$osf243$5162.1              = [00000000 00006D40]  
pvc$osf244$5161                = [00000000 00006D4C]  
pvc$osf245$1008                = [00000000 00006D58]  
pvc$osf246$1008                = [00000000 00006D68]  
pvc$osf247$1008                = [00000000 00006D90]  
pvc$osf248$1008                = [00000000 00006D94]  
pvc$osf249$5158.1              = [00000000 00006DB8]  
pvc$osf25$3119                 = [00000000 00004B98]  
pvc$osf250$29                  = [00000000 00006DB8]  
pvc$osf26$3119.1               = [00000000 00004B9C]  
pvc$osf27$5121.1               = [00000000 00004E6C]  
pvc$osf28$1007                 = [00000000 00002014]  
pvc$osf29$1007                 = [00000000 00002054]  
pvc$osf3$3100.1                = [00000000 00000240]  
pvc$osf30$1007                 = [00000000 00002094]  
pvc$osf31$1007                 = [00000000 000020D4]  
pvc$osf32$1007                 = [00000000 00002114]  
pvc$osf33$1007                 = [00000000 00002154]  
pvc$osf34$1007                 = [00000000 00002194]  
pvc$osf35$1007                 = [00000000 000021D4]  
pvc$osf36$1007                 = [00000000 00002214]  
pvc$osf37$1007                 = [00000000 00002254]  
pvc$osf38$1007                 = [00000000 00002294]  
pvc$osf39$1007                 = [00000000 000022D4]  
pvc$osf4$3102                  = [00000000 000040EC]  
pvc$osf40$1007                 = [00000000 00002314]  
pvc$osf41$1007                 = [00000000 00002354]  
pvc$osf42$1007                 = [00000000 00002394]  
pvc$osf43$1007                 = [00000000 000023D4]  
pvc$osf44$1007                 = [00000000 00002414]  
pvc$osf45$1007                 = [00000000 00002454]  
pvc$osf46$1007                 = [00000000 00002494]  
pvc$osf47$1007                 = [00000000 000024D4]  
pvc$osf48$1007                 = [00000000 00002514]  
pvc$osf49$1007                 = [00000000 00002554]  
pvc$osf5$3102.1                = [00000000 000040F0]  
pvc$osf50$1007                 = [00000000 00002594]  
pvc$osf51$1007                 = [00000000 000025D4]  
pvc$osf52$1007                 = [00000000 00002614]  
pvc$osf53$1007                 = [00000000 00002654]  
pvc$osf54$1007                 = [00000000 00002694]  
pvc$osf55$1007                 = [00000000 000026D4]  
pvc$osf56$1007                 = [00000000 00002714]  
pvc$osf57$1007                 = [00000000 00002754]  
pvc$osf58$1007                 = [00000000 00002794]  
pvc$osf59$1007                 = [00000000 000027D4]  
pvc$osf6$2                     = [00000000 00000340]  
pvc$osf60$1007                 = [00000000 00002814]  
pvc$osf61$1007                 = [00000000 00002854]  
pvc$osf62$1007                 = [00000000 00002894]  
pvc$osf63$1007                 = [00000000 000028D4]  
pvc$osf64$1007                 = [00000000 00002914]  
pvc$osf65$1007                 = [00000000 00002954]  
pvc$osf66$1007                 = [00000000 00002994]  
pvc$osf67$1007                 = [00000000 000029D4]  
pvc$osf68$1007                 = [00000000 00002A14]  
pvc$osf69$1007                 = [00000000 00002A54]  
pvc$osf7$3104                  = [00000000 000041A8]  
pvc$osf70$1007                 = [00000000 00002A94]  
pvc$osf71$1007                 = [00000000 00002AD4]  
pvc$osf72$1007                 = [00000000 00002B14]  
pvc$osf73$1007                 = [00000000 00002B54]  
pvc$osf74$1007                 = [00000000 00002B94]  
pvc$osf75$1007                 = [00000000 00002BD4]  
pvc$osf76$1007                 = [00000000 00002C14]  
pvc$osf77$1007                 = [00000000 00002C54]  
pvc$osf78$1007                 = [00000000 00002C94]  
pvc$osf79$1007                 = [00000000 00002CD4]  
pvc$osf8$3104.1                = [00000000 000041AC]  
pvc$osf80$1007                 = [00000000 00002D14]  
pvc$osf81$1007                 = [00000000 00002D54]  
pvc$osf82$1007                 = [00000000 00002D94]  
pvc$osf83$1007                 = [00000000 00002DD4]  
pvc$osf84$1007                 = [00000000 00002E14]  
pvc$osf85$1007                 = [00000000 00002E54]  
pvc$osf86$1007                 = [00000000 00002E94]  
pvc$osf87$1007                 = [00000000 00002ED4]  
pvc$osf88$1007                 = [00000000 00002F14]  
pvc$osf89$1007                 = [00000000 00002F54]  
pvc$osf9$2                     = [00000000 00004290]  
pvc$osf90$1007                 = [00000000 00002F94]  
pvc$osf91$1007                 = [00000000 00002FD4]  
pvc$osf92$1007                 = [00000000 00003014]  
pvc$osf93$1007                 = [00000000 00003054]  
pvc$osf94$1007                 = [00000000 00003094]  
pvc$osf95$1007                 = [00000000 000030D4]  
pvc$osf96$1007                 = [00000000 00003114]  
pvc$osf97$1007                 = [00000000 00003154]  
pvc$osf98$1007                 = [00000000 00003194]  
pvc$osf99$1007                 = [00000000 000031D4]  
reference_platform             = [00000000 00000001]  
restore_fpcr_offset            = [00000000 00000010]  
sbe_off_offset                 = [00000000 00000014]  
scb__passive__rel              = [00000000 000006F0]  
scb__perfmon                   = [00000000 00000650]  
scb__proc_corr_err             = [00000000 00000630]  
scb__procmchk                  = [00000000 00000670]  
scb__pwrfail                   = [00000000 00000640]  
scb__sys_corr_err              = [00000000 00000620]  
scb__sys_event                 = [00000000 00000680]  
scb__sysmchk                   = [00000000 00000660]  
send_bit                       = [00000000 00006CE0]  Branch Displacement at 00006CD8 in PSECT 0000
set_baud                       = [00000000 00006DB0]  Branch Displacement at 00006DA4 in PSECT 0000
simple_div                     = [00000000 00006D9C]  Branch Displacement at 00006DAC in PSECT 0000
spinlock_hack                  = [00000000 00000000]  
srm_console                    = [00000000 00000000]  
srom                           = [00000000 00000001]  
start_bit                      = [00000000 00006C60]  Branch Displacement at 00006C48 in PSECT 0000
sys__cbox                      = [00000000 000063F0]  Branch Displacement at 00005C00 in PSECT 0000
                                                      Branch Displacement at 00005DC0 in PSECT 0000
                                                      Branch Displacement at 00006000 in PSECT 0000
                                                      Branch Displacement at 00006310 in PSECT 0000
                                                      Branch Displacement at 0000690C in PSECT 0000
sys__cbox_cbox_done            = [00000000 000064C0]  Branch Displacement at 000064B0 in PSECT 0000
sys__cbox_over1                = [00000000 00006440]  Branch Displacement at 000064BC in PSECT 0000
sys__cbox_over2                = [00000000 00006450]  Branch Displacement at 00006448 in PSECT 0000
                                                      Branch Displacement at 000064A8 in PSECT 0000
sys__cbox_over3                = [00000000 00006460]  Branch Displacement at 00006458 in PSECT 0000
sys__cbox_over4                = [00000000 00006470]  Branch Displacement at 00006468 in PSECT 0000
sys__cbox_over5                = [00000000 00006480]  Branch Displacement at 00006478 in PSECT 0000
sys__cbox_over6                = [00000000 00006490]  Branch Displacement at 00006488 in PSECT 0000
sys__cbox_over7                = [00000000 000064A0]  Branch Displacement at 00006498 in PSECT 0000
sys__cbox_over8                = [00000000 000064B0]  Branch Displacement at 00006490 in PSECT 0000
sys__cbox_sbe_off              = [00000000 00006408]  Branch Displacement at 00006404 in PSECT 0000
sys__cbox_sbe_off_done         = [00000000 0000641C]  
sys__cbox_touch1               = [00000000 0000644C]  Branch Displacement at 0000641C in PSECT 0000
sys__cbox_touch2               = [00000000 0000645C]  Branch Displacement at 0000644C in PSECT 0000
sys__cbox_touch3               = [00000000 0000646C]  Branch Displacement at 0000645C in PSECT 0000
sys__cbox_touch4               = [00000000 0000647C]  Branch Displacement at 0000646C in PSECT 0000
sys__cbox_touch5               = [00000000 0000648C]  Branch Displacement at 0000647C in PSECT 0000
sys__cbox_touch6               = [00000000 0000649C]  Branch Displacement at 0000648C in PSECT 0000
sys__cbox_touch7               = [00000000 000064AC]  Branch Displacement at 0000649C in PSECT 0000
sys__cbox_touch8               = [00000000 000064BC]  Branch Displacement at 000064AC in PSECT 0000
sys__cflush                    = [00000000 000056C0]  Branch Displacement at 00002040 in PSECT 0000
sys__cflush_do_outer           = [00000000 00005750]  Branch Displacement at 00005748 in PSECT 0000
sys__cflush_done               = [00000000 00005760]  Branch Displacement at 00005750 in PSECT 0000
sys__cflush_inner_loop         = [00000000 000056E4]  Branch Displacement at 0000574C in PSECT 0000
sys__cflush_interrupt          = [00000000 00005764]  Branch Displacement at 00005744 in PSECT 0000
sys__cflush_outer_loop         = [00000000 000056DC]  Branch Displacement at 0000575C in PSECT 0000
sys__crd                       = [00000000 00005C00]  Branch Displacement at 000006A4 in PSECT 0000
sys__crd_addr                  = [00000000 00005CA8]  Branch Displacement at 00005CC0 in PSECT 0000
sys__crd_addr_done             = [00000000 00005CC4]  Branch Displacement at 00005CB4 in PSECT 0000
sys__crd_arrange_cbox          = [00000000 00005C70]  
sys__crd_do_scrub              = [00000000 00005D18]  Branch Displacement at 00005D00 in PSECT 0000
                                                      Branch Displacement at 00005D10 in PSECT 0000
sys__crd_header                = [00000000 00005DF8]  Branch Displacement at 00005FD4 in PSECT 0000
                                                      Branch Displacement at 000063C0 in PSECT 0000
sys__crd_merge                 = [00000000 00005DD4]  Branch Displacement at 00005CF8 in PSECT 0000
                                                      Branch Displacement at 00005D08 in PSECT 0000
                                                      Branch Displacement at 00005D14 in PSECT 0000
                                                      Branch Displacement at 00005D70 in PSECT 0000
sys__crd_scrub                 = [00000000 00005D80]  Branch Displacement at 00005D58 in PSECT 0000
                                                      Branch Displacement at 00005EE8 in PSECT 0000
sys__crd_scrub_done            = [00000000 00005DB8]  Branch Displacement at 00005DB0 in PSECT 0000
sys__crd_second                = [00000000 00005E30]  Branch Displacement at 00005C6C in PSECT 0000
sys__crd_skip_frame            = [00000000 00005E3C]  Branch Displacement at 00005C24 in PSECT 0000
sys__crd_skip_frame_addr       = [00000000 00005E84]  Branch Displacement at 00005E9C in PSECT 0000
sys__crd_skip_frame_addr_done  = [00000000 00005EA0]  Branch Displacement at 00005E90 in PSECT 0000
sys__crd_skip_frame_do_scrub   = [00000000 00005E7C]  Branch Displacement at 00005E64 in PSECT 0000
                                                      Branch Displacement at 00005E74 in PSECT 0000
sys__crd_skip_frame_merge      = [00000000 00005F04]  Branch Displacement at 00005E5C in PSECT 0000
                                                      Branch Displacement at 00005E6C in PSECT 0000
                                                      Branch Displacement at 00005E78 in PSECT 0000
                                                      Branch Displacement at 00005F00 in PSECT 0000
sys__cserve                    = [00000000 000064D8]  Branch Displacement at 00002240 in PSECT 0000
sys__dc_tag_perr_while_in_pal  = [00000000 000063DC]  Branch Displacement at 00005F40 in PSECT 0000
sys__deassert_interrupt        = [00000000 00005A00]  Branch Displacement at 000054C0 in PSECT 0000
                                                      Branch Displacement at 00005508 in PSECT 0000
sys__double_machine_check      = [00000000 000063C4]  Branch Displacement at 00000554 in PSECT 0000
                                                      Branch Displacement at 00005AC4 in PSECT 0000
                                                      Branch Displacement at 00006034 in PSECT 0000
sys__enter_console             = [00000000 00006580]  Branch Displacement at 000047AC in PSECT 0000
                                                      Branch Displacement at 00006570 in PSECT 0000
                                                      Branch Displacement at 00006948 in PSECT 0000
                                                      Branch Displacement at 00006AC0 in PSECT 0000
sys__enter_console_get_pal_base = [00000000 00006620]  Branch Displacement at 0000661C in PSECT 0000
sys__exit_console              = [00000000 00006680]  Branch Displacement at 0000650C in PSECT 0000
sys__int_check_dev             = [00000000 00005A3C]  Branch Displacement at 00005A34 in PSECT 0000
sys__int_check_err             = [00000000 00005A48]  Branch Displacement at 00005A40 in PSECT 0000
sys__int_check_ip              = [00000000 00005A30]  Branch Displacement at 00005A28 in PSECT 0000
sys__int_clk                   = [00000000 00005A5C]  Branch Displacement at 00005A2C in PSECT 0000
sys__int_dev                   = [00000000 00005A94]  Branch Displacement at 00005A44 in PSECT 0000
sys__int_err                   = [00000000 00005A98]  Branch Displacement at 00005A50 in PSECT 0000
sys__int_ip                    = [00000000 00005A94]  Branch Displacement at 00005A38 in PSECT 0000
sys__int_pal_err               = [00000000 00005A54]  Branch Displacement at 00005A4C in PSECT 0000
sys__int_post                  = [00000000 00005B74]  Branch Displacement at 00005A90 in PSECT 0000
                                                      Branch Displacement at 00005B70 in PSECT 0000
                                                      Branch Displacement at 000061C4 in PSECT 0000
sys__int_post_cm               = [00000000 00005B8C]  Branch Displacement at 00005B88 in PSECT 0000
sys__int_post_cm_done          = [00000000 00005B9C]  Branch Displacement at 00005B7C in PSECT 0000
sys__interrupt_ei              = [00000000 00005A24]  Branch Displacement at 000006B8 in PSECT 0000
sys__interrupt_pc              = [00000000 00005B38]  Branch Displacement at 000006A8 in PSECT 0000
sys__interrupt_sl              = [00000000 00005B20]  Branch Displacement at 00004748 in PSECT 0000
sys__machine_check_while_in_pal = [00000000 000063D0]  Branch Displacement at 00005AC8 in PSECT 0000
                                                      Branch Displacement at 00006038 in PSECT 0000
sys__mchk                      = [00000000 00006000]  Branch Displacement at 0000051C in PSECT 0000
sys__mchk__double_bit          = [00000000 00006004]  Branch Displacement at 00005C10 in PSECT 0000
sys__mchk_addr                 = [00000000 000060A0]  Branch Displacement at 000060B8 in PSECT 0000
sys__mchk_addr_done            = [00000000 000060BC]  Branch Displacement at 000060AC in PSECT 0000
sys__mchk_arrange_cbox         = [00000000 00006068]  
sys__mchk_clear_crd            = [00000000 0000630C]  
sys__mchk_dc_tag_perr          = [00000000 00005F40]  Branch Displacement at 00004444 in PSECT 0000
sys__mchk_double               = [00000000 00006108]  Branch Displacement at 000060FC in PSECT 0000
sys__mchk_header               = [00000000 00006118]  Branch Displacement at 00004598 in PSECT 0000
                                                      Branch Displacement at 00005B18 in PSECT 0000
                                                      Branch Displacement at 00006238 in PSECT 0000
                                                      Branch Displacement at 00006254 in PSECT 0000
sys__mchk_istream              = [00000000 000061C8]  Branch Displacement at 00006104 in PSECT 0000
sys__mchk_istream_check_cmov   = [00000000 000061D4]  
sys__mchk_istream_cmov_err     = [00000000 00006220]  Branch Displacement at 00006218 in PSECT 0000
sys__mchk_istream_cmov_fault   = [00000000 0000623C]  Branch Displacement at 00004260 in PSECT 0000
                                                      Branch Displacement at 000043D8 in PSECT 0000
sys__mchk_istream_not_cmov     = [00000000 00006258]  Branch Displacement at 0000621C in PSECT 0000
sys__mchk_post                 = [00000000 0000618C]  Branch Displacement at 00005E2C in PSECT 0000
sys__mchk_registers            = [00000000 00006140]  
sys__mchk_scrub                = [00000000 000062C0]  Branch Displacement at 00006294 in PSECT 0000
sys__mchk_scrub_done           = [00000000 000062F8]  Branch Displacement at 000062F0 in PSECT 0000
sys__mchk_to_crd               = [00000000 0000633C]  
sys__perr_dis                  = [00000000 00005FE8]  Branch Displacement at 00005F4C in PSECT 0000
sys__perr_second               = [00000000 00005FD8]  Branch Displacement at 00005FA8 in PSECT 0000
                                                      Branch Displacement at 00006380 in PSECT 0000
sys__perr_skip_frame           = [00000000 00005FE4]  Branch Displacement at 00005F60 in PSECT 0000
                                                      Branch Displacement at 0000634C in PSECT 0000
sys__reset                     = [00000000 00006700]  Branch Displacement at 00000000 in PSECT 0000
sys__reset_check_switch        = [00000000 0000694C]  Branch Displacement at 00006714 in PSECT 0000
sys__reset_init                = [00000000 00006730]  Branch Displacement at 00006724 in PSECT 0000
sys__reset_noswitch            = [00000000 00006AB8]  Branch Displacement at 00006950 in PSECT 0000
sys__switch_base               = [00000000 00006960]  
sys__switch_get_pal_base       = [00000000 00006964]  Branch Displacement at 00006960 in PSECT 0000
sys__switch_unknown            = [00000000 00006568]  
sys__wakeup                    = [00000000 00006B00]  Branch Displacement at 000009A0 in PSECT 0000
sys__wakeup_bc_on              = [00000000 00006B50]  Branch Displacement at 00006B84 in PSECT 0000
sys__wakeup_bc_on_done         = [00000000 00006B6C]  Branch Displacement at 00006B60 in PSECT 0000
sys__wakeup_bc_on_loop         = [00000000 00006B58]  Branch Displacement at 00006B68 in PSECT 0000
sys__wakeup_get_ticks          = [00000000 00006B98]  
sys__wakeup_probe              = [00000000 00006B88]  Branch Displacement at 00006B74 in PSECT 0000
sys__wakeup_touch1             = [00000000 00006B40]  
sys__wakeup_touch2             = [00000000 00006B80]  Branch Displacement at 00006B44 in PSECT 0000
sys__wakeup_write_many_chain   = [00000000 00006B00]  
sys__wripir                    = [00000000 00005780]  Branch Displacement at 00002340 in PSECT 0000
sys__wtint                     = [00000000 00005794]  Branch Displacement at 00002F80 in PSECT 0000
sys__wtint_addr                = [00000000 00005948]  Branch Displacement at 00005914 in PSECT 0000
sys__wtint_bc_off              = [00000000 000058D0]  Branch Displacement at 000058B8 in PSECT 0000
sys__wtint_bc_off_done         = [00000000 000058EC]  Branch Displacement at 000058E0 in PSECT 0000
sys__wtint_bc_off_loop         = [00000000 000058D8]  Branch Displacement at 000058E8 in PSECT 0000
sys__wtint_clocks              = [00000000 00005908]  Branch Displacement at 000058F4 in PSECT 0000
sys__wtint_inner_loop          = [00000000 000058A4]  Branch Displacement at 000058A0 in PSECT 0000
                                                      Branch Displacement at 000058B4 in PSECT 0000
sys__wtint_loop_test           = [00000000 000058B8]  Branch Displacement at 000058B0 in PSECT 0000
sys__wtint_noticks             = [00000000 000059C8]  Branch Displacement at 00005794 in PSECT 0000
                                                      Branch Displacement at 000059C4 in PSECT 0000
sys__wtint_outer_loop          = [00000000 00005890]  Branch Displacement at 000058BC in PSECT 0000
sys__wtint_punt                = [00000000 000059C0]  Branch Displacement at 0000589C in PSECT 0000
sys__wtint_sleep               = [00000000 00005988]  Branch Displacement at 00005974 in PSECT 0000
sys__wtint_start_flush         = [00000000 00005888]  Branch Displacement at 00005984 in PSECT 0000
sys__wtint_touch0              = [00000000 00005880]  
sys__wtint_touch1              = [00000000 000058C0]  Branch Displacement at 00005884 in PSECT 0000
sys__wtint_touch2              = [00000000 00005900]  Branch Displacement at 000058C4 in PSECT 0000
sys__wtint_touch3              = [00000000 00005940]  Branch Displacement at 00005904 in PSECT 0000
sys__wtint_touch4              = [00000000 00005980]  Branch Displacement at 00005944 in PSECT 0000
sys_cserve_srom_getc           = [00000000 00006C10]  Branch Displacement at 00006504 in PSECT 0000
sys_cserve_srom_init           = [00000000 00006BE0]  Branch Displacement at 000064F4 in PSECT 0000
sys_cserve_srom_putc           = [00000000 00006C00]  Branch Displacement at 000064FC in PSECT 0000
t                              = [00000000 0000001F]  
tb_mb_en                       = [00000000 00000000]  
tbi_function_power             = [00000000 00000006]  
tbi_tbl                        = [00000000 00004FC0]  
tpcv_jsr_index                 = [00000000 00000C65]  
trap__arith                    = [00000000 00000600]  
trap__arith_cm                 = [00000000 000046E0]  Branch Displacement at 000046DC in PSECT 0000
trap__arith_cont               = [00000000 00004680]  Branch Displacement at 00000634 in PSECT 0000
trap__arith_finish             = [00000000 000046AC]  
trap__arith_fpcr               = [00000000 0000469C]  Branch Displacement at 00004698 in PSECT 0000
trap__arith_int                = [00000000 00000628]  Branch Displacement at 00000620 in PSECT 0000
trap__arith_post               = [00000000 000046BC]  Branch Displacement at 00000630 in PSECT 0000
                                                      Branch Displacement at 000046B4 in PSECT 0000
trap__arith_stack              = [00000000 000046F0]  Branch Displacement at 000046CC in PSECT 0000
trap__bpt_cm                   = [00000000 0000555C]  Branch Displacement at 00005558 in PSECT 0000
trap__bpt_stack                = [00000000 0000556C]  Branch Displacement at 00005548 in PSECT 0000
trap__callsys_cm               = [00000000 000030DC]  Branch Displacement at 000030D8 in PSECT 0000
trap__callsys_cm_done          = [00000000 000030EC]  
trap__d1to1                    = [00000000 0000427C]  Branch Displacement at 00000324 in PSECT 0000
trap__dc_tag_perr              = [00000000 000043F0]  Branch Displacement at 00000390 in PSECT 0000
trap__dfault                   = [00000000 00000380]  
trap__dfault_check             = [00000000 000042D8]  Branch Displacement at 000042C0 in PSECT 0000
trap__dfault_cm                = [00000000 0000430C]  Branch Displacement at 00004308 in PSECT 0000
trap__dfault_cont              = [00000000 000042C0]  Branch Displacement at 00000398 in PSECT 0000
trap__dfault_dismiss           = [00000000 00004374]  Branch Displacement at 000042D0 in PSECT 0000
                                                      Branch Displacement at 000042E4 in PSECT 0000
trap__dfault_in_pal            = [00000000 0000437C]  Branch Displacement at 00000394 in PSECT 0000
trap__dfault_in_pal_istream_mchk = [00000000 000043D0]  Branch Displacement at 000043B4 in PSECT 0000
trap__dfault_in_pal_urti       = [00000000 000043BC]  Branch Displacement at 000043A8 in PSECT 0000
trap__dfault_no_dismiss        = [00000000 000042E8]  Branch Displacement at 000042D4 in PSECT 0000
                                                      Branch Displacement at 000043CC in PSECT 0000
trap__dfault_stack             = [00000000 0000431C]  Branch Displacement at 000042F8 in PSECT 0000
trap__double3_1to1             = [00000000 00004034]  Branch Displacement at 00000120 in PSECT 0000
                                                      Branch Displacement at 000001A0 in PSECT 0000
trap__double3_pte_inv          = [00000000 00004018]  Branch Displacement at 0000013C in PSECT 0000
                                                      Branch Displacement at 00000150 in PSECT 0000
                                                      Branch Displacement at 000001BC in PSECT 0000
                                                      Branch Displacement at 000001D8 in PSECT 0000
                                                      Branch Displacement at 000001EC in PSECT 0000
trap__dtbm_double3_mb          = [00000000 0000400C]  Branch Displacement at 00004000 in PSECT 0000
trap__dtbm_double4_mb          = [00000000 000040A4]  Branch Displacement at 00004098 in PSECT 0000
trap__dtbm_double_3            = [00000000 00000100]  
trap__dtbm_double_3_cont       = [00000000 00004000]  Branch Displacement at 00000178 in PSECT 0000
trap__dtbm_double_4            = [00000000 00000180]  
trap__dtbm_double_4_cont       = [00000000 00004080]  Branch Displacement at 000001F4 in PSECT 0000
trap__dtbm_single              = [00000000 00000300]  
trap__dtbm_single_gh_mb_io     = [00000000 00000358]  Branch Displacement at 00000350 in PSECT 0000
trap__dtbm_single_vpte         = [00000000 00000320]  
trap__emul_fen                 = [00000000 00000210]  
trap__fen                      = [00000000 00000200]  
trap__fen_cm                   = [00000000 00000230]  Branch Displacement at 0000022C in PSECT 0000
trap__fen_stack                = [00000000 00000240]  Branch Displacement at 0000021C in PSECT 0000
trap__foe                      = [00000000 000045DC]  Branch Displacement at 000005AC in PSECT 0000
trap__i1to1                    = [00000000 000045C0]  Branch Displacement at 00000598 in PSECT 0000
trap__iacv                     = [00000000 00000480]  
trap__iacv_bad_iva             = [00000000 000004D8]  Branch Displacement at 00000498 in PSECT 0000
trap__iacv_cm                  = [00000000 0000449C]  Branch Displacement at 00004498 in PSECT 0000
trap__iacv_pal                 = [00000000 000044E8]  Branch Displacement at 00000490 in PSECT 0000
trap__iacv_pc_ovfl             = [00000000 000004A8]  Branch Displacement at 000004A0 in PSECT 0000
trap__iacv_post                = [00000000 00004480]  Branch Displacement at 000004A4 in PSECT 0000
                                                      Branch Displacement at 000004B4 in PSECT 0000
                                                      Branch Displacement at 000004C4 in PSECT 0000
                                                      Branch Displacement at 000004D4 in PSECT 0000
                                                      Branch Displacement at 000004E4 in PSECT 0000
trap__iacv_stack               = [00000000 000044AC]  Branch Displacement at 00004488 in PSECT 0000
trap__iacv_under               = [00000000 000004C8]  Branch Displacement at 000004BC in PSECT 0000
trap__iacv_va_48               = [00000000 000004B8]  Branch Displacement at 000004B0 in PSECT 0000
trap__interrupt                = [00000000 00000680]  
trap__interrupt_dismiss        = [00000000 0000474C]  Branch Displacement at 00004744 in PSECT 0000
trap__interrupt_passive        = [00000000 0000474C]  
trap__interrupt_sl             = [00000000 00004740]  Branch Displacement at 000006B4 in PSECT 0000
trap__invalid_dpte             = [00000000 00004140]  Branch Displacement at 00000328 in PSECT 0000
trap__invalid_dpte_check       = [00000000 00004168]  Branch Displacement at 00004150 in PSECT 0000
trap__invalid_dpte_cm          = [00000000 0000419C]  Branch Displacement at 00004198 in PSECT 0000
trap__invalid_dpte_dismiss     = [00000000 0000420C]  Branch Displacement at 00004160 in PSECT 0000
                                                      Branch Displacement at 00004174 in PSECT 0000
trap__invalid_dpte_get         = [00000000 00004148]  Branch Displacement at 00004140 in PSECT 0000
trap__invalid_dpte_have        = [00000000 0000414C]  Branch Displacement at 00004144 in PSECT 0000
trap__invalid_dpte_no_dismiss  = [00000000 00004178]  Branch Displacement at 00004164 in PSECT 0000
                                                      Branch Displacement at 00004254 in PSECT 0000
trap__invalid_dpte_stack       = [00000000 000041AC]  Branch Displacement at 00004184 in PSECT 0000
trap__invalid_ipte             = [00000000 000045E4]  Branch Displacement at 000005A8 in PSECT 0000
trap__invalid_ipte_cm          = [00000000 00004608]  Branch Displacement at 00004604 in PSECT 0000
trap__invalid_ipte_merge       = [00000000 000045E8]  Branch Displacement at 000045E0 in PSECT 0000
trap__invalid_ipte_stack       = [00000000 00004618]  Branch Displacement at 000045F0 in PSECT 0000
trap__itb_miss                 = [00000000 00000580]  
trap__itb_miss_mb              = [00000000 000005D0]  Branch Displacement at 000005C8 in PSECT 0000
trap__itb_miss_vpte            = [00000000 00000590]  
trap__ksp_invalid              = [00000000 00004264]  Branch Displacement at 00004240 in PSECT 0000
                                                      Branch Displacement at 000043B8 in PSECT 0000
trap__ldvpte_dfault            = [00000000 000043DC]  Branch Displacement at 00004394 in PSECT 0000
                                                      Branch Displacement at 0000439C in PSECT 0000
trap__lock_cell                = [00000000 00000010]  
trap__mchk                     = [00000000 00000500]  
trap__mchk_cont                = [00000000 00004540]  Branch Displacement at 00000558 in PSECT 0000
trap__mchk_mb                  = [00000000 00000514]  Branch Displacement at 00000510 in PSECT 0000
trap__mt_fpcr                  = [00000000 00000700]  
trap__opcdec                   = [00000000 00000400]  
trap__opcdec_call_pal          = [00000000 00000418]  
trap__opcdec_cm                = [00000000 00000434]  Branch Displacement at 00000430 in PSECT 0000
trap__opcdec_stack             = [00000000 00000444]  Branch Displacement at 00000420 in PSECT 0000
trap__pal_base                 = [00000000 00000000]  
trap__pal_bugcheck             = [00000000 00000530]  Branch Displacement at 00000528 in PSECT 0000
                                                      Branch Displacement at 00005A58 in PSECT 0000
trap__pal_exc_bugcheck         = [00000000 0000052C]  Branch Displacement at 00000210 in PSECT 0000
                                                      Branch Displacement at 00000290 in PSECT 0000
                                                      Branch Displacement at 00000410 in PSECT 0000
                                                      Branch Displacement at 00000614 in PSECT 0000
trap__pal_os_bugcheck          = [00000000 00000520]  Branch Displacement at 000030C8 in PSECT 0000
                                                      Branch Displacement at 00003494 in PSECT 0000
trap__powerup                  = [00000000 00000000]  
trap__start                    = [00000000 00000000]  
trap__tnv_in_pal               = [00000000 00004214]  Branch Displacement at 0000414C in PSECT 0000
trap__tnv_in_pal_istream_mchk  = [00000000 00004258]  Branch Displacement at 0000423C in PSECT 0000
trap__tnv_in_pal_urti          = [00000000 00004244]  Branch Displacement at 00004230 in PSECT 0000
trap__unalign                  = [00000000 00000280]  
trap__unalign_cm               = [00000000 000040E0]  Branch Displacement at 000040DC in PSECT 0000
trap__unalign_nodismiss        = [00000000 000040C0]  Branch Displacement at 000002A0 in PSECT 0000
                                                      Branch Displacement at 000002A8 in PSECT 0000
trap__unalign_stack            = [00000000 000040F0]  Branch Displacement at 000040CC in PSECT 0000
trap__update_pcb_and_halt      = [00000000 00004780]  Branch Displacement at 00004278 in PSECT 0000
                                                      Branch Displacement at 000043EC in PSECT 0000
                                                      Branch Displacement at 00004500 in PSECT 0000
                                                      Branch Displacement at 0000200C in PSECT 0000
                                                      Branch Displacement at 000063CC in PSECT 0000
                                                      Branch Displacement at 000063D8 in PSECT 0000
                                                      Branch Displacement at 000063E4 in PSECT 0000
trap__update_pcb_and_halt_cpc  = [00000000 0000479C]  Branch Displacement at 00004790 in PSECT 0000
trap__update_pcb_from_user     = [00000000 00004794]  Branch Displacement at 00004788 in PSECT 0000
trap__wakeup                   = [00000000 00000780]  
trap__wakeup__next0            = [00000000 00000910]  Branch Displacement at 0000099C in PSECT 0000
trap__wakeup__next1            = [00000000 00000920]  Branch Displacement at 00000918 in PSECT 0000
trap__wakeup__next2            = [00000000 00000930]  Branch Displacement at 00000928 in PSECT 0000
trap__wakeup__next3            = [00000000 00000940]  Branch Displacement at 00000938 in PSECT 0000
trap__wakeup__next4            = [00000000 00000950]  Branch Displacement at 00000948 in PSECT 0000
trap__wakeup__next5            = [00000000 00000960]  Branch Displacement at 00000958 in PSECT 0000
trap__wakeup__next6            = [00000000 00000970]  Branch Displacement at 00000968 in PSECT 0000
trap__wakeup__next7            = [00000000 00000980]  Branch Displacement at 00000978 in PSECT 0000
trap__wakeup__next8            = [00000000 00000990]  Branch Displacement at 00000988 in PSECT 0000
trap__wakeup__sde_done         = [00000000 000009A0]  Branch Displacement at 00000998 in PSECT 0000
trap__wakeup__touch0           = [00000000 0000091C]  Branch Displacement at 00000908 in PSECT 0000
trap__wakeup__touch1           = [00000000 0000092C]  Branch Displacement at 0000091C in PSECT 0000
trap__wakeup__touch2           = [00000000 0000093C]  Branch Displacement at 0000092C in PSECT 0000
trap__wakeup__touch3           = [00000000 0000094C]  Branch Displacement at 0000093C in PSECT 0000
trap__wakeup__touch4           = [00000000 0000095C]  Branch Displacement at 0000094C in PSECT 0000
trap__wakeup__touch5           = [00000000 0000096C]  Branch Displacement at 0000095C in PSECT 0000
trap__wakeup__touch6           = [00000000 0000097C]  Branch Displacement at 0000096C in PSECT 0000
trap__wakeup__touch7           = [00000000 0000098C]  Branch Displacement at 0000097C in PSECT 0000
trap__wakeup__touch8           = [00000000 0000099C]  Branch Displacement at 0000098C in PSECT 0000
unalign_cm_offset              = [00000000 00000010]  
va_48                          = [00000000 00000001]  
va_bits_3                      = [00000000 0000002B]  
va_bits_4                      = [00000000 00000030]  
vmaj                           = [00000000 00000001]  
vmin                           = [00000000 00000032]  
vms_pal                        = [00000000 00000001]  
wait                           = [00000000 00006D30]  Branch Displacement at 00006D3C in PSECT 0000
wait_init                      = [00000000 00006D14]  
waitbitcont                    = [00000000 00006D14]  Branch Displacement at 00006CFC in PSECT 0000
                                                      Branch Displacement at 00006D04 in PSECT 0000
                                                      Branch Displacement at 00006D0C in PSECT 0000
waitbiteighth                  = [00000000 00006D10]  Branch Displacement at 00006C4C in PSECT 0000
waitbithalf                    = [00000000 00006D00]  Branch Displacement at 00006C60 in PSECT 0000
waitbitquarter                 = [00000000 00006D08]  
waitbittime                    = [00000000 00006CF8]  Branch Displacement at 00006C64 in PSECT 0000
                                                      Branch Displacement at 00006C8C in PSECT 0000
                                                      Branch Displacement at 00006CEC in PSECT 0000
wrent_tbl                      = [00000000 00005140]  


PSECT name            Alignment  Bytes     Base address       
0000                  2             28096  [00000000 00000000]
