// Sample code file: cntr2000.h

// Warning: This code has been marked up for HTML

/*--------------------------------------------------------------------------*
 * $name: NTR2000.H
 * $version: 3
 * $date_modified: 12181998 
 * $description: Header file for NTR2000 HSM  
 * $owner:  ODI LAN Driver Manager
 * Copyright (c) 1996, 1997, 1998 Novell, Inc. All Rights Reserved.
 *
 * THIS WORK IS SUBJECT TO U.S. AND INTERNATIONAL COPYRIGHT LAWS AND 
 * TREATIES. USE AND REDISTRIBUTION OF THIS WORK IS SUBJECT TO THE LICENSE
 * AGREEMENT ACCOMPANYING THE SOFTWARE DEVELOPMENT KIT (SDK) THAT CONTAINS
 * THIS WORK. PURSUANT TO THE SDK LICENSE AGREEMENT, NOVELL HEREBY GRANTS 
 * TO DEVELOPER A ROYALTY-FREE, NON-EXCLUSIVE LICENSE TO INCLUDE NOVELL'S 
 * SAMPLE CODE IN ITS PRODUCT. NOVELL GRANTS DEVELOPER WORLDWIDE 
 * DISTRIBUTION RIGHTS TO MARKET, DISTRIBUTE, OR SELL NOVELL'S SAMPLE CODE
 * AS A COMPONENT OF DEVELOPER'S PRODUCTS. NOVELL SHALL HAVE NO 
 * OBLIGATIONS TO DEVELOPER OR DEVELOPER'S CUSTOMERS WITH RESPECT TO THIS 
 * CODE.
 *--------------------------------------------------------------------------*/
/*****************************************************************************
 *
 * Title:         C language NTR2000 HSM Header file
 *
 * Filename:      NTR2000.H
 *
 * ODI Spec Ver:   1.11
 *
 * Description:       Header file for NTR2000 HSM
 *
 * Modification History: 
 *
 * 97-03-05 WTT      Changed define SHARING_FLAGS to set the shutdown bit 
 *               for the initial start up state.
 *
 ****************************************************************************/

#ifndef DRIVER_H

/**************************************************************************\
**
**    MACROS
**
\**************************************************************************/


/**************************************************************************\
**
**    HSM Defines
**
\**************************************************************************/
/* Token Ring Equate Values                                               */

#define  DEFAULT_RAM_SEGMENT     0xD8     /* default shared-ram segment   */
#define  INIT_TIMEOUT_IN_TICKS   3 * 18   /* DIR.Initialize Timeout 3 sec */
#define  MAX_INIT_RETRIES        2        /* DIR.Initialize re-try value  */
#define  DIR_INIT_WAIT_IN_TICKS  2        /* DIR.Initialize adptr rel wait*/
#define  SHARED_RAM_LOWER_LIMIT  0xA0000  /* minimum val 4 shared RAM seg */
#define  ADAPTER_CHECK_TIMEOUT   250/54+1 /* hardware adapter chck timeout*/

/* MLIDStatusFlag -- Token-Ring Card State Flag Equates                   */

#define  IGNORE_INTERRUPT_BIT    0x80     /* bit 7 - ignore all interrupts*/
#define  NIC_INTERRUPTED_BIT     0x40     /* bit 6 - interrupt happened   */
#define  RE_INIT_ADAPTER_BIT     0x20     /* bit 5 - Re-initialize adapter*/
#define  DIR_READ_LOG_BIT        0x10     /* bit 4 - DIR.Read.Log in order*/
#define  DIR_FUNCTIONAL_BIT      0x08     /* bit 3 - DIR.Set.Functinal.Add*/
#define  ADAPTER_RESET_BIT       0x04     /* bit 2 - Adapter held reset   */
#define  TX_IN_PROCESS_BIT       0x02     /* bit 1 - Transmit in progress */
#define  SRB_IS_BUSY_BIT         0x01     /* bit 0 - SRB is busy          */

/* IntStatusToAdapter -- PC To Adapter Int Status HIGH Byte Bit Values    */

#define  PC_PARITY_ERROR_BIT      0x80     /* bit 7 - parity err in s-ram  */
#define  PC_TIMER_EXPIRED_BIT      0x40     /* bit 6 - exp of timer count   */
#define  PC_ACCESS_VIOLATION_BIT 0x20     /* bit 5 - access violation     */

/* IntStatusToAdapter -- PC To Adapter Int Status LOW Byte Bit Values     */

#define  BRIDGE_FORWARD          0x40     /* bit 6 - Bridge Frame Fwd Req */
#define  COMMAND_IN_SRB          0x20     /* bit 5 - Command In SRB       */
#define  RESPONSE_IN_ASB         0x10     /* bit 4 - Response In ASB      */
#define  SRB_FREE                0x08     /* bit 3 - SRB Free Request     */
#define  ASB_FREE                0x04     /* bit 2 - ASB Free Request     */
#define  ARB_FREE                0x02     /* bit 1 - ARB Free             */
#define  SSB_FREE                0x01     /* bit 0 - SSB Free             */

/* IntStatusToPC -- Adapter To PC Int Status HIGH Byte Bit Values         */

#define  NMI_DISABLED_BIT        0x80     /* Bit 7 - NMI Disabled         */
#define  INTERRUPT_ENABLE_BIT    0x40     /* Bit 6 - Interrupt Enable     */
#define  PARITY_ERROR_BIT        0x20     /* Bit 5 - Parity Err In S-RAM  */
#define  TIMER_EXPIRED_BIT       0x10     /* Bit 4 - Exp Of Timer Count   */
#define  ADAPTER_ERROR_BIT       0x08     /* Bit 3 - Adapter Check        */
#define  RAM_VIOLATION_BIT       0x04     /* Bit 2 - S-RAM Access Violate */

/* IntStatusToPC -- Adapter To PC Int Status LOW Byte Bit Values          */

#define  IMPL_RECEIVED_BIT       0x80     /* Bit 7 - IMPL Received        */
#define  ADAPTER_CHECK_BIT       0x40     /* Bit 6 - Adapter Check        */
#define  SRB_RESPONSE_BIT        0x20     /* Bit 5   - SRB Response         */
#define  ASB_FREE_BIT            0x10     /* Bit 4 - ASB Free             */
#define  ARB_COMMAND_BIT         0x08      /* Bit 3 - ARB Command          */
#define  SSB_RESPONSE_BIT        0x04     /* Bit 2 - SSB Response         */
#define  BRIDGE_FORWARD_BIT      0x02     /* Bit 1 - Brdge Frame Fwd Cmpl */

/* RAMPageRegister Equates                                                */

#define  PAGING_ACTIVE_FLAG      0xc0     /* Paging Active Flag           */
#define  DEFAULT_PAGE_MASK       16*1024-1/* Paging Size Mask             */

/* RAMRelocationRegister LOW Byte Bit Values                              */

#define  ALTERNATE_IPL           0x01     /* Bit 0 - Alternate IPL        */
#define  PARTIAL_RESET           0x80     /* Bit 7 - Partial Reset        */
#define  SHARED_RAM_MASK         0x0c     /* Shared RAM Size Mask         */
#define  SHARED_RAM_8K           0x00     /* Shared RAM Size = 08k        */
#define  SHARED_RAM_16K          0x04     /* Shared RAM Size = 16k        */
#define  SHARED_RAM_32K          0x08     /* Shared RAM Size = 32k        */
#define  SHARED_RAM_64K          0x0c     /* Shared RAM Size = 64k        */

/* TimerControlRegister HIGH Byte Bit Values                              */

#define  TIMER_INTERRUPT         0x80     /* Bit 7 - INT PC When TVR = 0  */
#define  TIMER_RELOAD            0x40     /* Bit 6 - Auto Reload Of Count */
#define  TIMER_ENABLE            0x20     /* Bit 5 - Enble Timer, Strt Cnt*/
#define  TIMER_OVERRUN           0x10     /* Bit 4 - Timer Overrun        */

/* AdapterRequestBlock Command Code Equates                               */

#define  ARB_SIZE                28       /* 28 Size Of ARB in Shared RAM */
#define  ARB_RECEIVED_DATA       0x81     /* 81h - Received Data          */
#define  ARB_TRANSMIT_DATA       0x82     /* 82h - Transmit Data Request  */
#define  ARB_DLC_STATUS          0x83     /* 83h - DLC Status             */
#define  ARB_RING_STATUS_CHANGE  0x84     /* 84h - Ring Status Change     */

/* RingNewStatus Bit Values                                               */

#define  RING_SIGNAL_LOSS        0x0080   /* Bit 07 - Signal Loss         */
#define  RING_HARD_ERROR         0x0040   /* Bit 06 - Hard Error          */
#define  RING_SOFT_ERROR         0x0020   /* Bit 05 - Soft Error          */
#define  RING_TX_BEACON          0x0010   /* Bit 04 - Transmit Beacon     */
#define  RING_LOBE_WIRE_FAULT    0x0008   /* Bit 03 - Lobe Wire Fault     */
#define  RING_AUTO_REMOVE        0x0004   /* Bit 02 - Auto Remove Error 01*/
#define  RING_REMOVE_RECEIVED    0x0001   /* Bit 00 - Remove Received     */
#define  RING_COUNTER_OVERFLOW   0x8000   /* Bit 15 - Counter Overflow    */
#define  RING_SINGLE_STATION     0x4000   /* Bit 14 - Single Station      */
#define  RING_RECOVERY           0x2000   /* Bit 13 - Ring Recovery       */

/* ARBRxMessageType Equates                                               */

#define  ARB_MAC_FRAME            2       /* 02 MAC  Frame                */
#define  ARB_I_FRAME              4       /* 04 I    Frame                */
#define  ARB_UI_FRAME             6       /* 06 UI   Frame                */
#define  ARB_XID_POLL_FRAME       8       /* 08 XID  Command  Poll        */
#define  ARB_XID_NOTPOLL_FRAME   10       /* 10 XID  Command  Not Poll    */
#define  ARB_XID_FINAL_FRAME     12       /* 12 XID  Response Final       */
#define  ARB_XID_NOTFINAL_FRAME  14       /* 14 XID  Response Not Final   */
#define  ARB_TEST_FINAL_FRAME    16       /* 16 TEST Response Final       */
#define  ARB_TEST_NOTFINAL_FRAME 18       /* 18 TEST Response Not Final   */
#define  ARB_UNIDENTIFIED_FRAME  20       /* 20 Other Or Unidentified     */

/* DIRInitErrorCode Equates                                               */

#define  INIT_SUCCESSFUL         0x00     /* 00h Successful               */
#define  INIT_DIAG_FAILED        0x20     /* 20h Diag Could Not Execute   */
#define  INIT_ROM_ERROR          0x22     /* 22h ROM/BIOS Diag Fail       */
#define  INIT_RAM_ERROR          0x24     /* 24h Shared RAM Diag Failed   */
#define  INIT_INSTRUCTION_ERROR  0x26     /* 26h Processor Inst Test Fail */
#define  INIT_INTERRUPT_ERROR    0x28     /* 28h Processor Int Test Fail  */
#define  INIT_INTERFACE_ERROR    0x2a     /* 2Ah S-AM I/F Reg Diags Fail  */
#define  INIT_PROTOCOL_ERROR     0x2c     /* 2Ch Prot Hndlr Diag Fail     */
#define  INIT_ADAPTER_ERROR      0x40     /* 40h Adapter Timer Failed     */
#define  INIT_WRITE_ERROR        0x42     /* 42h Cannot Write to S-RAM    */
#define  INIT_READ_ERROR         0x44     /* 44h Reading S-RAM Caused INT */
#define  INIT_WRITE_INT_ERROR    0x46     /* 46h Writing S-RAM no INT     */
#define  INIT_TIMED_OUT          0x48     /* 48h Init Timed Out           */

/* DIR.Initialize Equates                                                 */

#define  INIT_16_MBPS            0x01     /* INIsta-01 1==>16 Mbps; 0==>4 */
#define  INIT_DEFAULT_RAM_ADDR   0xd800   /* Shared RAM Default Address   */
#define  INIT_DEFAULT_RAM_SIZE   0x4000   /* Default S-Ram Size = 16k     */
#define  INIT_MMIO_SIZE          0x2000   /* BIOS/MMIO Domain Size = 8k   */
#define  INIT_FAST_PATH          0x20     /* Fast Path Tx supported       */
#define  INIT_MULTIPORT_BRIDGE   0x10     /* Multiport Bridge supported   */
#define  INIT_UTIL_MEASURE       0x08     /* Ring utilization supported   */

/* OpenOptions Bit Values                                                 */

#define  WRAP_INTERFACE_OPTION   0x0080   /* Bit 07 - Wrap Interface      */
#define  DIS_HARD_ERROR_OPTION   0x0040   /* Bit 06 - Disable Hard Error  */
#define  DIS_SOFT_ERROR_OPTION   0x0020   /* Bit 05 - Disable Soft Error  */
#define  PASS_ADAPTER_MAC_OPTION 0x0010   /* Bit 04 - Pass Adptr MAC Frm  */
#define  PASS_ATTEN_MAC_OPTION   0x0008   /* Bit 03 - Pass Att MAC Frames */
#define  RETURN_OPEN_OPTION      0x0002   /* Bit 01 - Return Open Parms   */
#define  PASS_BEACON_MAC_OPTION  0x0001   /* Bit 00 - Pass Beacon MAC Frm */
#define  CONTENDER_OPTION        0x8000   /* Bit 15 - Contender           */

/* OpenAdapterStructure Default Equates                                   */

#define  OPEN_FUNCTIONAL_ADDR    0x8000   /* 20 Func Add = 00 80 00 00    */
#define  OPEN_GROUP_ADDRESS      0x0000   /* 16 Group Address             */
#define  OPEN_MAX_MEMBERS        00       /* 35 Max Mem Per Group SAP     */
#define  OPEN_MAX_GROUP_SAPS     00       /* 34 Max Num of Group SAPs     */
#define  OPEN_LINK_STATIONS      00       /* 33 Max Num of Link Stations  */
#define  OPEN_MAX_SAPS           1        /* 32 Max Num of SAPs           */
#define  OPEN_RX_BUFFERS         8        /* 24 Num of Receive  Buffers   */
#define  OPEN_RX_BUFFS_HIGH      0        /* 24 Num of Receive  Buffers   */
#define  OPEN_RX_BUFFS_LOW       8        /* 24 Num of Receive  Buffers   */
#define  OPEN_TX_BUFFERS         2        /* 29 Num of Transmit Buffers   */
#define  OPEN_OPTIONS            DIS_SOFT_ERROR_OPTION * 256 /* 08 Open   */
#define  OPEN_OPTIONS_HIGH       0        /* 08 Open   */
#define  OPEN_OPTIONS_LOW        0x08     /* 08 Open   */
#define  OPEN_GROUP_ONE_TI       25       /* 38 DLC Tmr Ti, Gp 01 (  1 -   2 Seconds) */
#define  OPEN_GROUP_TWO_TI       125      /* 41 DLC Tmr Ti, Gp 02 (  5 -  10 Seconds) */
#define  OPEN_GROUP_ONE_T1       5        /* 36 DLC Tmr T1, Gp 01 (200 - 400 Mills)   */
#define  OPEN_GROUP_TWO_T1       25       /* 39 DLC Tmr T1, Gp 02 (  1 -   2 Seconds) */
#define  OPEN_GROUP_ONE_T2       1        /* 37 DLC Tmr T2, Gp 01 ( 40 -  80 Mills)   */
#define  OPEN_GROUP_TWO_T2       10       /* 40 DLC Tmr T2, Gp 02 (400 - 800 Mills)   */
#define  OPEN_RX_LENGTH          320      /* 26 Len of Rx Buffers         */
#define  OPEN_RX_LENGTH_HI       0x01     /* 26 Len of Rx Buffers         */
#define  OPEN_RX_LENGTH_LO       0x40     /* 26 Len of Rx Buffers         */
#define  OPEN_TX_LENGTH          2048     /* 28 Len of Tx Buffers         */

/* OpenSRBErrorCode Equates                                               */

#define  OPEN_ERROR_LOBE_TEST    0x10     /* 10 Lobe Media Test           */
#define  OPEN_ERROR_INSERTION    0x20     /* 20 Physical Insertion        */
#define  OPEN_ERROR_ADDRESS      0x30     /* 30 Address Verification      */
#define  OPEN_ERROR_ROLL_CALL    0x40     /* 40 Roll Call Poll            */
#define  OPEN_ERROR_REQUEST      0x50     /* 50 Request Parameters        */

#define  OPEN_ERROR_FUNCTION     0x01     /* 01 Function Failure          */
#define  OPEN_ERROR_SIGNAL_LOSS  0x02     /* 02 Signal Loss               */
#define  OPEN_ERROR_WIRE_FAULT   0x03     /* 03 Wire Fault                */
#define  OPEN_ERROR_FREQUENCY    0x04     /* 04 Frequency Error           */
#define  OPEN_ERROR_TIMEOUT      0x05     /* 05 Timeout                   */
#define  OPEN_ERROR_RING         0x06     /* 06 Ring Failure              */
#define  OPEN_ERROR_BEACONING    0x07     /* 07 Ring Beaconing            */
#define  OPEN_ERROR_NODE         0x08     /* 08 Duplicate Node Addr       */
#define  OPEN_ERROR_PARM_REQUEST 0x09     /* 09 Parameter Request         */
#define  OPEN_ERROR_REMOVED      0x0a     /* 10 Remove Received           */
#define  OPEN_ERROR_IMPL_FORCED  0x0b     /* 11 IMPL Force Received       */

/* DLCOpenSAPOptions Bit Values                                           */

#define  DLC_OPEN_SAP_MASK       0xe0     /* Priority Mask Field          */
#define  DLC_OPEN_SAP_01         0x20     /* Priority 01                  */
#define  DLC_OPEN_SAP_XIDS       0x08     /* Bit 3 - XIDs Passed To Appl  */
#define  DLC_OPEN_SAP_INDIVIDUAL 0x04     /* Bit 2 - Individual SAP       */
#define  DLC_OPEN_SAP_GROUP      0x02     /* Bit 1 - Group      SAP       */
#define  DLC_OPEN_SAP_GROUP_SAP  0x01     /* Bit 0 - SAP is Member of Gp  */

/* DLCOpenSAP Equates                                                     */

#define  DLC_OPEN_LINK_STATIONS  0        /* 18 Num Link Stations to Res  */
#define  DLC_OPEN_SAP_OPTIONS    DLC_OPEN_SAP_INDIVIDUAL /* 17 SAP Optns  */
#define  DLC_OPEN_SAP            0xe0     /* 16 SAP Value To Be Assigned  */
#define  DLC_OPEN_TIMER_T1       0        /* 06 DLC Tmr T1, Resp Timer    */
#define  DLC_OPEN_TIMER_T2       0        /* 07 DLC Tmr T2, Ackn Timer    */
#define  DLC_OPEN_TIMER_TI       0        /* 08 DLC Tmr Ti, Inac Timer    */
#define  DLC_OPEN_STATION_ID     0        /* 05 Link Station ID           */
#define  DLC_OPEN_MAX_IFIELD     600      /* 14 Max Receive I-Field Len   */
#define  DLC_OPEN_MAX_RETRIES    8        /* 12 Max Retry Count (N2 Val)  */
#define  DLC_OPEN_MAX_WINDOW_INC 1        /* 11 Dynamic Window Inc Value  */
#define  DLC_OPEN_RX_WO_ACK      1        /* 10 MAX Rxs W/o a Xmit ACK    */
#define  DLC_OPEN_TX_WO_ACK      2        /* 09 Max Xmits W/o A Rx ACK    */

/* Program Option Select Equates                                          */

#define  TOKEN_ID_LO             0x0001   /* POS Reg 00 ID LOW  Byte      */
#define  TOKEN_ID_HI             0x00E0   /* POS Reg 01 ID High Byte      */
#define  PRIMARY_ADAPTER_BIT     0x0001   /* POS Reg 03 Pri(0)/Alt(1)     */

#ifndef USE_NBI
#define  CARD_ENABLE_BIT         0x0001   /* POS Reg 02 Card Enable Bit   */
#define  POS_IO_PORT             0x0100   /* Prgm Option Sel I/O Port @   */
#define  SLOT_0                  0x0008   /* Slot 00 Start Value          */
#define  MAXIMUM_SLOTS           0x000F   /* Maximum Slot Number          */
#define  SLOT_SELECT_REG         0x0096   /* POS Slot Select Register     */
#endif

#define  PRODUCT_ID_LEN          0x0002   /* 2 byte product ID for MCA    */
#define   MCA_CFG_BLOCK_SIZE      0x0008   /* Config Block size for MCA     */


/* RCBFrameStatus Equates (Last Buffer Only)                              */

#define  RCB_ADDRESS_RECOGNIZED  0x88     /* 88 Add Recognized Indicator  */
#define  RCB_FRAME_COPIED        0x44     /* 44 Frame copied indicator    */

#define  SRB_SIZE                28       /* 28 size of SRB in shared-ram */
#define  SSB_SIZE                20       /* 20 size of SSB in shared-ram */

/* SRBCommand Equates                                                     */

#define  SRB_DIR_INTERRUPT       0x00     /* 00 DIR.Interrupt             */
#define  SRB_DIR_MODIFY_PARMS    0x01     /* 01 DIR.Modify.Open.Parms     */
#define  SRB_DIR_RESTORE_PARMS   0x02     /* 02 DIR.Restore.Open.Parms    */
#define  SRB_OPEN_ADAPTER        0x03     /* 03 DIR.Open.Adapter          */
#define  SRB_CLOSE_ADAPTER       0x04     /* 04 DIR.Close.Adapter         */
#define  SRB_DIR_SET_GROUP_ADDR  0x06     /* 06 DIR.Set.Group.Address     */
#define  SRB_DIR_SET_FUNC_ADDR   0x07     /* 07 DIR.Set.Functional.Address*/
#define  SRB_DIR_READ_LOG        0x08     /* 08 DIR.Read.Log              */
#define  SRB_SET_BRIDGE          0x09     /* 09 Set.Bridge.Parameter      */
#define  SRB_TX_DIR_FRAME        0x0a     /* 0A XMT.DIR.Frame             */
#define  SRB_TX_I_FRAME          0x0b     /* 0B XMT.I.Frame               */
#define  SRB_CONFIGURE_BRIDGE    0x0c     /* 0C DIR.Configure.Bridge.RAM  */
#define  SRB_TX_UI_FRAME         0x0d     /* 0D XMT.UI.Frame              */
#define  SRB_TX_XID_COMMAND      0x0e     /* 0E XMT.XID.Command           */
#define  SRB_TX_XID_RESPONSE     0x0f     /* 0F XMT.XID.Response.Final    */
#define  SRB_TX_XID_NO_RESPONSE  0x10     /* 10 XMT.XID.Response.Not.Final*/
#define  SRB_TX_TEST_FRAME       0x11     /* 11 XMT.TEST.Frame            */
#define  SRB_DLC_RESET           0x14     /* 14 DLC.Reset                 */
#define  SRB_DLC_OPEN_SAP        0x15     /* 15 DLC.Open.SAP              */
#define  SRB_DLC_CLOSE_SAP       0x16     /* 16 DLC.Close.SAP             */
#define  SRB_DLC_REALLOC_SAP     0x17     /* 17 DLC.Reallocate.SAP        */
#define  SRB_DLC_OPEN_STATION    0x19     /* 19 DLC.Open.Station          */
#define  SRB_DLC_CLOSE_STATION   0x1a     /* 1A DLC.Close.Station         */
#define  SRB_DLC_CONNECT_STATION 0x1b     /* 1B DLC.Connect.Station       */
#define  SRB_DLC_MODIFY          0x1c     /* 1C DLC.Modify                */
#define  SRB_DLC_FLOW_CONTROL    0x1d     /* 1D DLC.Flow.Control          */
#define  SRB_DLC_STATISTICS      0x1e     /* 1E DLC.Statistics            */
#define  SRB_INIT_COMPLETE       0x80     /* 80 DIR.Initialize Complete   */
#define  SRB_INVALID             0xff     /* FF INVALID Command Code      */

/* SRBReturnCode Equates                                                  */

#define  SRB_SUCCESSFUL          0x00     /* 00 Successful                */
#define  SRB_INVALID_COMMAND     0x01     /* 01 Invalid Command Code      */
#define  SRB_DUPLICATE_COMMAND   0x02     /* 02 Duplicate Command         */
#define  SRB_ALREADY_OPEN        0x03     /* 03 Adapter Already Open      */
#define  SRB_ADAPTER_NOT_OPEN    0x04     /* 04 Adapter Not Open          */
#define  SRB_NO_PARMS            0x05     /* 05 Req Parms Not Provided    */
#define  SRB_INVALID_OPTIONS     0x06     /* 06 Options Invalid Or Incomp */
#define  SRB_COMMAND_CANCELLED   0x07     /* 07 Comm Canc, Disaster Strck */
#define  SRB_UNAUTHORIZED        0x08     /* 08 Unauthorized Acc Priority */
#define  SRB_NOT_INITIALIZED     0x09     /* 09 Adapter Not Initialized   */
#define  SRB_CANCELLED_BY_USER   0x0a     /* 0A Comm Cancelled By User    */
#define  SRB_CANCELLED_CLOSED    0x0b     /* 0B Comm Cancelled Adptr Clsd */
#define  SRB_COMPLETE_CLOSED     0x0c     /* 0C Cmd Complete Adptr Closed */
#define  SRB_INVALID_BRIDGE      0x0d     /* 0D Invld Bridge Parms        */
#define  SRB_INVALID_RAM_SEG     0x14     /* 14 Invld S-RAM Segment       */
#define  SRB_NO_BUFFERS          0x20     /* 20 Lost Data, No Buffers     */
#define  SRB_NOT_ENOUGH_BUFFERS  0x21     /* 21 Lost Data, Not Engh Buffs */
#define  SRB_TX_ERROR            0x22     /* 22 Error On Frame Xmit       */
#define  SRB_FRAME_ERROR         0x23     /* 23 Frame Or Strip Error      */
#define  SRB_MAC_ERROR           0x24     /* 24 Unauthorized Mac Frame    */
#define  SRB_TOO_MANY_COMMANDS   0x25     /* 25 Maximum Commands Exceeded */
#define  SRB_BAD_CORRELATOR      0x26     /* 26 Unrecognized Command Corr */
#define  SRB_LINK_NOT_TXING      0x27     /* 27 Link No Longer Txing      */
#define  SRB_BAD_FRAME_LENGTH    0x28     /* 28 Invalid Tx Frame Length   */
#define  SRB_BAD_BRIDGE_PARM     0x2d     /* 2D Bridge Parameters Not Set */
#define  SRB_RX_BUFFER_NOT_OPEN  0x30     /* 30 Inadequate Rx Buff 4 Open */
#define  SRB_INVALID_NODE        0x32     /* 32 Invalid Node Address      */
#define  SRB_INVALID_RX_LENGTH   0x33     /* 33 Invalid Receive Buff Len  */
#define  SRB_INVALID_TX_LENGTH   0x34     /* 34 Invalid Transmit Buff Len */
#define  SRB_INVALID_STATION_ID  0x40     /* 40 Invalid Station ID        */
#define  SRB_PROTOCOL_ERROR      0x41     /* 41 Protocol Error            */
#define  SRB_PARM_MAXED_OUT      0x42     /* 42 Parameter Exceeded Max    */
#define  SRB_INVALID_SAP         0x43     /* 43 Invalid SAP.Val           */
#define  SRB_BAD_HEADER_LENGTH   0x44     /* 44 Invalid Header Length     */
#define  SRB_GROUP_IN_BAD_SAP    0x45     /* 45 Group Member In Bad SAP   */
#define  SRB_NO_RESOURCES        0x46     /* 46 Resources Not Available   */
#define  SRB_SAP_LINK_OPENED     0x47     /* 47 SAP Has Link Station Open */
#define  SRB_CANNOT_CLOSE_GROUP  0x48     /* 48 Group SAP Cannot Close    */
#define  SRB_GROUP_MAX_MEMBERS   0x49     /* 49 Group SAP Reached Max Mem */
#define  SRB_SEQ_ERROR_CLOSED    0x4a     /* 4A Seq Error - DLC Cls In Pr */
#define  SRB_CLOSED              0x4b     /* 4B Closed W/O Remote Ack     */
#define  SRB_SEQ_ERROR           0x4c     /* 4C Seq Error - Outstndg Comm */
#define  SRB_BAD_LS_CONNECTION   0x4d     /* 4D Unsuccessful LS Connction */
#define  SRB_MEMBER_NOT_IN_GROUP 0x4e     /* 4E Mem SAP Not In Gp SAP Lst */
#define  SRB_BAD_REMOTE_ADDR     0x4f     /* 4F Invalid Remote Address    */
#define  SRB_NOT_PROCESSED       0xfe     /* FE Command NOT Processed     */
#define  SRB_IN_PROCESS          0xff     /* FF Command In Process        */

/* Source Routing Driver Send Control EQUates; ESI = 0000 0000            */

#define  ROUTING_LOAD            00                       /* AL = 00 ==> EBX = Board Number to LOAD      */
#define  ROUTING_UNLOAD          ROUTING_LOAD+01          /* AL = 01 ==> EBX = Board Number to UNLOAD    */
#define  ROUTING_CLEAR           ROUTING_UNLOAD+01        /* AL = 02 ==> EBX = Board Number to CLEAR     */
#define  ROUTING_DEFAULT_BROAD   ROUTING_CLEAR+01         /* AL = 03 ==> AH = DEFault   Broadcast Route  */
#define  ROUTING_GENERAL_BROAD   ROUTING_DEFAULT_BROAD+01 /* AL = 04 ==> AH = GENERAL   Broadcast Route  */
#define  ROUTING_MULTICAST       ROUTING_GENERAL_BROAD+01 /* AL = 05 ==> AH = MULTICAST Broadcast Route  */
#define  ROUTING_RESPONSE        ROUTING_MULTICAST+01     /* AL = 06 ==> AH = Broadcasted Response Type  */
#define  ROUTING_TIMEOUT         ROUTING_RESPONSE+01      /* AL = 07 ==> AH = Last Rcv Time Timeout      */
#define  ROUTING_REMOVE_NODE     ROUTING_TIMEOUT+01       /* AL = 08 ==> EDI = Address of NODE to REMOVE */
#define  ROUTING_MAX_REQUEST     ROUTING_REMOVE_NODE+01   /* AL = Maximum Request Code                   */

/* Token-Ring Interrupt Level Equates                                     */

#define  ADAPTER_IRQ_2           00       /* 00 = IRQ 02                  */
#define  ADAPTER_IRQ_3           01       /* 01 = IRQ 03                  */
#define  ADAPTER_IRQ_6           02       /* 02 = IRQ 06 (PC) IRQ 10 (MC) */
#define  ADAPTER_IRQ_7           03       /* 03 = IRQ 07 (PC) IRQ 11 (MC) */
#define  ADAPTER_IRQ_MASK        03       /*      IRQ Msk 4 IN AL,A20h Rd */

/* Token-Ring PIO Register Equates                                        */

#define  PRIMARY_PIO             0xa20    /* A24 BIOS/MMIO Swtchs IGNORED */
#define  SECONDARY_PIO           0xa24    /* A20 BIOS/MMIO Swtchs IGNORED */
#define  RESET_IRQ_PORT          0x2f0    /* 2Fn IGNORED  Reset IRQ       */

#define  LOW_PRIMARY_PIO         0x20     /* low order byte of PRIMARY_PIO*/

/* TxDSAP, SSAP, ControlByte DLC Control Field Equates                    */

#define  TX_8022_SNAP            0x03aaaa        /* IP Stndrd DLC Header  */
#define  TX_SNAP_HEADER_SIZE     8               /* IP Stndrd Header Size */
#define  TX_MAC_FRAME_PID        0xffffff        /* MAC Frame Protocol ID */
#define  DEFAULT_TX_DSAP         DLC_OPEN_SAP    /* E0 Destination SAP    */
#define  DEFAULT_TX_SSAP         DEFAULT_TX_DSAP /* E0 Source      SAP    */
#define  DEFAULT_TX_CTRL         0x03            /* 03 Control Byte 03    */

/* MediaID equates                                                        */

#define  RAM_PAGE_RANGE0         8196/16  /* 110 Memory    00 Range       */
#define  RAM_PAGE_RANGE1         8196/16  /* 116 Memory    01 Range       */

/* Configuration Table equates                                            */

#define  MODE_FLAGS     MM_MULTICAST_BIT | MM_C_HSM_BIT \
                        | MM_RAW_SENDS_BIT | MM_FRAG_RECEIVES_BIT
#define  FLAGS          0
#define  SHARING_FLAGS  MS_SHUTDOWN_BIT      /* Start in shutdown state. */

/* miscellaneous defines */

#define  SIGNATURE_SIZE    22

#define  MMIO_SEGMENT_MASK       0xfc        /* MMIO segment mask         */
#define  MMIO_BIT                0x8000      /* MMIO segment bit          */
#define  INTERRUPT_MASK          0x03        /* Interrupt mask            */

/* TCBWorkSpace defines                                                   */

#define     TCB_LINK          0
#define     TCB_CORRELATOR    1


/**************************************************************************\
**
**    HSM Structures that have been turned into defines
**
\**************************************************************************/

/* Token-Ring MMIO Port Structure equivalents                             */

#define  READ_MMIO               0x00        /* 00 Rd BIOS/MMIO Swtchs    */
#define  ADAPTER_RESET           0x01        /* 01 Adapter Reset          */
#define  RELEASE_ADAPTER_RESET   0x02        /* 02 Release Adapter Rst    */
#define  RESET_IRQ               0x03        /* 03 Reset IRQ (Hog)        */

/* Token-Ring MMIO offset equivalents                                     */

#define  RAM_RELOCATION_REG      0x1E00
#define  WRITE_REGION_BASE       0x1E02
#define  WRITE_WINDOW_OPEN_REG   0x1E04
#define  WRITE_WINDOW_CLOSE_REG  0x1E06
#define  INT_STATUS_TO_PC        0x1E08
#define  INT_STATUS_TO_ADAPTER   0x1E0A
#define  TIMER_CONTROL_REG       0x1E0C
#define  TIMER_VALUE_REG         0x1E0E
#define  RESERVED1               0x1E10
#define  RAM_PAGE_REG            0x1E18
#define  RESERVED2               0x1E1A
#define  NODE_ADDRESS_OFFSET     0x1F00
#define  SIGNATURE_OFFSET        0x1F30
#define  ADAPTER_ID_OFFSET       0x1FA0



/* FastPathControlArea                                                    */

#define  FP_BUFFER_COUNT         0x00
#define  FP_FREE_Q_HEAD          0x02
#define  FP_FREE_Q_TAIL          0x04
#define  FP_ADAPTER_Q_TAIL       0x06
#define  FP_C_BUFFER_SIZE        0x08
#define  FP_COMPLETION_Q_TAIL    0x0a
#define  FP_RESERVED             0x0c

/* Fast Path Transmit Buffer Structure                                    */

#define  FP_TX_COMMAND           0x00
#define  FP_TX_CORRELATOR        0x01
#define  FP_TX_RETCODE           0x02
#define  FP_TX_RESERVED1         0x03
#define  FP_TX_STATION_ID        0x04
#define  FP_TX_FRAME_LENGTH      0x06
#define  FP_TX_HEADER_LENGTH     0x08
#define  FP_TX_RSAP_VALUE        0x09
#define  FP_TX_RESERVED2         0x0a
#define  FP_TX_LAST_BUFFER       0x0c
#define  FP_TX_FRAME_POINTER     0x0e
#define  FP_TX_NEXT_BUFFER       0x10
#define  FP_TX_STATUS            0x12
#define  FP_TX_STRIPPED_FS       0x13
#define  FP_TX_BUFFER_LENGTH     0x14
#define  FP_TX_FRAME_DATA        0x16

/* MMIO Write Structure                                                   */

#define  STORE_OFFSET            0x00
#define  AND_OFFSET              0x20
#define  OR_OFFSET               0x40

/* DIR.Initialize SRB Response Structure                                  */

#define  DIR_INIT_COMMAND_CODE   0x00
#define  DIR_INIT_STATUS         0x01
#define  DIR_INIT_RESERVED       0x02
#define  DIR_INIT_ERROR_CODE     0x06
#define  DIR_INIT_NODE_ADDRESS   0x08
#define  DIR_INIT_MICROC_LEVEL   0x0a
#define  DIR_INIT_ADPTR_ADDRESS  0x0c
#define  DIR_INIT_ADPTR_PM_ADDR  0x0e
#define  DIR_INIT_MAC_BUFFER     0x10

/* Adapter Status Block Structure                                         */

#define  ASB_COMMAND_CODE        0x00
#define  ASB_CORRELATOR          0x01
#define  ASB_RETURN_CODE         0x02
#define  ASB_RESERVED            0x03
#define  ASB_SAP                 0x04
#define  ASB_LINK_STATION        0x05
#define  ASB_RX_BUFFER           0x06
#define  ASB_HEADER_LENGTH       0x08
#define  ASB_REMOTE_SAP          0x09

#define  ASB_STATION_ID          0x04
#define  ASB_FRAME_LENGTH        0x06

/* ARB 81h - Received Data Structure                                      */

#define  ARB_RX_COMMAND_CODE      0x00
#define  ARB_RX_RESERVED          0x01
#define  ARB_RX_SAP               0x04
#define  ARB_RX_LINK_STATION      0x05
#define  ARB_RX_FIRST_BUFFER      0x06
#define  ARB_RX_LAN_HEADER_LENGTH 0x08
#define  ARB_RX_HEADER_LENGTH     0x09
#define  ARB_RX_FRAME_LENGTH      0x0a
#define  ARB_RX_MESSAGE_TYPE      0x0c

/* ARB 82h - Transmit Data Request Structure                              */

#define  ARB_TX_COMMAND_CODE     0x00
#define  ARB_TX_CORRELATOR       0x01
#define  ARB_TX_RESERVED         0x02
#define  ARB_TX_SAP              0x04
#define  ARB_TX_LINK_STATION     0x05
#define  ARB_TX_DHB_ADDRESS      0x06

/* ARB 83h - DLC Status Structure                                         */

#define  ARB_DLC_COMMAND_CODE    0x00
#define  ARB_DLC_RESERVED        0x01
#define  ARB_DLC_SAP             0x04
#define  ARB_DLC_LINK_STATION    0x05
#define  ARB_DLC_STAT            0x06
#define  ARB_DLC_FRAME_REJECT    0x08
#define  ARB_DLC_NEW_ACCESS      0x0d
#define  ARB_DLC_RING_ADDRESS    0x0e
#define  ARB_DLC_REMOTE_SAP      0x14

/* Transmit buffer structure                                              */

#define  TX_ACCESS_CONTROL       0x00
#define  TX_FRAME_CONTROL        0x01
#define  TX_DEST_NODE_ADDRESS    0x02
#define  TX_SOURCE_NODE_ADDRESS  0x08
#define  TX_DSAP                 0x0e
#define  TX_SSAP                 0x0f
#define  TX_CONTROL_BYTE         0x10
#define  TX_DATA                 0x11

#define  TX_ROUTING_INFO         0x0e

/* System Request Block/ System Status Block Structure                    */

#define  SRB_COMMAND             0x00
#define  SRB_CMD_CORRELATE       0x01
#define  SRB_RETURN_CODE         0x02
#define  SRB_RESERVED            0x03
#define  SRB_SERVICE_ACCESS_PT   0x04
#define  SRB_LINK_STATION        0x05
#define  SRB_FUNCTIONAL_ADDRESS  0x06

/* DIR.Open.Adapter SRB Response Structure                                */

#define  OPEN_SRB_COMMAND_CODE   0x00
#define  OPEN_SRB_RESERVED1      0x01
#define  OPEN_SRB_RETURN_CODE    0x02
#define  OPEN_SRB_RESERVED2      0x03
#define  OPEN_SRB_ERROR_CODE     0x06
#define  OPEN_ASB_ADDRESS        0x08
#define  OPEN_SRB_ADDRESS        0x0a
#define  OPEN_ARB_ADDRESS        0x0c
#define  OPEN_SSB_ADDRESS        0x0e

/* DIR.Open.Adapter SRB Structure                                         */

#define  SOPEN_COMMAND_CODE       0x00
#define  SOPEN_RESERVED1          0x01
#define  SOPEN_RETURN_CODE        0x02
#define  SOPEN_RESERVED2          0x03
#define  SOPEN_OPTIONS            0x08
#define  SOPEN_NODE_ADDRESS       0x0a
#define  SOPEN_GROUP_ADDRESS      0x10
#define  SOPEN_FUNCTIONAL_ADDR    0x14
#define  SOPEN_RX_BUFFERS         0x18
#define  SOPEN_RX_LENGTH          0x1a
#define  SOPEN_TX_LENGTH          0x1c
#define  SOPEN_TX_BUFFERS         0x1e
#define  SOPEN_RESERVED3          0x1f
#define  SOPEN_MAXIMUM_SAPS       0x20
#define  SOPEN_MAX_LINK_STATIONS  0x21
#define  SOPEN_MAX_GROUP_SAPS     0x22
#define  SOPEN_MAX_MEMBERS        0x23
#define  SOPEN_GROUP_ONE_T1       0x24
#define  SOPEN_GROUP_ONE_T2       0x25
#define  SOPEN_GROUP_ONE_Ti       0x26
#define  SOPEN_GROUP_TWO_T1       0x27
#define  SOPEN_GROUP_TWO_T2       0x28
#define  SOPEN_GROUP_TWO_Ti       0x29
#define  SOPEN_PRODUCT_ID         0x2a

/* DIRInitAdapterParmsAddr Structure                                      */

#define  PARMS_PHYS_ADDR         0x00
#define  PARMS_UP_NODE_ADDR      0x04
#define  PARMS_UP_PHYS_ADDR      0x0a
#define  PARMS_POLL_ADDR         0x0e
#define  PARMS_RESERVED1         0x14
#define  PARMS_ACC_PRIORITY      0x16
#define  PARMS_SOURCE_CLASS      0x18
#define  PARMS_ATT_CODE          0x1a
#define  PARMS_SOURCE_ADDRESS    0x1c
#define  PARMS_BEACON_TYPE       0x22
#define  PARMS_MAJOR_VECTOR      0x24
#define  PARMS_NETW_STATUS       0x26
#define  PARMS_SOFT_ERROR        0x28
#define  PARMS_FE_ERROR          0x2a
#define  PARMS_LOCAL_RING        0x2c
#define  PARMS_MON_ERROR         0x2e
#define  PARMS_BEACON_TRANSMIT   0x30
#define  PARMS_BEACON_RECEIVE    0x32
#define  PARMS_FRAME_CORREL      0x34
#define  PARMS_BEACON_NAUN       0x36
#define  PARMS_RESERVED2         0x3c
#define  PARMS_BEACON_PHYS       0x40

/* Configure Fast Path RAM Return SRB structure                           */

#define  FPR_COMMAND             0x00
#define  FPR_RESERVED1           0x01
#define  FPR_RET_CODE            0x02
#define  FPR_RESERVED2           0x03
#define  FPR_FAST_PATH_XMIT      0x08
#define  FPR_SRB_ADDRESS         0x0a

/* ARB 84h - Ring Status Change Structure                                 */

#define  RING_COMMAND_CODE       0x00
#define  RING_RESERVED           0x01
#define  RING_NEW_STATUS0        0x06
#define  RING_NEW_STATUS1        0x07

/* RCB -- Receive Buffer Format For ARB 81h -- Recieve Data               */

#define  RCB_NEXT_BUFFER         0x00
#define  RCB_RESERVED            0x02
#define  RCB_FRAME_STATUS        0x03
#define  RCB_BUFFER_LENGTH       0x04
#define  RCB_FRAME_DATA          0x06

#define  OPEN_ADAPTER_SIZE       60
#define  CONFIG_FAST_PATH_SIZE   12
#define  CONFIG_BRIDGE_SIZE      10

#ifdef BROUTER

/* Brouter status bits                                                    */

#define  TWO_WAY_SR              0x00010000
#define  THREE_WAY_SR            0x00020000
#define  STE_FILTER              0x00200000
#define  VARIABLE_BR_NUM         0x00400000
#define  SR_SUPPORT              0x00800000
#define  TRANS_DA_AND_SA_SUPPORT 0x90000000
#define  TRANS_DA_SUPPORT        0xa0000000
#define  SR_AND_TRANS_SUPPORT    0xc0000000
#define  TRANS_SUPPORT           0x80000000

#define  BROUTER_STATUS          SR_SUPPORT | VARIABLE_BR_NUM | TWO_WAY_SR

/* Bridge SRB Response structure                                          */

#define  BSRB_COMMAND            0x00
#define  BSRB_RESERVED1          0x01
#define  BSRB_RETURN_CODE        0x02
#define  BSRB_RESERVED2          0x03
#define  BSRB_TX_OFFSET          0x08
#define  BSRB_SRB_ADDRESS        0x0a

/* Bridge Transmit Control Area                                           */

#define  BTCA_RESERVED1       0x00
#define  BTCA_INPUT_COUNT     0x02
#define  BTCA_OUTPUT_COUNT    0x03
#define  BTCA_RETURN_COUNT    0x04
#define  BTCA_RESERVED2       0x05
#define  BTCA_MAX_BUFFERS     0x06
#define  BTCA_NEXT_BUFFER     0x08
#define  BTCA_OLD_BUFFER      0x0a
#define  BTCA_RESERVED3       0x0c

/* Bridge Transmit Buffer                                                 */

#define  BTB_LAST_BUFFER      0x00
#define  BTB_FRAME_LENGTH     0x00
#define  BTB_BUFFER_POINTER   0x02
#define  BTB_XMIT_CONTROL     0x04
#define  BTB_STRIP_FS         0x05
#define  BTB_BUFFER_LENGTH    0x06
#define  BTB_FRAME_DATA       0x08
#define  BTB_NUMBER_BUFFERS   0x08

#endif

/**************************************************************************\
**
**    Token-Ring Structures
**
\**************************************************************************/

typedef struct
{
   UINT8    AdapterBIOSArea       [0x1e00];     /* Adapter BIOS Area      */
   UINT8    RAMRelocationRegister      [2];     /* 1E00                   */
   UINT8    WriteRegionBase            [2];     /* 1E02                   */
   UINT8    WriteWindowOpenRegister    [2];     /* 1E04                   */
   UINT8    WriteWindowCloseRegister   [2];     /* 1E06                   */
   UINT8    IntStatusToPC              [2];     /* 1E08                   */
   UINT8    IntStatusToAdapter         [2];     /* 1E0A                   */
   UINT8    TimerControlRegister       [2];     /* 1E0C                   */
   UINT8    TimerValueRegister         [2];     /* 1E0E                   */
   UINT8    Reserved1                  [8];     /* 1E10 Reserved          */
   UINT8    RAMPageRegister            [2];     /* 1E18                   */
   UINT8    Reserved2               [0xe6];     /* 1E1A Reserved          */
   UINT8    NodeAddressOffset       [0x30];     /* 1F00                   */
   UINT8    SignatureOffset         [0x70];     /* 1F30                   */
   UINT8    AdapterIDOffset               ;     /* 1F70                   */
}
tAdapterControlRegion;

typedef struct
{
   UINT8    STOREOffset             [0x20];     /* offset 0x00            */
   UINT8    ANDOffset               [0x20];     /* offset 0x20            */
   UINT8    OROffset                      ;     /* offset 0x40            */
}
tMMIOWriteStructure;

/* ARB 84h - Ring Status Change Structure                                 */

typedef struct
{
   UINT8    RingCommandCode          ;       /* 00 ARB Cmd                */
   UINT8    Reserved              [5];       /* 01 ARB Res                */
   UINT8    RingNewStatus         [2];       /* 06 ARB NRS                */
}
tARBRingStatus;

/* ARB 81h - Received Data Structure                                      */

typedef struct
{
   UINT8    ARBRxCommandCode         ;       /* 00 ARB Cmd Code           */
   UINT8    Reserved              [3];       /* 01 ARB RESERVED           */
   UINT8    ARBRxSAP                 ;       /* 04 Serv Acc Pnt           */
   UINT8    ARBRxLinkStation         ;       /* 05 Link Station           */
   UINT8    ARBRxFirstBuffer      [2];       /* 06 1st Rx Buff            */
   UINT8    ARBRxLanHeaderLength     ;       /* 08 LAN Hdr Len            */
   UINT8    ARBRxHeaderLength        ;       /* 09 DLC Hdr Len            */
   UINT8    ARBRxFrameLength      [2];       /* 10 Ent Frm Len            */
   UINT8    ARBRxMessageType         ;       /* 12 Message Type           */
}
tARBReceivedData;

/* ARB 82h - Transmit Data Request Structure                              */

typedef struct
{
   UINT8    ARBTxCommandCode         ;       /* 00 ARB Cmd Code           */
   UINT8    ARBTxCorrelator          ;       /* 01 Tx Cmd Crltr           */
   UINT8    Reserved              [2];       /* 02 ARB RESERVED           */
   UINT8    ARBTxSAP                 ;       /* 04 Serv Acc Pnt           */
   UINT8    ARBTxLinkStation         ;       /* 05 Link Station           */
   UINT8    ARBTxDHBAddress       [2];       /* 06 DHB Address            */
}
tARBTransmitData;

/* ARB 83h - DLC Status Structure                                         */

typedef struct
{
   UINT8    ARBDLCCommandCode        ;       /* 00 ARB Cmd Code           */
   UINT8    Reserved              [3];       /* 01 ARB RESERVED           */
   UINT8    ARBDLCSAP                ;       /* 04 Serv Acc Point         */
   UINT8    ARBDLCLinkStation        ;       /* 05 Link Station           */
   UINT8    ARBDLCStat            [2];       /* 06 Status                 */
   UINT8    ARBDLCFrameReject     [5];       /* 08 Frame Rej Data         */
   UINT8    ARBDLCNewAccess          ;       /* 13 New Ac Priority        */
   UINT8    ARBDLCRingAddress     [6];       /* 14 Phys Ring Add          */
   UINT8    ARBDLCRemoteSAP          ;       /* 20 Rmt Sttn SAP Val       */
}
tARBDLCStatus;

/* Adapter Status Block Structure                                         */

typedef struct
{
   UINT8    ASBCommandCode           ;       /* 00 ASB Command Code       */
   UINT8    ASBCorrelator            ;       /* 01 ASB Correlator         */
   UINT8    ASBReturnCode            ;       /* 02 ASB Return Code        */
   UINT8    Reserved                 ;       /* 03 ASB RESERVED           */
   UINT8    ASBSAP                   ;       /* 04 ASB Serv Acc Pnt (SAP) */
   UINT8    ASBLinkStation           ;       /* 05 ASB Link Station  (LS) */
   UINT8    ASBRxBuffer           [2];       /* 06 ASB Rx Buffer (ARB 81) */
   UINT8    ASBHeaderLength          ;       /* 08 ASB Hdr Len   (ARB 82) */
   UINT8    ASBRemoteSAP             ;       /* 09 ASB R SAP Val (ARB 82) */
}
tASB;

typedef struct
{
   UINT8    Dup [4];
   UINT16   ASBStationID;
   UINT16   ASBFrameLength;
   UINT8    DupA [3];
}
tASBT;

/* DLC.Status Appendage Queue Element Structure                           */

typedef struct sDLCQueue
{
   struct sDLCQueue  *DLCQLink;              /* 00 Next DLC.Status Struct */
   UINT32            DLCQStatusAppendage;    /* 04 DLC.Status Appendage   */
   UINT16            DLCQStatusMask;         /* 08 DLC.Status Mask Value  */
   UINT8             DLCQParameter;          /* 10 DLC.Status User Parame */
   UINT8             DLCQStatusSAPID;        /* 11 DLC.Status SAP ID      */
}
tDLCQueue;

/* DIR.Initialize SRB Response Structure                                  */

typedef struct
{
   UINT8    DIRInitCommandCode         ;     /* 00 Cmd Code               */
   UINT8    DIRInitStatus              ;     /* 01 DIR.Init               */
   UINT8    Reserved                [4];     /* 02 RESERVED               */
   UINT8    DIRInitErrorCode        [2];     /* 06 Bg Up Code             */
   UINT8    DIRInitNodeAddress      [2];     /* 08 S-RAM Add              */
   UINT8    DIRInitMicrocodeLevel   [2];     /* 10 S-RAM Add              */
   UINT8    DIRInitAdapterAddress   [2];     /* 12 S-RAM Add              */
   UINT8    DIRInitAdapterParmsAddr [2];     /* 14 S-RAM Add              */
   UINT8    DIRInitMACBuffer        [2];     /* 16 S-RAM Add              */
}
tDIRInitialize;

/* DIRInitAdapterParmsAddr Structure                                      */

typedef struct
{
   UINT32   ParmsPhysAddr            ;       /* 00 Adapter Physical Addr  */
   UINT8    ParmsUPNodeAddr       [6];       /* 04 Next Act Up Node Addr  */
   UINT32   ParmsUPPhysAddr          ;       /* 0A Next Act Up Phys Addr  */
   UINT8    ParmsPollAddr         [6];       /* 0E Last Poll Addr         */
   UINT16   Reserved1                ;       /* 14 Reserved               */
   UINT16   ParmsAccPriority         ;       /* 16 Tx Access Priority     */
   UINT16   ParmsSourceClass         ;       /* 18 Src Class Authority    */
   UINT16   ParmsAttCode             ;       /* 1A Last Attention Code    */
   UINT8    ParmsSourceAddress    [6];       /* 1C Last Source Address    */
   UINT16   ParmsBeaconType          ;       /* 22 Last Beacon Type       */
   UINT16   ParmsMajorVector         ;       /* 24 Last Major Vector      */
   UINT16   ParmsNetwStatus          ;       /* 26 Network Status         */
   UINT16   ParmsSoftError           ;       /* 28 Soft Err Timer Value   */
   UINT16   ParmsFEError             ;       /* 2A Front End Err Cntr     */
   UINT16   ParmsLocalRing           ;       /* 2C Number of the Ring     */
   UINT16   ParmsMonError            ;       /* 2E Monitor Error Code     */
   UINT16   ParmsBeaconTransmit      ;       /* 30 Beacon Transmit Type   */
   UINT16   ParmsBeaconReceive       ;       /* 32 Beacon Receive Type    */
   UINT16   ParmsFrameCorrel         ;       /* 34 Frame Correlator Save  */
   UINT8    ParmsBeaconNAUN       [6];       /* 36 Beacon Station NAUN    */
   UINT32   Reserved2                ;       /* 3C Reserved               */
   UINT32   ParmsBeaconPhys          ;       /* 40 Beacon Sttn Phys Addr  */
}
tParmsStructure;

/* Configure Fast Path RAM SRB structure                                  */

typedef struct
{
   UINT8    FPCommand                ;       /* 12h - 00 Command          */
   UINT8    Reserved1                ;       /* 0    - 01 reserved         */
   UINT8    FPRetcode                ;       /* 0    - 02 Set by adptr ret */
   UINT8    Reserved2             [5];       /* 0   - 03 reserved         */
   UINT16   FPRAMSize                ;       /* 0    - 08 RAM size 2 Alloc */
   UINT8    FPBufferSize          [2];       /* 2,0 - 10 Size of Tx buff  */
}
tConfigFastPathStructure;

/* Configure Fast Path RAM Return SRB structure                           */

typedef struct
{
   UINT8    FPRCommand               ;       /* 00 Command                */
   UINT8    Reserved1                ;       /* 01 reserved               */
   UINT8    FPRRetcode               ;       /* 02 Ret code 4 this cmd    */
   UINT8    Reserved2             [5];       /* 03 reserved               */
   UINT16   FPRFastPathXmit          ;       /* 08 Off to Tx ctrl area    */
   UINT16   FPRSRBAddress            ;       /* 10 Off 4 next SRB addr    */
}
tConfigFastPathResponse;

/* Fast Path Transmit Control Area structure                              */

typedef struct
{
   UINT16   FPBufferCount            ;       /* 00 Number of buffers      */
   UINT16   FPFreeQHead              ;       /* 02 Off to first free buff */
   UINT16   FPFreeQTail              ;       /* 04 Off to last free buff  */
   UINT16   FPAdapterQTail           ;       /* 06 Off to next expected   */
   UINT16   FPCBufferSize            ;       /* 08 Size in bytes of buff  */
   UINT16   FPCompletionQTail        ;       /* 10 Off to last comp buff  */
   UINT8    Reserved              [4];       /* 12 reserved               */
}
tFastPathControlArea;

/* Fast Path Transmit Buffer Structure                                    */

typedef struct
{
   UINT8    FPTxCommand;                     /* 00 Tx command code        */
   UINT8    FPTxCorrelator;                  /* 01 Tx correlator(0-127)   */
   UINT8    FPTxRETCODE;                     /* 02 Ret Code for this cmd  */
   UINT8    Reserved1;                       /* 03 reserved               */
   UINT16   FPTxSTATIONID;                   /* 04 stat ID 2 tx this frm  */
   UINT16   FPTxFrameLength;                 /* 06 Tot of data in buffs   */
   UINT8    FPTxHeaderLength;                /* 08 Len of the Frame Hdr   */
   UINT8    FPTxRSAPValue;                   /* 09 DSAP value             */
   UINT16   Reserved2;                       /* 10 reserved               */
   UINT16   FPTxLastBuffer;                  /* 12 Offset in s-RAM        */
   UINT16   FPTxFramePointer;                /* 14 reserved               */
   UINT16   FPTxNextBuffer;                  /* 16 Offset to NEXT.BUFFER  */
   UINT8    FPTxStatus;                      /* 18 reserved               */
   UINT8    FPTxStrippedFS;                  /* 19 Final status ret       */
   UINT16   FPTxBufferLength;                /* 20 len of the frame data  */
   UINT8    FPTxFrameData;                   /* 22 frame data to be tx    */
}
tFastPathTxBuffer;

/* DIR.Open.Adapter SRB Structure                                         */

typedef struct
{
   UINT8    OpenCommandCode          ;       /* 00 Command Code           */
   UINT8    Reserved1                ;       /* 01 RESERVED               */
   UINT8    OpenReturnCode           ;       /* 02 Return Code            */
   UINT8    Reserved2             [5];       /* 03 RESERVED               */
   UINT8    OpenOptions           [2];       /* 08 Open Options           */
   UINT8    OpenNodeAddress       [6];       /* 10 Node Address           */
   UINT32   OpenGroupAddress         ;       /* 16 Group Address          */
   UINT32   OpenFunctionalAddr       ;       /* 20 Func Add = 00800000    */
   UINT8    OpenRxBuffers         [2];       /* 24 Num of Receive         */
   UINT8    OpenRxLength          [2];       /* 26 Len of Receive         */
   UINT16   OpenTxLength             ;       /* 28 Len of Transmit        */
   UINT8    OpenTxBuffers            ;       /* 30 Num of Tx Buffers      */
   UINT8    Reserved3                ;       /* 31 RESERVED               */
   UINT8    OpenMaximumSAPs          ;       /* 32 Max Num of SAPs        */
   UINT8    OpenMaxLinkStations      ;       /* 33 Max Num of Link Stats  */
   UINT8    OpenMaxGroupSAPs         ;       /* 34 Max Num of Group SAPs  */
   UINT8    OpenMaxMembers           ;       /* 35 Max Mem Per Group SAP  */
   UINT8    OpenGroupOneT1           ;       /* 36 DLC Timer T1, Group 01 */
   UINT8    OpenGroupOneT2           ;       /* 37 DLC Timer T2, Group 01 */
   UINT8    OpenGroupOneTi           ;       /* 38 DLC Timer Ti, Group 01 */
   UINT8    OpenGroupTwoT1           ;       /* 39 DLC Timer T1, Group 02 */
   UINT8    OpenGroupTwoT2           ;       /* 40 DLC Timer T2, Group 02 */
   UINT8    OpenGroupTwoTi           ;       /* 41 DLC Timer Ti, Group 02 */
   UINT8    OpenProductID        [18];       /* 42 Product ID             */
}
tDIROpenAdapter;

/* DIR.Open.Adapter SRB Response Structure                                */

typedef struct
{
   UINT8    OpenSRBCommandCode       ;       /* 00 Cmd Code               */
   UINT8    Reserved1                ;       /* 01 RESERVED               */
   UINT8    OpenSRBReturnCode        ;       /* 02 Return Code            */
   UINT8    Reserved2             [3];       /* 03 RESERVED               */
   UINT16   OpenSRBErrorCode         ;       /* 06 Open Error Code        */
   UINT16   OpenASBAddress           ;       /* 08 Shared RAM ASB Address */
   UINT16   OpenSRBAddress           ;       /* 10 Shared RAM SRB Address */
   UINT16   OpenARBAddress           ;       /* 12 Shared RAM ARB Address */
   UINT16   OpenSSBAddress           ;       /* 14 Shared RAM SSB Address */
}
tOpenSRB;

/* DLC.Open.SAP SRB Structure                                             */

typedef struct
{
   UINT8    DLCOpenCommandCode       ;       /* 00 Command Code           */
   UINT8    Reserved1                ;       /* 01 RESERVED               */
   UINT8    DLCOpenReturnCode        ;       /* 02 Return Code            */
   UINT8    Reserved2                ;       /* 03 RESERVED               */
   UINT16   DLCOpenStationID         ;       /* 04 SAP  Station ID        */
   UINT8    DLCOpenTimerT1           ;       /* 06 DLC Tmr T1, Resp Timer */
   UINT8    DLCOpenTimerT2           ;       /* 07 DLC Tmr T2, Ackn Timer */
   UINT8    DLCOpenTimerTi           ;       /* 08 DLC Tmr Ti, Inac Timer */
   UINT8    DLCOpenMaxOut            ;       /* 09 Max Xmits W/o A Rx ACK */
   UINT8    DLCOpenMaxIn             ;       /* 10 Max Rxs W/o a Xmit ACK */
   UINT8    DLCOpenMaxOutIncr        ;       /* 11 Dyn Window Inc Value   */
   UINT8    DLCOpenMaxRetryCount     ;       /* 12 Max Retry Cnt (N2 Val) */
   UINT8    Reserved3                ;       /* 13 Max Num of SAPs for Gp */
   UINT8    DLCOpenMaxIField      [2];       /* 14                        */
   UINT8    DLCOpenSAP               ;       /* 16 SAP Value To Be Assign */
   UINT8    DLCOpenSAPOptions        ;       /* 17 SAP Options            */
   UINT8    DLCOpenStationCount      ;       /* 18 Num of Link Stat 2 Rst */
   UINT8    Reserved4                ;       /* 19 Num of Ent in GSAP Lst */
}
tDLCOpenSAPSRB;

/* RCB -- Receive Buffer Format For ARB 81h -- Recieve Data               */

typedef struct
{
   UINT16   RCBNextBuffer;                   /* 00 Next Buffer @          */
   UINT8    Reserved2;                       /* 02 RESERVED               */
   UINT8    RCBFrameStatus;                  /* 03 Rx Frame Status (FS)   */
   UINT16   RCBBufferLength;                 /* 04 Buffer Length          */
   UINT8    RCBFrameData;                    /* 06 Frame Data             */
}
tRCB;

/* System Request Block/ System Status Block Structure                    */

typedef struct
{
   UINT8    SRBCommand;                      /* 00 Command                */
   UINT8    SRBCMDCorrelate;                 /* 01 CMD.Correlate          */
   UINT8    SRBReturnCode;                   /* 02 Return Code            */
   UINT8    Reserved;                        /* 03 Reserved               */
   UINT8    SRBServiceAccessPoint;           /* 04 Serv Acc Point (SAP)   */
   UINT8    SRBLinkStation;                  /* 05 Link Station    (LS)   */
   UINT32   SRBFunctionalAddress;            /* 06 DIR.Set.Func.Address   */
}
tSRB;

/* Token-Ring MMIO Port Structure                                         */

typedef struct
{
   UINT8    ReadMMIO;                        /* 00 Rd BIOS/MMIO Swtchs    */
   UINT8    AdapterReset;                    /* 01 Adapter Reset          */
   UINT8    ReleaseAdapterReset;             /* 02 Release Adapter Rst    */
   UINT8    ResetIRQ;                        /* 03 Reset IRQ (Hog)        */
}
tMIOPortStructure;

typedef struct
{
   UINT8    TxAccessControl          ;       /* 00 Physical Control Field */
   UINT8    TxFrameControl           ;       /* 01 Physical Control       */
   UINT8    TxDestNodeAddress     [6];       /* 02 Destination Address    */
   UINT8    TxSourceNodeAddress   [6];       /* 08 Source Node Address    */
   UINT8    TxDSAP                   ;       /* 14 Destination SAP        */
   UINT8    TxSSAP                   ;       /* 15 Source      SAP        */
   UINT8    TxControlByte            ;       /* 16 Control Byte 01        */
   UINT8    TxData                   ;       /* 17 Frame Data Field       */
}
tTransmitBufferStructure;






#ifdef BROUTER

/* Bridge SRB Response structure                                          */

typedef struct
{
   UINT8    BSRBCommand              ;       /* SRB command.              */
   UINT8    Reserved1                ;       /* Reserved.                 */
   UINT8    BSRBReturnCode           ;       /* Return code.              */
   UINT8    Reserved2             [5];       /* Reserved.                 */
   UINT16   BSRBTxOffset             ;       /* Offset to bridge Tx ctrl. */
   UINT16   BSRBSRBAddress           ;       /* Offset to new SRB.        */
}
tBridgeSRB;

/* Bridge Transmit Control Area                                           */

typedef struct
{
   UINT8    Reserved1             [2];       /* Reserved.                 */
   UINT8    BTCAInputCount           ;       /* Buffers in use by PC.     */
   UINT8    BTCAOutputCount          ;       /* Buffers Tx'd by adapter.  */
   UINT8    BTCAReturnCount          ;       /* Buffers returned to PC.   */
   UINT8    Reserved2                ;       /* Reserved.                 */
   UINT16   BTCAMaxBuffers           ;       /* Total bridge Tx Buffers.  */
   UINT16   BTCANextBuffer           ;       /* Next Available Buffer.    */
   UINT16   BTCAOldBuffer            ;       /* Next Buffer to transmit.  */
   UINT8    Reserved3             [4];       /* Reserved.                 */
}
tBridgeTCA;

/* Bridge Transmit Buffer                                                 */

typedef struct
{
   UINT16   BTBFrameLength;                  /* Length of frame.          */
   UINT16   BTBBufferPointer;                /* Offset to next buffer.    */
   UINT8    BTBXmitControl;                  /* Control bits.             */
   UINT8    BTBStripFS;                      /* Res (FS byte on compl).   */
   UINT16   BTBBufferLength;                 /* Len of data in this buff. */
}
tBridgeTransmitBuffer;

#endif

/* InterruptVectorTable -- Interrupt Vector Table                         */

typedef struct
{
   void     (* routine)();
   UINT16   mask;
   UINT8    pageNotProvided;
   UINT8    pageValue;
   void     *baseAddress;
}
tINTVector;

/**************************************************************************\
**
**    HSM Structures
**
\**************************************************************************/

/* Start of the Driver Virtual Adapter structure for Token-Ring           */

typedef struct _DRIVER_DATA_
{
   UINT8          ARBSaveArea           [ARB_SIZE];
   UINT32         functionalAddress;
   struct _TCB_   *SendQueueHead;
   struct _TCB_   *SendQueueTail;
   UINT32         txStartTime;   
   struct _TCB_   *txInProcessHead;
   void           *FirstRxBuffer;
   void           *CompletionQHead;
   UINT32         CheckAlertTimer          ;
   UINT32         TotalBytes               ;
   UINT8          TxCorrelator             ;
   UINT8          TxBuffersUsed            ;
   UINT8          pageSize8KFlag;
   MEON_STRING    *pageSizeMSG;
   MEON_STRING    *sendMSG;
   MEON_STRING    *LastErrorMessage;

   struct _TCB_   *tcbInProcess;
   UINT32         busType;
   void            *busTag;

   UINT32      pageSize;
   UINT8       pagingMask;
   UINT8       pageSizeMask;

   UINT8       startSendFlag;
   UINT8       SRAFlag;
   UINT8       MLIDStatusFlag;
   UINT32      inDriverReset;
   UINT32      OpeningAdapter;
   UINT8       initRetryCounter;
   UINT8       initStatus;
   UINT32      boardNumber;
   UINT32      interruptResetLevel;
   void        *absoluteMMIOAddress;
   void        *sharedRAMRelative;

   UINT8          adapterParmsPageValue;
   void           *adapterParmsAddr;
   UINT32         txLastBuffer             ;
   UINT32         txBufferSpace            ;
   void           *txCurrentBuffer         ;
   struct _TCB_   *txCurrentTCB            ;
   UINT32         txFragmentCount          ;

   UINT32      brouterState             ;
   UINT8       bConfigCommand        [6];
   UINT8       bParmsCommand         [6];

   UINT16      bParmsSRing              ;
   UINT16      bParmsTRing              ;
   UINT16      bParmsBNumber            ;
   UINT8       bParmsPBits              ;
   UINT8       bParmsCopySTE         [2];

   UINT8       configFastPath       [12];

   tDIROpenAdapter         DIROA     ;

   tINTVector        ivt_AER;
   tINTVector        ivt_ACK;
   tINTVector        ivt_ASB;
   tINTVector        ivt_SRB;
   tINTVector        ivt_FTX;
   tINTVector        ivt_ARB;
   tINTVector        ivt_SSB;
   tINTVector        ivt_RET;

   UINT8             commonNodeAddress [6];
   UINT16            commonIOPort;
   UINT16            commonLineSpeed;
   void              *commonMemoryDecode0;
   void              *commonLinearMemory0;
   UINT32            commonMaximumSize;

   MLID_AES_ECB      DAES;

   MLID_StatsTable   StatsTable;
   StatTableEntry    TotalTxPacketTable;
   StatTableEntry    TotalRxPacketTable;
   StatTableEntry    NoECBAvailableTable;
   StatTableEntry    PacketTxTooBigTable;
   StatTableEntry    PacketTxTooSmallTable;
   StatTableEntry    PacketRxOverflowTable;
   StatTableEntry    PacketRxTooBigTable;
   StatTableEntry    PacketRxTooSmallTable;
   StatTableEntry    PacketTxMiscErrorTable;
   StatTableEntry    PacketRxMiscErrorTable;
   StatTableEntry    RetryTxTable;
   StatTableEntry    ChecksumErrorTable;
   StatTableEntry    HardwareRxMismatchTable;
   StatTableEntry    TotalTxOKByteTable;
   StatTableEntry    TotalRxOKByteTable;
   StatTableEntry    TotalGroupAddrTxTable;
   StatTableEntry    TotalGroupAddrRxTable;
   StatTableEntry    AdapterResetTable;
   StatTableEntry    AdapterOprTimeStampTable;
   StatTableEntry    QDepthTable;

   StatTableEntry    ACErrorTable;
   StatTableEntry    AbortDelimiterTable;
   StatTableEntry    BurtErrorTable;
   StatTableEntry    FrameCopiedErrorTable;
   StatTableEntry    FrequencyErrorTable;
   StatTableEntry    InternalErrorTable;
   StatTableEntry    LastRingStatusTable;
   StatTableEntry    LineErrorTable;
   StatTableEntry    LostFrameTable;
   StatTableEntry    TokenErrorTable;
   StatTableEntry    UpstreamNodeAddressTable;
   StatTableEntry    LastRingIDTable;
   StatTableEntry    LastBeaconTypeTable;

   StatTableEntry    BadCorrelatorTable;
   StatTableEntry    UnknownARBTable;
   StatTableEntry    QDepthEqualTwoTable;
   StatTableEntry    CardIsDeadTable;
   StatTableEntry    TxFreeCountZeroTable;
   StatTableEntry    TxFreeCountZeroAndResetTable;

   UINT32            TotalTxPacketCount;
   UINT32            TotalRxPacketCount;
   UINT32            NoECBAvailableCount;
   UINT32            PacketTxTooBigCount;
   UINT32            PacketTxTooSmallCount;
   UINT32            PacketRxOverflowCount;
   UINT32            PacketRxTooBigCount;
   UINT32            PacketRxTooSmallCount;
   UINT32            PacketTxMiscErrorCount;
   UINT32            PacketRxMiscErrorCount;
   UINT32            RetryTxCount;
   UINT32            ChecksumErrorCount;
   UINT32            HardwareRxMismatchCount;
   UINT64            TotalTxOKByteCount;
   UINT64            TotalRxOKByteCount;
   UINT32            TotalGroupAddrTxCount;
   UINT32            TotalGroupAddrRxCount;
   UINT32            AdapterResetCount;
   UINT32            AdapterOprTimeStamp;
   UINT32            QDepth;

   UINT32            ACError;
   UINT32            AbortDelimiter;
   UINT32            BurstError;
   UINT32            FrameCopiedError;
   UINT32            FrequencyError;
   UINT32            InternalError;
   UINT32            LastRingStatus;
   UINT32            LineError;
   UINT32            LostFrame;
   UINT32            TokenError;
   UINT64            UpstreamNodeAddress;
   UINT32            LastRingID;
   UINT32            LastBeaconType;

   UINT32            BadCorrelator;
   UINT32            UnknownARB;
   UINT32            QDepthEqualTwo;
   UINT32            CardIsDead;
   UINT32            TxFreeCountZero;
   UINT32            TxFreeCountZeroAndReset;
}                     
DRIVER_DATA;         

#include <tokentsm.h>

/********************************************0******************************\
**
**    HSM Specific declarations
**
\**************************************************************************/

void     CFixUpStatStrings (
            DRIVER_DATA       *driverData);

ODISTAT   DriverInit (
   struct _MODULE_HANDLE_  *ModuleHandle,
   SCREEN_HANDLE            *ScreenHandle,
   MEON                     *CommandLine,
   MEON                     *ModuleLoadPath,
   UINT32                  UnitializedDataLength,
   void                     *CustomDataFileHandle,
   UINT32                  (* FileRead)(
                              void *FileHandle,
                              UINT32 FileOffset,
                              void *FileBuffer,
                              UINT32 FileSize),
   UINT32                  CustomDataOffset,
   UINT32                  CustomDataSize,
   UINT32                  NumMsgs,
   MEON                     **Msgs);

ODISTAT  DriverReset (
            DRIVER_DATA       *driverData,
            CONFIG_TABLE      *configTable,
            OPERATION_SCOPE   operationScope);

ODISTAT   DriverManagement (
            DRIVER_DATA   *driverData,
            CONFIG_TABLE   *configTable,
            ECB         *ecb);

ODISTAT   DriverMulticastChange (
      DRIVER_DATA      *driverData,
      CONFIG_TABLE   *configTable,
      GROUP_ADDR_LIST_NODE *mcTable,
      UINT32         numEntries,
      UINT32         functionalTable);

ODISTAT  DriverShutdown (
            DRIVER_DATA       *driverData,
            MLID_ConfigTable  *configTable,
            UINT32            shutDownType,
            OPERATION_SCOPE   operationScope);

void     DriverSend (
            DRIVER_DATA       *driverData,
            MLID_ConfigTable  *configTable,
            struct _TCB_      *tcb,
            UINT32            pktSize,
            void         *physTcb);

void     DriverSendFastPath (
            DRIVER_DATA       *driverData,
            MLID_ConfigTable  *configTable,
            struct _TCB_      *tcb,
            UINT32            pktSize,
            struct _TCB_      *physTcb);

void     DriverSendBridge(
            DRIVER_DATA       *driverData,
            MLID_ConfigTable  *configTable,
            struct _TCB_      *tcb,
            UINT32            pktSize,
            struct _TCB_      *physTcb);

UINT32   WaitForEvent (
            DRIVER_DATA       *driverData,
            void         *busTag,
            UINT32            waitTicks,
            UINT16            memMask,
            UINT16            *memAddress,
            void              *smemAddress);

void      DriverISR(
            DRIVER_DATA         *driverData);

void     DriverCallBack(
            DRIVER_DATA         *driverData,
            CONFIG_TABLE      *ConfigTable);

BOOLEAN  DriverDisableInterrupt(
            DRIVER_DATA         *driverData,
            BOOLEAN            switchVal);

void      DriverEnableInterrupt(
            DRIVER_DATA         *driverData);

void   IV_AdapterCheck   (void *MMIOBase, void *SRAMBase, DRIVER_DATA *driverData);
void   IV_AdapterError   (void *MMIOBase, void *SRAMBase, DRIVER_DATA *driverData);
void   IV_ARBRequest     (void *MMIOBase, void *SRAMBase, DRIVER_DATA *driverData);
void   IV_ARBReturn      (void *MMIOBase, void *SRAMBase, DRIVER_DATA *driverData);
void   IV_FastTxComplete (void *MMIOBase, void *SRAMBase, DRIVER_DATA *driverData);
void   IV_InvalidASB     (void *MMIOBase, void *SRAMBase, DRIVER_DATA *driverData);
void   IV_SRBResponse    (void *MMIOBase, void *SRAMBase, DRIVER_DATA *driverData);
void   IV_SSBResponse    (void *MMIOBase, void *SRAMBase, DRIVER_DATA *driverData);

#ifdef BROUTER
void  ARB_JMP_BReceiveDataRoutine (void *MMIOBase, DRIVER_DATA *driverData);
#endif /* BROUTER */

void  ARB_JMP_ReceiveDataRoutine (void *MMIOBase, DRIVER_DATA *driverData);
void  ARB_JMP_TransmitDataRequest (void *MMIOBase, DRIVER_DATA *driverData);
void  ARB_JMP_InvalidARBEntry (void *MMIOBase, DRIVER_DATA *driverData);
void  ARB_JMP_RingStatusRoutine (void *MMIOBase, DRIVER_DATA *driverData);

void  ARB_JMP_SUB_ReturnASBResponse (void *MMIOBase, DRIVER_DATA *driverData);

void   DIROpenAdapterError (void *MMIOBase, DRIVER_DATA *driverData, void *SRB, UINT8 errorCode);
void   UpdateAlertStats (void *MMIOBase, DRIVER_DATA *driverData);
void   CheckNextSRBCommand (void *MMIOBase, DRIVER_DATA *driverData);

void  MoveDataToPagedBuffers (void *dest, void *source, UINT32 length, DRIVER_DATA *driverData);
void   CheckForAnotherSend (DRIVER_DATA *driverData);
void   CheckFunctionalAddressFlag (void *SRBBase, void *MMIO, DRIVER_DATA *driverData, UINT8 ramPage);

/**************************************************************************\
**
**    OS Specific, non-portable declarations
**
\**************************************************************************/

void EnterDebugger(void);

#define DRIVER_H
#endif /* DRIVER_H */