AXPpci 33 : Information for developers ================================================= This information is provided in good faith but no guarantee is made as to its accuracy. This information should be read in conjunction with information contained in the 'Digital AXPpci 33 Alpha PC Motherboard Design Guide' MEMORY ------- The Digital AXPpci 33 system provides for up to 256 Mbyte of 70 nS DRAM and 512 Kbyte of FlashROM. Four industry standard 72-pin SIMM sockets allow DRAM memory to be added to the Main Logic Board. Memory must be added as pairs of SIMMs, to make two banks of two SIMMs each. Several SIMM sizes are supported allowing memory configurations from 8 Mbyte to 256 Mbyte. If SIMMs of different sizes are used together, there is no restriction on physical ordering of the SIMM pairs. The larger SIMMs must be initialized by power-on code to occupy the lower addresses, since the base address of each bank is required to be naturally aligned with its size. The SIMMs supported are of two kinds, ones having a single RAS line and ones having two RAS lines. The SIMMs with two RAS lines are addressed as two separate memories and require that the Split Bank Enable bit be set in the appropriate Bank Configuration Register (BCR). The number of address lines used varies according to the size of the SIMM. The Row Address Select field of the Bank Configuration Register (BCR) and the Bank Mask Register must be loaded with the appropriate value for each bank. Table 3-1 Possible Memory Capacities Organization SIMM Bank BCR BCR BMR size size ---------------------------------------------------------------- 1 Mbit x 36 4 Mbyte 8 Mbyte 0 0011b 0070.0000 2 Mbit x 36 8 Mbyte 16 Mbyte 1 0011b 00F0.0000 4 Mbit x 36 16 Mbyte 32 Mbyte 0 0111b 01F0.0000 8 Mbit x 36 32 Mbyte 64 Mbyte 1 0111b 03F0.0000 16 Mbit x 36 64 Mbyte 128 Mbyte 0 1111b 07F0.0000 ---------------------------------------------------------------- Memory Setup ------------ The Memory Controller has one control register that effects all banks of memory and two error/status registers used for reporting any errors. Each memory bank has associated with it its own set of three Setup Registers. For the Digital AXPpci 33 System, only Banks [1:0] are used for selection of DRAM memory; Bank [3] is used to select FlashROM. Memory timing is determined by the values in the Global Timing Register (GTR) and the four Bank Timing Registers (BTR[3:0]). Addressing of each bank is set up in the four Bank Configuration Registers (BCR[3:0]) and the four Bank Mask Registers (BMR[3:0]). Global Timing Register (GTR) ---------------------------- Address GTR 1 2000.0060 read/write This register selects certain timing parameters common to all banks of memory. Table 3-2 GTR Register Bits Name Description ----------------------------------------------------------- 4:0 RAS/CAS precharge The number of cycles to precharge RAS and CAS at the end of a memory cycle. A new memory cycle cannot begin until the precharge time has passed. The number of cycles is this value plus one. RAS/CAS precharge is set by the DRAM vendors. 9:5 Minimum RAS The number of cycles that RAS is assertion time asserted during a memory Refresh cycle. The number of cycles is this value plus one. The minimum time that RAS should be asserted during a Refresh operation (CAS before RAS Refresh) is the same as the minimum RAS assertion time during a normal read cycle - 70 nS. 17:10 Maximum RAS Maximum number of cycles (pre- assertion time scaled by 128) that RAS may remain asserted. This feature allows faster accesses to addresses within the same memory page that are split over several memory accesses. The number of cycles is the value in this field. The Maximum RAS assertion time is subject to experimentation. 18 Refresh Enable Enables Refresh for all banks when set. Cleared by Power-on Reset. This bit should be set for any memory bank populated with SIMMs. Bank [3], with its non- volatile memories, does not require refresh. 26:19 Refresh Interval The number of cycles (pre-scaled by 64 or 512 as set by bit<27>) between requests to start a Refresh cycle. The number of cycles is the value in this field. The SIMMs used for memory on Digital AXPpci 33 require either 1024 refresh cycles every 16 milliseconds or 2048 refreshes every 32 milliseconds. Either case requires a refresh at least every 15.6 microseconds. To allow some margin, refresh should be done approximately every 12.5 - 13 sec. 27 Refresh Divide Sets the pre-scalar for Refresh Select Interval (see above). 0 = divided by 64; 1 = divide by 512. A value of 0 is recommended. 31:28 CAS/RAS Setup The number of cycles between the assertion of CAS and the assertion of RAS for Refresh cycles. The number of cycles is this value plus two. CAS to RAS setup is specified as 10 nS for the SIMMs used; this field should be set to 0000b. 63:32 RESERVED IGN on Write; UNPREDICTABLE on Read. Bank Timing Registers (BTR[0:3]) Addresses BTR0 1 2000.0040 read/write BTR1 1 2000.0048 read/write BTR2 1 2000.0050 read/write BTR3 1 2000.0058 read/write Each memory bank has its own Timing Register used to set those timing parameters that are specific to a particular SIMM pair. All bits in this register are Read/Write and are UNDEFINED following power-on reset. Banks [2:0] will be programmed the same, Bank [3] will be programmed differently as it accesses the FlashROM’s. Table 3-3 BTR<3:0> Register Bits Name Description ------------------------------------------------------------- 3:0 Row Address The number of cycles from Setup that the RAS address is valid on the memory address bus to the assertion of RAS. The number of cycles is this value plus one. 7:4 Row Address The number of cycles from Hold RAS assertion to the memory address changing to the CAS value. The number of cycles is this value plus one. 11:8 Column The number of cycles from Address Setup the CAS address (and write data during write cycles) being valid to the assertion of CAS. The number of cycles is this value. 16:12 CAS The number of cycles for which CAS is Assertion asserted. The number of cycles is this Time value plus one. 20:17 CAS The number of cycles that CAS is de- Pre-charge asserted between active phases during Page Mode cycles. The number of cycles is this value plus one. 23:21 Tri-state The number of cycles required to put the memory into the high-impedance state when switching from READ to WRITE. The number of cycles is this value plus one. 24 Data Setup Data setup time prior to assertion of CAS on writes. The number of cycles is this value plus one. 63:25 RESERVED UNPREDICTABLE on Read, ignored on Write -------------------------------------------------------------- Bank Configuration Registers (BCR[0:3]) Addresses BCR0 1 2000.0000 write only BCR0 1 2000.0008 write only BCR0 1 2000.0010 write only BCR0 1 2000.0018 write only Each memory bank has its own Configuration Register that sets the Bank Base Address, certain DRAM device specific parameters and some operating modes. Table 3-4 BCR<3:0> Register Bit Name Description ------------------------------------------------------------ 5:0 RESERVED Ignored on Write 9:6 Row These bits are set as a function Select of Address the SIMM type installed in the particular bank. They select which address bits become the RAS address and which the CAS address. 0011b - ten bits for row and column addresses 0111b - eleven bits for row and column addresses 1111b - twelve bits for row and column addresses 10 Error If set, ECC is checked for each access to Mode this bank. If cleared, no checking is performed. 11 Write This bit selects a mode of operation not Mode used for Digital AXPpci 33. It MUST be cleared. 12 Byte This bit selects a mode of Enable operation Write not used for Digital AXPpci 33. It MUST be cleared. 13 Split This bit controls RAS assertion Enable to Bank SIMM banks that have two RAS lines - RASA and RASB. This bit should be set Valid when the Base Address Register has been loaded for a particular memory bank. The Bank Mask Register should be loaded first. It is cleared by Power-on Reset. 19:15 RESERVED Ignored on Write. 28:20 Bank This specifies the start address of this Base bank. Banks are assumed to be a minimum size of 1 Mbyte. Start addresses MUST be aligned with the size of the bank, i.e., for a bank of size 2^n bytes, the least significant (20- n) bits of this field must be ZERO. 63:29 RESERVED Ignored on Write. -------------------------------------------------------------- Bank Address Mask Registers (BMR[0:3]) Addresses BMR0 1 2000.0020 write only BMR0 1 2000.0028 write only BMR0 1 2000.0030 write only BMR0 1 2000.0038 write only Each memory bank has its own Address Mask Register used for specifying the bank size. Possible bank sizes for the Digital AXPpci 33 are 8, 16, 32, 64 and 128 Mbyte. These registers are WRITE ONLY. A bank is selected when physical address bits <28:20> match the Bank Base Address bits masked by the Bank Base Address Mask. Table 3-5 BMR<3:0> Register Bits Name Description ------------------------------------------------------------ 19:0 RESERVED Ignored on write. 28:20 Bank Address This field specifies the mask to be used Mask when comparing the requested address with the Bank Base Address Registers. A "1" in any position means do not check the corresponding address bit. These bits correspond to physical address bits <28:20> 63:29 RESERVED Ignored on write. Memory Sizing And Bank Initialization ------------------------------------- To size the SIMMs in a particular bank, and thus setup the control registers correctly for that bank, memory test code should perform the following operations. Start at Bank [0], initially setting the Row Address Field to 12+12 (BCR<9:6> = 1111b) and clearing the Split Bank Enable bit, i.e., setup for the maximum SIMM size; a 128 Mbyte bank comprising two SIMMs each of 64 Mbyte. The Base Address should be set to some multiple of the Bank Size (BCR<28:20> = xx0000000b). The Mask Register for that Bank should be set accordingly (BMR<28:20> = 001111111b). Writing and reading the entire assumed SIMM address space will allow the real SIMM size to be determined; the correct values may then be loaded into the control registers for that bank. This procedure should then be repeated for Bank [1]. FlashROM Memory --------------- This memory is normally used as Read-only storage for the system firmware, which is copied to read-write memory (DRAM) for execution. A feature of the "Flash" ROM is that under certain conditions it may be written or totally erased. The FlashROM memory is accessed via an address space that is defined (by the CPU chip) as non-cacheable. This address space starts at address 0 3800.0000. The FlashROM memory is byte wide, bytes are accessed at sequential quadword addresses, i.e., only bits<7:0> of data on a read or a write have significance. When writing the FlashROM memory there are very specific timing requirements that are met by program delays. Details . There are two FlashROM devices on the Digital AXPpci 33 system module, each of 256 Kbyte, all with the bytes aligned on quadword (8 byte) addresses. Their address ranges are thus: Table 3-6 FlashROM Memory Space 0 3800.0000 - 0 381F.FFF8 First device RESERVED 0 3820.0000 - 0 383F.FFF8 Second device RESERVED 0 3840.0000 - 0 385F.FFF8 Third device 0 3860.0000 - 0 387F.FFF8 Fourth device The original architecture contained four FlashROM devices, two were subsequently remove but are left as reserved memory space. Byte 0 of FlashROM 0 is accessed at location 0 3800.0000h; byte 1 at 0 3800.0008h etc. The FlashROM devices are can be written to by setting the Program Enable bit on the 8242 keyboard Controller chip. Details . LED’s ----- This module has provision for eight off-board Light-Emitting Diodes (LED’s) for general use by software. See individual operating system and firmware documentation for the meaning of specific values. The pattern displayed at power-on is undefined. The LED’s are available via a 16 pin header and a suitable cable and daughter card. Bank [3] of memory is set up for two-RAS operation, and the second RAS line is used to access the LED’s. The first RAS line accesses the FlashROM’s. The LED’s display the pattern of the low byte during a write to any CPU address in the range 0 3880.0000 through 0 38FF.FFFF. Address 0 3880.0000 is recommended for consistency and to allow for future expansion. Cache ----- The Digital AXPpci 33 secondary cache has a capacity of 0 Kbytes, 256 Kbytes or 1 Mbyte. The cache is controlled by a single register contained within the CPU. Note that the cache is not directly accessible through any special address ranges or diagnostic access modes. Cache Register (CAR) Address CAR 1 2000 0078 read/write The Cache Register controls the function and timing of the secondary cache. Table 3-7 CAR Register Bits Name R/W Description ------------------------------------------------------------ 0 Cache R/W When set, enables the secondary cache. Enable This bit is set by power-on reset. 1 RESERVED R/W UNPREDICTABLE on Read, Writes ignored 2 Enable R/W When set, parity checking on the TAG TAG value is enabled. 3 Write R/W When set, this bit forces Parity Wrong writing of incorrect parity to the TAG. 4 ECC R/W When set, this bit enables ECC checking enable and correction for the secondary cache data store. 7:5 Cache R/W Must be set to 010b to indicate 256 Size Kbytes of secondary cache. 10:8 Read R/W Set according to the speed of the cache Cycle SRAM’s. The actual Read Access time, in CPU cycles, is three more than the value in this field. 13:11 Write R/W Set according to the speed of the cache Cycle SRAM’s. Specifies the number of cycles for which Write Enable is asserted. The actual Write Access time, in CPU cycles, is one more than the value in this field. 14 Write R/W Specifies the number of cycles for Hold which write data is held valid after Write Enable is de-asserted. BC_WE_L is asserted for one more CPU cycle than this value. 15 RESERVED R/W UNPREDICTABLE on Read, Ignored on Write 30:16 TAG RO Contains the TAG value (Parity; Dirty; TAG<7:0>; IDX_TAG<4:0>) latched during the most recent read. 31 Cache RO Reflects the state of the TAG compare HIT for the most recent access to the cache. reading a ONE, indicates that the most recent access was a HIT. -------------------------------------------------------------