AXPpci 33 : Information for developers ================================================= This information is provided in good faith but no guarantee is made as to its accuracy. This information should be read in conjunction with information contained in the 'Digital AXPpci 33 Alpha PC Motherboard Design Guide' INTERRUPTS ---------- Interrupts from the various I/O components of the system connect to the interrupt controller section of the PCI ISA Bus Bridge chip. Some are hard wired to specific Interrupt Levels, some of the PCI Interrupts may be programmed to connect to specific Interrupt Levels (Note "levels" here is in the context of the bridge chip - not the CPU) The CPU has three interrupts - all interrupt handling is performed in PALcode - refer to the CPU and/or PALcode Specification for more details. These three are assigned as follows. · IRQ[2] - Periodic interval timer interrupt from TOY chip · IRQ[1] - Device interrupt from PCI and ISA logic · IRQ[0] - Attention interrupt from NMI, HALTREQ, and KBRST The action taken for each of these interrupts will be determined by PALcode. See the Digital AXPpci 33 Firmware Specification for details. Interval Timer Interrupt ------------------------ The Time of Year chip can be programmed to generate a periodic interrupt, which is connected directly to the CPU's IRQ[2] interrupt input to allow more precise control of software events. HALTREQ ------- The HALTREQ signal may be asserted when the front panel HALT button is pressed. The function of this button is controlled by Jumper J8; it can generate a HALTREQ interrupt or a CPU Reset signal. The HALTREQ signal is logically combined with NMI and KBRST before connecting to IRQ[0] on the CPU. Table 5-1 HALT/Reset Jumper Settings Jumper Function 1-2 CPU Reset 2-3 Halt Request Interrupt 2-4 Disabled NMI --- The PCI-ISA bridge chip generates this "non-maskable interrupt" when either SERR or IOCHK is asserted. The NMI signal is logically combined with HALTREQ and KBRST before connecting to IRQ[0] on the CPU. · SERR - an address parity error has been detected on the PCI bus by the Bridge Chip. The Bridge Chip takes no action other than reporting the error. · IOCHK - a parity error has been detected on a memory module plugged into the ISA bus. KBRST ----- The keyboard reset signal (KBRST) can be generated by the 8242 Keyboard Controller chip under software control. This line is connected to the P20 pin, and is sometimes called SRESET. Device Interrupts ----------------- All PCI interrupts are routed to the ISA interrupt controller, and the resulting INT signal is brought to the IRQ[1] input of the CPU. Devices should power-on without generating interrupts, and should not issue any interrupts until specifically enabled by software, after interrupt handlers are in place. This is especially important for PCI add-in cards, whose functions are not known until after the devices are configured. PCI Interrupts -------------- The PCI ISA Bridge Chip allows for 4 PCI based interrupts to be channeled into 4 channels of the ISA Interrupt controller. The following table identifies how the PCI interrupts are routed to the PCI ISA Bridge. Each PCI ISA Bridge channel has a ‘wire OR’ gate to combined the multiple PCI sources. The 4 channel to the ISA Interrupt controller are programmable. Table 5-2 PCI Interrupt routing PCI ISA Bridge PCI channel Source ---------------------------------- PIRQ0 PCI Slot 1 Int A PCI Slot 2 Int B PCI Slot 3 Int C PCI Slot 1 Int D PIRQ1 PCI Slot 2 Int A PCI Slot 3 Int B PCI Slot 1 Int C PCI Slot 2 Int D PIRQ2 PCI Slot 3 Int A PCI Slot 1 Int B PCI Slot 2 Int C PCI Slot 3 Int D PIRQ3 SCSI Controller --------------------------------- ISA Interrupts -------------- The PCI-ISA Bridge Chip allows for 16 Interrupt inputs, not all of which are external. Two separate interrupt controllers are connected together, with IRQ2 used to cascade the second controller. Their priority, from highest to lowest, is 0-1, 8-15, 3-7. These interrupts are assigned as described in the table below, which indicates the various interrupt lines with all possible (P) sources, and with the standard (S) or the hard-wired (H) use. Table 5-3 ISA Interrupt Sources 0 0 0 0 0 0 0 0 0 0 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 Timer/co H . . . . . . . . . . . . . . . unter Keyboard . S . . . . . . . . . . . . . . Com A . . . S . . . . . . . . . . . . Com B . . . . S . . . . . . . . . . . Floppy . . . . . . S . . . . . . . . . Parallel . . . . . . S . . . . . . . . Mouse . . . . . . . . . . . . S . . . IDE . . . . . . . . . . . . . . S . ISA 1 . . . . . P . . . P P . . . P P ISA 2 . . . . . P . . . P P . . . P P ISA 3 . . . . . P . . . P P . . . P P ISA 4 . . . . . P . . . P P . . . P P ISA 5 . . . . . P . . . P P . . . P P PIRQ0 . . . . . P . . . P P . . . P P PIRQ1 . . . . . P . . . P P . . . P P PIRQ2 . . . . . P . . . P P . . . P P SCSI . . . . . . . . . . . S . . . . There are several interrupt lines that are dedicated for specific uses. Additionally, three IRQ lines are unavailable due to hardware restrictions; IRQ2 is used to cascade the two DMA controllers in the PCI-ISA bridge chip, and IRQ8 and IRQ13. IRQ8 is ordinarily used for an interval timer interrupt, but is unconnected in the Digital AXPpci 33 system; the interval timer interrupt is tied directly to the CPU instead. IRQ13 is ordinarily used for a co-processor error, or to signal the end of a DMA scatter-gather operation in the bridge chip. This features are not used in the Digital AXPpci 33 system, and this interrupt line is not connected. IRQs 5, 9, 10 and-15 can be driven by ISA and/or PCI slots. When the IDE function is not used(i.e in the SRM console) IRQ14 is also available. Care must be taken to avoid conflicts with interrupt lines used by the system's base logic and other options. CPU Recognition Of Interrupts ----------------------------- CPU Interrupts on lines IRQ[2:0] cause entry to PALcode. The interrupt dispatcher must do something along these lines. IRQ[0] Interrupts ----------------- The IRQ[0] interrupt line is driven by any of NMI, HALTREQ and KBRST. The NMISC register in the PCI-ISA bridge chip can be used to determine whether the NMI interrupt was set. Check for either or both of the SERR and IOCHK bits asserted and enabled. If the NMI is not asserted, either the HALTREQ or the KBRST lines are asserted. The handling of these signals is identical, so it is not necessary to distinguish between them. IRQ[1] Interrupts ------------------ All device interrupts from the ISA and PCI busses come in through IRQ[1]. To determine the source of the interrupt, read the standard ISA based PIC. When an ISA interrupt has been detected, a PCI INTACK cycle must be generated by the PALcode interrupt dispatcher. This is seen by the PCI ISA Bridge chip and converted by it into two cycles that freeze, then read the normal ISA-style Interrupt Priority Encoders within the Bridge Chip. The Bridge Chip then returns a vector on data bits<7:0>. Refer to the Bridge Chip Specification for full details. Note that this INTACK cycle does not remove the source of the interrupt, specific code that accesses the device that interrupted must do this. The bridge chip releases its interrupt when an end-of-interrupt (EOI) command is issued by the interrupt dispatcher. This is a co-operative activity performed by some combination of PALcode and the particular Operating System. IRQ[2] Interrupt ---------------- The Time of Year (TOY) clock chip can be programmed to provide an interrupt output, which is connected to IRQ[2]. See the TOY chip spec for details on how to generate and clear interrupts.