AXPpci 33 : Information for developers - part 4 ================================================= This information is provided in good faith but no guarantee is made as to its accuracy. This information should be read in conjunction with information contained in the 'Digital AXPpci 33 Alpha PC Motherboard Design Guide' CPU --- The CPU is a single Alpha AXP processor. The following parts are supported: Table 2-1 Supported CPU’s Type Clock Cycle Time ----------------------------- 21066A 233 MHz 4.28 nS 21066 166 MHz 6 nS 21068A 100 MHz 10 nS 21068 66 MHz 15 nS ----------------------------- Architecture -------------- The CPU has a fully-pipelined, dual-issue, 64-bit RISC architecture. Its on-chip pipelined floating point unit supports IEEE and Digital formats. 44 translation buffers speed execution of memory management operations. The memory data path is 64 bits wide, with an additional eight bits of error correction code (ECC). There are two on-chip eight- Kbyte caches for instruction and data streams. Clock ------ The clock supplied to the CPU is 33.33 MHz; the CPU has an on-chip VCO/PLL that multiplies this external clock up to the required speed internally. The clock multiplier is set during power-on, while RESET is still low. A three-bit multiplier code is input to the CPU on pins IRQ[2:0]. Provisions are made for many CPU clock frequencies, from 66 to 300 MHz, selected by a set of jumpers (J7). Table 2-2 CPU Clock Frequency Jumper Settings Jumper Jumper Jumper IRQ[2: CPU Notes 1-2 3-4 5-6 0] Clock ---------------------------------------------------- Out Out Out 000 66 21068 Only Out Out In 001 100 21068A Only Out In Out 010 133 RESERVED Out In In 011 166 21066 Only In Out Out 100 200 21066A Only In Out In 101 233 21066A Only In In Out 110 266 RESERVED In In In 111 300 RESERVED ----------------------------------------------------- Serial ROM ---------- Following power-on, the CPU loads it's I-stream internal cache from an external 64 Kbyte ROM, clocking in the data as a serial bit stream. The ROM can hold up to eight programs, only one of which is loaded for any power-on. A set of jumpers at J28 and J29 allows selection of one of the eight data bits as the source of the serial load data. Refer to the Digital AXPpci 33 System Firmware Specification for ROM contents information. Table 2-3 SROM Jumper Settings Jumper Bit Function ----------------------------------------------------- J28 1-3 0 Normal Operation(Default) J28 3-5 1 SROM Mini Console with Bcache enabled J28 2-4 2 SROM Mini Console with Bcache disabled J28 4-6 3 RESERVED J29 1-3 4 Fail-safe Loader J29 3-5 5 RESERVED J29 2-4 6 Normal operation with 12 nS Bcache(Not Officially supported) J29 4-6 7 Fail-safe Loader with 12 nS Bcache(Not Officially supported) --------------------------------------------------------- All I-stream Cache bits are loaded from the 65536 bit serial stream, including both data and control bits; therefore the size of the loaded program is 7136 bytes. Data are loaded, least significant bit first, from LW0 (32 bits), then LW2, LW4, LW6, TAG (21 bits), ASN (six bits), the ASM bit, the V bit, LW1, LW3, LW5, LW7, and lastly BHT (8 bits). Following the I-stream cache load, the same pins that control the serial ROM are used to control a software timed serial I/O port which may be used for diagnostic purposes. This serial EIA port uses a 10-pin header (J32), accessible only when the module is out with an enclosure. It is not accessible, nor is it active, during normal system operation. Note that 12 nS is NOT officially supported. The last two channels of the SROM have timings that have been demonstrated, using simulation only, functional for 12 nS cache parts. Vendors may choose to verify these with real parts at there own risk. Memory Controller ------------------ The CPU has an integral memory controller able to control up to two banks of DRAM, each of up to 128 Mbyte capacity. A fourth bank is used for FlashROM and LED’s. See the Memory Chapter for details. In the Digital AXPpci 33 system, the CPU supports 256 Kbyte of ECC-protected secondary cache SRAM’s. The integral graphics assist of the DECchip 21066/68's memory controller is not used. PCI Interface --------------- The I/O port is the industry-standard Peripheral Component Interconnect (PCI) bus. The CPU chip can be the PCI bus master, generating cycles on the PCI bus or can act as a bridge between the PCI bus and memory. It is able to generate all types of PCI cycles and responds to cycles initiated by devices requiring access to memory. It performs translation of addresses supplied by other PCI devices acting as bus masters.