AXPpci 33 : Information for developers - part 4 ================================================= This information is provided in good faith but no guarantee is made as to its accuracy. This information should be read in conjunction with information contained in the 'Digital AXPpci 33 Alpha PC Motherboard Design Guide' CONTROLLERS ----------- I/O controllers connect either directly to the PCI bus or to the ISA and Utility busses spawned by the PCI-ISA bridge chip. The bridge chip itself has many internal registers accessible from the PCI bus. CPU accesses to the PCI bus may be either to I/O space or to Memory Space. These two spaces are specified by different dedicated address spaces within the CPU's total address space and are separately decoded on the PCI bus from different encodings of the multi-function C/BE lines. PCI Interface ------------- The PCI interface clock speed is fixed at 33.33 MHz, for a 30 nS cycle time. The maximum instantaneous burst data rate is 132 Mbyte/s. Initialization -------------- Following power-on, the 21066/68 chip's PCI interface must be initialized so that each device has a unique address, among other things. Configuration Cycles -------------------- Configuration cycles are generated on the PCI bus when accesses are made to CPU addresses 1 E000.0000 through 1 FFFF.FF80. The corresponding PCI physical address presented in the configuration cycle are 0000.0000 through 00FF.FFFC, due to the five-bit address shift required by the CPU's sparse-space addressing scheme. See the DECchip 21066/68 specification for details. PCI devices on the base system module have hardwired assignments of the PCI physical address bits AD<23:11> (corresponding to CPU address bit A<28:16>) to each device's IDSEL signal, listed below. Table 4-1 PCI Configuration Address Space PCI IDSEL Base Base Bit address address ---------------------------------------------- SCSI AD[17] 0002.0000 1 E020.0000 PCI ISA Bridge AD[18] 0004.0000 1 E040.0000 PCI Bus Slot 1 AD[22] 0040.0000 1 E400.0000 PCI Bus Slot 2 AD[23] 0080.0000 1 E800.0000 PCI Bus Slot 3 AD[19] 0008.0000 1 0008.0000 ---------------------------------------------- The CPU PCI controller is responsible for generating the cycles necessary to configure the PCI bus. These cycles are, not unnaturally, called Configuration Cycles and must be performed after power-on as PCI devices power on with no built-in knowledge of address ranges to which they should respond. The first step in configuration is deciding which devices are connected to the PCI bus. As the devices have no allotted address range at this point, they use a special mechanism for this purpose. Each device on the PCI bus has its own select input (IDSEL), each one of these is connected to a different one of PCI AD lines <23:11>, i.e., a maximum of 13 devices. As part of the configuration sequence, the CPU asserts each one of these address lines in sequence looking for a DEVSEL response. Note that only a single IDSEL may be asserted in the configuration space address. When a device is addressed in this way, the low eight bits of the PCI physical address generated by the CPU select one of 256 possible byte-wide registers within the device. Of these, 64 are pre-defined as a "header" region whose format is fixed for all PCI devices; the remainder are device specific. See the PCI Specification for details on using the configuration space accesses to set up the device's base address, etc. Interrupt Acknowledge Cycles ---------------------------- The CPU generates an INTACK cycle on the PCI bus when CPU address 1 C000.0000 is read. See the chapter on Interrupts for a description of what occurs in an INTACK cycle. Special Cycle ------------- The CPU generates a PCI Special Cycle when CPU address 1 C000.0000 is written. Byte Accesses On PCI Bus ------------------------ The CPU has no addressing modes that permit direct access to bytes or combinations of bytes, other than aligned four-byte entities (longwords) on the PCI bus. An encoding scheme of certain low order address bits is therefore used to allow direct byte, word (two contiguous bytes) and tri-byte (three contiguous bytes) accesses. The Byte Enables are driven out on the four multi-function PCI bus lines CBE[3:0]. For all CPU PCI bus accesses, the two low order address bits [1:0] will be 00b for memory space cycles and will be encoded according to the bytes specified for I/O cycles. The address bit encoding for byte selection is shown below. Table 4-2 PCI Byte Access Translation CPU CPU PCI PCI PCI Transfer ADDR[6:5] ADDR[4:3] CBE[3:0] AD[1:0] AD[1:0] Size Memory I/O ----------------------------------------------------------- 00 00 1110 00 00 Byte 01 00 1101 00 01 Byte 10 00 1011 00 10 Byte 11 00 0111 00 11 Byte 00 01 1100 00 00 Word 01 01 1001 00 01 Word 10 01 0011 00 10 Word 00 10 1000 00 00 Tri-byte 01 10 0001 00 01 Tri-byte 00 11 0000 00 00 Longword 11 11 0000 00 00 Quadword ----------------------------------------------------------- By using some of the low order address bits in this way, it is not possible to generate a full 32-bit PCI address from the CPU address - only 27-bits of CPU supplied address are available for passing to the PCI bus; CPU address bits A<31:5> generate PCI address bits AD<26:0>. A register field within an IOC register - the Host Address Extension (HAE) Register - allows this address to be extended to a full 32- bits. The 128 Mbyte region the CPU is thus able to access is further subdivided so that accesses to the first 16 Mbyte (CPU address bits A<31:30> = 00) ignore the HAE bits - treat them as all zero. Thus the PCI space accessible is a 16 Mbyte region that always starts at PCI physical address 0, referenced when CPU address bits A<31:30> are zero and a 112 Mbyte region whose address is formed by concatenating the CPU supplied 27 bits of address with the five bits of the HAE when CPU address bits A<31:30> are non-zero. Bus Arbitration --------------- The internal arbitration hardware within the SIO (Intel 82378ZB).is used to perform PCI bus arbitration. PCI-ISA Bridge Chip ------------------- The PCI-ISA bridge chip (an Intel 82378ZB System I/O chip, also known as the SIO) connects to the PCI bus but does not obey the normal PCI Configuration rules. On power-on it responds to PCI I/O space addresses in the range 0 to 0000.FFFFh (first 64 Kbytes) and to PCI Memory Space addresses 0 to 00FF.FFFFh (first 16 Mbyte). Some of these addresses are decoded for use within the bridge chip, some for use on the ISA bus. PCI I/O Space ------------- To access this space, use addresses 1 C000.0000 through 1 DFFF.FFFF in the CPU's address space, noting the address rules relating to specification of bytes within a 32-bit longword and the use of the HAE field in the IOCCTRL register. The PCI-ISA bridge chip will respond to the first 64 Kbytes of addresses in this space, some of these addresses will directly reference registers within the bridge chip, some will be decoded "subtractively" and be passed on to potential devices connected to the ISA bus. Note that the 64 Kbyte range refers to PCI bus addresses 0000.0000 through 0000.FFFFh which are generated from CPU addresses 1 C000.0000 through 1 C01F.FFE0h. Table 4-3 PCI I/O Address Space ISA PCI CPU address address address --------------------------- 0000.0000 0000.0000 1 C000.0000 0000.0000 0000.0000 1 C000.0020 : : : 0000.FFFF 0000.FFFF 1 C01F.FFE0 PCI Sparse Memory Space ----------------------- To access this space, use addresses 2 0000.0000 though 2 FFFF.FFFF in the CPU's address space, noting again the rules relating to the specification of bytes within a longword and the use of the HAE register. The PCI-ISA bridge chip will respond to the 16 Mbyte of addresses in this space, again positively decoding some addresses and subtractively decoding others. Addresses beyond 16 Mbyte will not cause any action by the bridge chip. Table 4-4 PCI Memory Address Space ISA PCI CPU address address address --------------------------- 0000.0000 0000.0000 2 0000.0000 0000.0000 0000.0000 2 0000.0020 : : : 00FF.FFFf 00FF.FFFf 1FFF.FFE0 The PCI address lines AD<26:0> are driven by CPU address lines A<31:5> during Memory Access Cycles. PCI Dense Memory Space ---------------------- To access this space, use addresses 3 0000.0000 though 3 FFFF.FFFF in the CPU's address space .Dense Memory Space accesses are always longword accesses. Table 4-5 PCI Memory Address Space PCI CPU address address ------------------------ 0000.0000 3 0000.0000 0000.0004 3 0000.0004 : FFFF.FFFC 3 FFFF.FFFC ------------------------ SCSI ---- Integral to the Digital AXPpci 33 System Module is a fast SCSI-2 controller, using the NCR 53C810 controller chip. This chip connects directly to the on-board PCI bus and supports 8-bit, single-ended SCSI devices running at up to 10 Mbyte/second. The chip off loads the CPU by executing a "Script" of commands, stored in system memory and retrieved by the SCSI controller as required. A connector at the rear of the system enclosure allows for the addition of external devices. A second connector mounted on the system module allows for connection to devices internal to the system enclosure. There may be up to seven peripheral devices, which is the limit of the SCSI bus. Termination The SCSI bus must be terminated at both physical ends. The on-board terminator can be enabled/disabled dependent on the position of J13. Table 4-6 SCSI Jumper Settings Jumper Function -------------------------------------------- In SCSI terminator enabled(Default) Out SCSI terminator disabled -------------------------------------------- SCSI IDs -------- The SCSI controller chip is normally assigned Device ID seven. Other devices have default ID assignments as follows. Table 4-7 Default SCSI ID's ID Device ------------- 0 first hard disk 1 second hard disk 4 CD-ROM 5 tape drive 7 host adapter ISA Interface -------------- The ISA interface created by the System I/O chip allows connection of low-cost, industry-standard peripherals. Serial I/O ----------- Two asynchronous serial lines are provided, both supporting modem control. The maximum speed is 56 kBAUD. These are provided as a part of the functionality of the Super I/O chip which connects to the ISA bus spawned by the PCI-ISA bridge chip. The serial ports are labeled COM1 and COM2 and are accessed via ISA addresses 3F8h through 3FFh and 2F8 through 2FFh. These addresses map into CPU addresses 1 C000.5F00 to 1 C000.5FE0h and 1 C000.7F00 to 1 C000.7FE0h. Refer to the National PC87312 Specification for details of operation of these ports. Table 4-8 Serial I/O Registers Function ISA PCI CPU address address address --------------------------------------------------- Rcvbuff/Xmithold 0000.03F8 0000.03F8 1 C000.7F00 Int Enable 0000.03F9 0000.03F9 1 C000.7F20 Int Ident 0000.03FA 0000.03FA 1 C000.7F40 Line Control 0000.03FB 0000.03FB 1 C000.7F60 Modem Control 0000.03FC 0000.03FC 1 C000.7F80 Line Status 0000.03FD 0000.03FD 1 C000.7FA0 Modem Status 0000.03FE 0000.03FE 1 C000.7FC0 Scratch Pad 0000.03FF 0000.03FF 1 C000.7FE0 Rcvbuff/Xmithold 0000.02F8 0000.02F8 1 C000.5F00 Int Enable 0000.02F9 0000.02F9 1 C000.5F20 Int Ident 0000.02FA 0000.02FA 1 C000.5F40 Line Control 0000.02FB 0000.02FB 1 C000.5F60 Modem Control 0000.02FC 0000.02FC 1 C000.5F80 Line Status 0000.02FD 0000.02FD 1 C000.5FA0 Modem Status 0000.02FE 0000.02FE 1 C000.5FC0 Scratch Pad 0000.02FF 0000.02FF 1 C000.5FE0 --------------------------------------------------- Parallel I/O ------------- A "PC" standard parallel I/O port is provided. It is accessed via ISA addresses 378h through 37Fh. These addresses map into CPU addresses 1 C000.6F00 through 1 C000.6FE0. Table 4-9 Parallel I/O Registers Function ISA PCI CPU address address address ------------------------------------------------ Data Register 0378 0000.0378 1 C000.6F00 Status Register 0379 0000.0379 1 C000.6F20 Control Register 0380 0000.0380 1 C000.7000 ------------------------------------------------ Refer to the National PC87312 chip for programming details. Jumpers allow for the power-on configuration of the port to be set as input or output - this is also programmable. This is provided by a section of the Super I/O chip which connects to the ISA bus. Floppy Disk Controller ---------------------- The Floppy Disk Controller controls one or two drives, it is another section of the National PC87312 I/O chip. It is accessed via ISA addresses 3F0 through 3F7h. These addresses map into CPU addresses 1 C000.7E00 through 1 C000.7FE0. The PC87312 Super I/O chip is set to its "PC/AT mode" by tying the IDENT pin high during power-on reset. IDE Controller -------------- A connector is provided on the system module for the connection of up to two IDE devices within the system enclosure. The IDE interface is provided by another section of the National PC87312 I/O chip. The IDE interface has jumpers to allow it to use either DMA channels six or seven. It interrupts using IRQ14. The DMA IDE function is not currently used and there is no need to fit these jumpers. Table 4-10 IDE DMA Jumper Settings Jumper Position Action ------------------------------------------------------------------ J15,J16 Not Installed DMA Not Supported J15;J16 1-2; 1-2 DMA Request Channel 6;DMA Grant Channel 6 J15;J16 2-3; 2-3 DMA Request Channel 7;DMA Grant Channel 7 J15;J16 Other Illegal Combinations ------------------------------------------------------------------ Utility Bus ----------- The Utility Bus interface created by the System I/O chip connects several common peripheral devices. Keyboard/Mouse -------------- A "PC" standard keyboard and Mouse controller is provided. This is controlled by an 8242 single-chip micro-processor that is accessed via the PCI-ISA bridge chip. Access to the chip is via ISA addresses 060h and 064h. These map into CPU addresses 1 C000.0C00h and 1 C000.0C80h. For an understanding of the keyboard/mouse operation, consult the appropriate 8242 Internal Code Listings. Time Of Year Clock ------------------- A standard Time of Year (TOY) Clock that also has 50 bytes of battery supported RAM is provided. See the Dallas DS1287A documentation for full details. The chip is addressed as a device on the Utility Bus spawned by the ISA bridge chip. It is accessed at ISA addresses 070h and 071h, corresponding to CPU addresses 1 C000.0E00h and 1 C000.0E20h. The first address is used to load an address to the chip from bits<7:0>, the second address is then used to read or write data from/to that loaded address to/from data bits <7:0>. The TOY chip is also the source of a Periodic Interrupt for the CPU. It connects to IRQ[2] on the 21066/68 CPU Chip, bypassing the bridge chip's interrupt controller. For more details refer to the Firmware Specification for Digital AXPpci 33. Non-Volatile RAM ----------------- An 8K x 8 battery supported RAM is provided. Refer to the Dallas DS1285 Specification for full details. This device is addressed as a device on the Utility Bus spawned by the PCI- ISA bridge chip. It is accessed as data bits <7:0> at ISA addresses 800h through 8FFh, corresponding to CPU addresses 1 C001.0000 through 1 C001.1FE0h.