AXPpci 33 : Information for developers ================================================= This information is provided in good faith but no guarantee is made as to its accuracy. This information should be read in conjunction with information contained in the 'Digital AXPpci 33 Alpha PC Motherboard Design Guide' ADDRESS MAP ----------- Address Summary ---------------- The following list shows all addresses used by a standard Digital AXPpci 33 motherboard, grouped by function. Table 8-1 System Address Space Address Use --------------------------------------------------------------- 0 0000.0000 - 0 17FF.FFFF Memory 0 1800.0000 - 0 1FFF.FFFF Unused 0 2000.0000 - 0 37FF.FFFF Non-cacheable shadow copy of memory 0 3800.0000 - 0 387F.FFF8 FlashROM 0 3880.0000 - 0 38FF.FFFF LEDs (0 3880.0000 recommended) 0 3900.0000 - 0 FFFF.FFFF Unused 1 0000.0000 - 1 9FFF.FFFF CPU internal registers 1 A000.0000 - 1 BFFF.FFFF INTACK on read, Special Cycle on write 1 C000 0000 - 1 DFFF FFFF PCI I/O Space 1 E000.0000 - 1 FFFF.FFFF PCI configuration space 2 0000.0000 - 2 FFFF.FFFF PCI Sparse memory 3 0000 0000 - 3 FFFF FFFF PCI Dense Memory --------------------------------------------------------------- CPU Internal Registers: Memory Controller ----------------- Table 8-2 Memory Controller Registers Mnemonic Description CPU Address -------------------------------------- BCR0 Bank Config 0 1 2000.0000 BCR1 Bank Config 1 1 2000.0008 BCR2 Bank Config 2 1 2000.0010 BCR3 Bank Config 3 1 2000.0018 BMR0 Bank Mask 0 1 2000.0020 BMR1 Bank Mask 1 1 2000.0028 BMR2 Bank Mask 2 1 2000.0030 BMR3 Bank Mask 3 1 2000.0038 BTR0 Bank Timing 0 1 2000.0040 BTR1 Bank Timing 1 1 2000.0048 BTR2 Bank Timing 2 1 2000.0050 BTR3 Bank Timing 3 1 2000.0058 GTR Global Timing 1 2000.0060 ESR Error Status 1 2000.0068 EAR Error Address 1 2000.0070 CAR Cache Control 1 2000.0078 --------------------------------------- PCI Bus Control --------------- Table 8-3 PCI Bus Control Registers Mnemonic Description Address ------------------------------------------------------ IOC_HAE Host Address Ext. 1 8000.0000 IOC_CFG Configuration cycle type 1 8000.0020 IOC_STAT[0] Status 0 1 8000.0040 IOC_STAT[1] Status 1 1 8000.0060 IOC_TBIA Translation Buffer 1 8000.0080 Invalidate All IOC_TBEN Translation buffer 1 8000.00A0 enable IOC_PCIRST PCI soft reset 1 8000.00C0 IOC_PCIPAR PCI parity disable 1 8000.00E0 IOC_W_BASE[0] Window Base 0 1 8000.0100 IOC_W_BASE[1] Window Base 1 1 8000.0120 IOC_W_MASK[0] Window Mask 0 1 8000.0140 IOC_W_MASK[1] Window Mask 1 1 8000.0160 IOC_T_BASE[0] Translated Base 0 1 8000.0180 IOC_T_BASE[1] Translated Base 1 1 8000.01A0 IOC_TB_TAG[0] TB Tag 0 1 8100.0000 IOC_TB_TAG[1] TB Tag 1 1 8100.0020 IOC_TB_TAG[2] TB Tag 2 1 8100.0040 IOC_TB_TAG[3] TB Tag 3 1 8100.0060 IOC_TB_TAG[4] TB Tag 4 1 8100.0080 IOC_TB_TAG[5] TB Tag 5 1 8100.00A0 8100.00A0 IOC_TB_TAG[6] TB Tag 6 1 8100.00C0 8100.00C0 IOC_TB_TAG[7] TB Tag 7 1 8100.00E0 ------------------------------------------------------ I/O Devices ------------ ISA Bus Control Table 8-4 ISA Bus Control Registers Device/Register ISA I/O CPU Addresses Addresses ------------------------------------------------------------ Keyboard/Mouse 060 - 064 1 C000.0C00 - 1 C000.0C80 Time of Year Clock 070 - 071 1 C000.0E00 - 1 C000.0E20 Serial Port 1 3F8 - 3FF 1 C000.7F00 - 1 C000.7FE0 Serial Port 2 2F8 - 2FF 1 C000.5F00 - 1 C000.5FE0 Parallel Port 378 - 37F 1 C000.6F00 - 1 C000.6FE0 Floppy Disk 3F0 - 3F7 1 C000.7E00 - 1 C000.7EE0 Controller Non-Volatile RAM 800 - 8FF 1 C001.0000 - 1 C001.1FE0 C00 1 C001.8000 IDE 1F0 - 1F7 1 C000.3E00 - 1 C000.3EE0 3F6 - 3F7 1 C000.7EC0 - 1 C000.7EE0 ------------------------------------------------------------ Memory ------- Plug-in SIMMs occupy contiguous address space, starting at address 0 0000.0000 and extending to a highest value set by the size of the SIMM modules. FlashROM and the LEDs occupy additional memory space, set by the CPU to be non-cacheable, starting at address 0 3800.0000. This address is set by console firmware; it is the first address beyond the largest possible DRAM address. Additionally, bit 29 is set to indicate that the data are not to be cached. Table 8-5 Memory Address Space Address Function ------------------------------------------------------ Bank 0-1 0 0000.0000 - top R/W Cacheable Bank 2 top of memory-0 37FF FFFF Reserved Bank 3 0 3800.0000 - 0 381F.FF80 Reserved Bank 3 0 3820.0000 - 0 383F.FFF8 Reserved Bank 3 0 3840.0000 - 0 385F.FFF8 FlashROM 1 Bank 3 0 3860.0000 - 0 387F.FFF8 FlashROM 2 Bank 3 0 3880.0000 - 0 38FF.FFF8 LEDs -------------------------------------------------------